JP4198899B2 - 3D graphics processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a setup circuit for a 3D graphics processing apparatus.
[0002]
[Prior art]
The 3D graphics processing apparatus includes a setup circuit that calculates a change amount of a parameter with respect to a change amount of a position inside a polygon, and rasterizing, that is, a DDA (Digital Differential Analyzer) that converts a graphic object composed of a vector or a line element into a dot format. ) A processing circuit and a pixel pipeline circuit for obtaining final color information and depth information for each pixel constituting the dot matrix.
[0003]
Of these circuits constituting the 3D graphics processing apparatus, the amount of calculation of the setup circuit increases in proportion to the size of the polygon. In a conventional 3D graphics processing device, a high-precision setup circuit, that is, a setup circuit composed of an arithmetic unit having a large number of bits capable of processing many bits at once is used for a large polygon having a large amount of calculation. I was doing calculations.
[0004]
However, the size of an arithmetic unit having a large number of bits inevitably increases. In this case, of course, the area of the setup circuit also increases. If the area of the setup circuit increases, for example, the size of the chip on which the 3D graphics processing device is formed increases, which causes problems such as an increase in cost.
[0005]
FIG. 11 shows a conventional setup circuit.
[0006]
The setup circuit 11 is based on the vertex coordinates A (x0, y0), B (x1, y1), C (x2, y2) of the polygon and the vertex parameters A (p0), B (p1), C (p2). A change amount (dp / dx, dp / dy) of the parameter with respect to the change amount of the position inside the polygon is obtained. The change amount of the parameter is supplied to the DDA processing circuit 12.
[0007]
The setup circuit 11 includes an adder 1 for obtaining a difference between polygon vertex coordinates, an adder 2 for obtaining a difference between vertex parameters of the polygon, a multiplier 3 for obtaining 1 / e0, an adder 4 and a divider 5, and vertex coordinates. And the difference between the vertex parameters, the adder 7 for adding the output signal of the multiplier 6, the output signal of the adder 7 and 1 / e0 are multiplied, and the position inside the polygon is And a multiplier 8 for obtaining a change amount of the parameter with respect to the change amount.
[0008]
In such a setup circuit 11, the number of bits (or calculation accuracy) of each calculator 1, 2,..., 8 based on the maximum polygon size and parameters (color information, depth information, etc.) determined in advance as specifications. ) Is determined. That is, the number of bits of each of the computing units 1, 2,... 8 constituting the setup circuit 11 is set to the number of bits that can determine dp / dx and dp / dy of the maximum size polygon in one operation. Is done.
[0009]
For example, when the vertex coordinate of the maximum size polygon is represented by 16 bits and the vertex parameter is represented by 8 bits, the adder 1 is 16 bits, the adder 2 is 8 bits, and the multiplier 3 is 16 × 16. Bit, adder 4 is 32 bits, divider 5 is 32 bits, multiplier 6 is 8 × 16 bits, adder 7 is 20 bits, and multiplier 8 is 20 × 32 bits. The calculation accuracy of the calculator is uniquely determined by the number of bits).
[0010]
[Problems to be solved by the invention]
As described above, in the conventional 3D graphics processing apparatus, the number of bits of each arithmetic unit constituting the setup circuit is one calculation of the maximum size polygon dp / dx and dp / dy (throughput = “1”). Was set to the number of bits that can be processed. For this reason, the area (hardware size) of the setup circuit is increased, causing problems such as an increase in cost.
[0011]
The object of the present invention is to propose a 3D graphics processing apparatus capable of ensuring the accuracy of calculating dp / dx and dp / dy of a polygon of the maximum size without maximizing the number of bits of each arithmetic unit constituting the setup circuit. There is to do.
[0012]
The 3D graphics processing apparatus of the present invention includes a setup circuit that calculates a change amount of a parameter with respect to a change amount of a position inside a polygon, a DDA processing circuit that rasterizes an output signal of the setup circuit, and an output of the DDA processing circuit. A pixel pipeline circuit that obtains information related to the pixel based on the signal, and the setup circuit includes N (n is a natural number and N> n) of N (N is a natural number) input data. A bit is monitored, and when all the upper N−n bits have the same value, the first signal is output, and when the upper N−n bits include different values, the second signal is output. When the accuracy change circuit and the input data are inputted and the first signal is received, the calculation of the input data is executed by one operation, and the second When receiving the items, and an arithmetic unit for performing the repetitive operation of a plurality of times an operation of said input data, said set-up circuit The computing unit constituting Is An n-bit type arithmetic unit, and the throughput of the setup circuit is always regardless of the arithmetic accuracy of the arithmetic unit. More than the throughput of the DDA processing circuit Therefore, the input data that is input most frequently to the arithmetic unit is n-bit data. .
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the 3D graphics processing apparatus of the present invention will be described in detail with reference to the drawings.
[0031]
[Overview]
In the 3D graphics processing apparatus, the number of bits of each computing unit constituting the setup circuit is calculated once for the maximum size polygon dp / dx and dp / dy determined as specifications (throughput = “1”). Setting the number of bits that can be processed by the method causes an increase in the area of the setup circuit.
[0032]
By the way, in the 3D graphics processing, the polygon size and parameters are not fixed, but often change. That is, the maximum size polygon is rarely used. Normally, polygons of a predetermined size that is not the maximum are frequently used, and polygons of other sizes are rarely used.
[0033]
Therefore, first, in the 3D graphics processing apparatus of the present invention, the number of bits of each arithmetic unit constituting the setup circuit is set to a predetermined number of polygons dp / dx and dp / dy which are not maximum and are used at a high frequency. The number of bits that can be processed with a throughput (for example, throughput = “1”) is set.
[0034]
In this case, in the conventional 3D graphics processing device, the calculation precision (number of bits) of each calculator in the setup circuit is too low for dp / dx and dp / dy of polygons having a size exceeding a predetermined size. Can't handle.
[0035]
Therefore, in the 3D graphics processing apparatus of the present invention, for polygons having a size exceeding a predetermined size, each arithmetic unit in the setup circuit is repeatedly used (by increasing the arithmetic accuracy of each arithmetic unit). ), Dp / dx and dp / dy.
[0036]
Here, the predetermined throughput means (1) throughput = “1”, or (2) the throughput of the DDA processing circuit that receives the output signal of the setup circuit or a higher throughput.
[0037]
Thereby, it is possible to obtain dp / dx and dp / dy of the polygon of the maximum size without maximizing the number of bits of each arithmetic unit constituting the setup circuit.
[0038]
By the way, in the 3D graphics processing apparatus of the present invention, as described above, the number of times each arithmetic unit is repeatedly used is changed according to the polygon size and parameters. In this case, dp / dx and dp / dy can be obtained with a predetermined throughput (for example, throughput = “1”) for a polygon having a size equal to or smaller than a predetermined size, but the predetermined size requires high calculation accuracy. For polygons that exceed, each computing unit must be used repeatedly to determine dp / dx and dp / dy, reducing the throughput of the setup circuit.
[0039]
However, this is not a problem in a normal 3D graphics processing apparatus.
[0040]
For example, as shown in FIG. 1, the number of bits of each arithmetic unit constituting the setup circuit 11 is such that a small polygon (polygon of a predetermined size used frequently) has a predetermined throughput (for example, a throughput of a DDA processing circuit). Is set to the number of bits that can be processed.
[0041]
In this case, as shown in FIG. 2, when trying to process a polygon having a size larger than the size of the small polygon, the number of times each arithmetic unit in the setup circuit 11 is repeatedly used increases. Time increases and its throughput decreases.
[0042]
However, as shown in FIG. 2, the DDA processing circuit 12 also processes a large polygon, so that the throughput decreases. That is, when processing a polygon of a large size, the throughput in the DDA processing circuit 12 is greatly reduced. Therefore, unless the throughput of the setup circuit 11 is lower than the throughput of the DDA processing circuit 12, the throughput of the setup circuit 11 is reduced. The decline is not a problem.
[0043]
Therefore, for example, even if the number of bits of each arithmetic unit constituting the setup circuit 11 is maximized and the throughput of the setup circuit 11 for a large polygon is “1” (processing is completed in one operation), has no meaning.
[0044]
For this reason, in the 3D graphics processing apparatus of the present invention, the number of bits of each arithmetic unit constituting the setup circuit is not maximized, and dp / d of a polygon of a predetermined size that is used at a high frequency is not maximized. dx and dp / dy are set to the number of bits that can be obtained with a predetermined throughput. For polygons of a larger size, each arithmetic unit in the setup circuit is repeatedly used multiple times (the arithmetic accuracy of each arithmetic unit). Dp / dx and dp / dy are obtained.
[0045]
[First Embodiment]
FIG. 3 shows a setup circuit according to the first embodiment of the present invention.
[0046]
The setup circuit 11 is based on the vertex coordinates A (x0, y0), B (x1, y1), C (x2, y2) of the polygon and the vertex parameters A (p0), B (p1), C (p2). A change amount (dp / dx, dp / dy) of the parameter with respect to the change amount of the position inside the polygon is obtained. The change amount of the parameter is supplied to the DDA processing circuit 12.
[0047]
The setup circuit 11 is a circuit that performs calculations as shown in FIG.
[0048]
That is, there are triangles (polygons) formed by connecting three points A (x0, y0), B (x1, y1), and C (x2, y2). A parameter A (p0), Assume that B (p1) and C (p2) are given. In this case, the change amount (dp / dx, dp / dy) of the parameter with respect to the minute change amount of the position inside the triangle is given by the equations (1) to (3). The setup circuit 11 is a circuit that calculates the amount of change (dp / dx, dp / dy) of this parameter.
[0049]
The setup circuit 11 includes an adder 1A for obtaining a difference in polygon vertex coordinates, an adder 2A for obtaining a difference in polygon vertex parameters, a multiplier 3A for obtaining 1 / e0, an adder 4A and a divider 5A, and vertex coordinates. The multiplier 6A for multiplying the difference between the two and the vertex parameter difference, the adder 7A for adding the output signal of the multiplier 6A, the output signal of the adder 7A and 1 / e0, and multiplying the position inside the polygon A multiplier 8A for obtaining a change amount of the parameter with respect to the change amount.
[0050]
Further, in the present invention, the setup circuit 11 has a calculation accuracy changing circuit 10. The calculation accuracy changing circuit 10 monitors the difference in vertex coordinates (depending on the polygon size) and the difference in vertex parameters, and based on these differences (number of bits of the input signal), the respective arithmetic units 3A, 4A, 5A, The calculation accuracy of 6A, 7A, and 8A is changed.
[0051]
The number of bits of each of the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A is fixed to the number of bits that can process dp / dx and dp / dy of polygons of a predetermined maximum size that are used at a high frequency with a predetermined throughput. Therefore, the calculation accuracy is changed by changing the number of times each of the calculators 3A, 4A, 5A, 6A, 7A, and 8A is repeatedly used. If the number of repeated use of each computing unit 3A, 4A, 5A, 6A, 7A, 8A can be freely changed, the number of bits of each computing unit 3A, 4A, 5A, 6A, 7A, 8A is fixed to a predetermined number of bits. Even so, dp / dx and dp / dy of the maximum size polygon can be obtained.
[0052]
It should be noted that the number of times each of the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A is repeatedly used is determined by the arithmetic accuracy changing circuit 10 and is calculated from the arithmetic accuracy changing circuit 10 via the arithmetic accuracy control line 9. It is transmitted to the arithmetic units 3A, 4A, 5A, 6A, 7A, 8A.
[0053]
In this case, for example, when the polygon size is small, the setup circuit 11 only needs to have low accuracy. For example, the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A are moved only once. Thus, dp / dx and dp / dy can be calculated. The throughput of the setup circuit 11 at this time is “1”.
[0054]
Further, for example, when the polygon size is large, the setup circuit 11 is required to have high accuracy. Therefore, by changing each of the computing units 3A, 4A, 5A, 6A, 7A, and 8A repeatedly, the parameter change The quantity (dp / dx, dp / dy) can be calculated. However, the throughput of the setup circuit 11 at this time decreases.
[0055]
As described above, according to the setup circuit of the present invention, the number of bits of each of the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A is dp / dx and dp of polygons of a predetermined maximum size that are frequently used. / Dy is fixed to the number of bits that can be processed with a predetermined throughput. That is, the number of bits of each of the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A is not fixed to the maximum number of bits that can process dp / dx and dp / dy of the polygon of the maximum size with the throughput “1”. The area of the circuit 11 is not increased, and an increase in cost can be suppressed.
[0056]
For example, in the setup circuit 11 of the present invention, when the vertex coordinate of the maximum size polygon is represented by 16 bits and the vertex parameter is represented by 8 bits, the multiplier 3A is 8 × 8 bits and the adder 4A is 8 bits. The bit / divider 5A is set to 8 bits, the multiplier 6A is set to 8 × 8 bits, the adder 7A is set to 8 bits, and the multiplier 8A is set to 8 × 8 bits.
[0057]
In this case, in the conventional case (FIG. 11), the multiplier 3 is 16 × 16 bits, the adder 4 is 32 bits, the divider 5 is 32 bits, the multiplier 6 is 8 × 16 bits, and the adder 7 is 20 bits, and the multiplier 8 is 20 × 32 bits. Therefore, according to the setup circuit 11 of the present invention, it can be seen that the circuit area can be greatly reduced.
[0058]
On the other hand, in the setup circuit 11 of the present invention, the calculation accuracy of each of the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A is changed by the number of times the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A are used repeatedly. This is done by changing In this case, the larger the polygon size, the greater the number of times each of the computing units 3A, 4A, 5A, 6A, 7A, and 8A is repeatedly used, and the throughput decreases.
[0059]
However, a decrease in throughput due to an increase in polygon size is not a problem unless the throughput of the DDA processing apparatus is lower than that described above.
[0060]
FIG. 5 shows an example of the calculation accuracy changing circuit.
[0061]
The arithmetic accuracy changing circuit 10 can be configured by a combination of simple logic circuits, for example, an AND circuit, a NOR circuit, and an OR circuit. For example, when the vertex coordinate or vertex parameter is 16 bits, the value of the upper 8 bits of the 16-bit output signal (difference) output from the adders 2 and 3 in FIG. 3 is monitored.
[0062]
When these upper 8 bits are all the same value (“0” or “1”), since these upper 8 bits are not used, it is determined that the size of the polygon is small, and the output signal of the OR circuit is “1”. In this case, since the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A in FIG. 3 operate only once, the calculation accuracy of the setup circuit is lowered, but the throughput is “1”.
[0063]
On the other hand, if these upper 8 bits are not all the same value (“0” or “1”), since these upper 8 bits are used, it is determined that the size of the polygon is large, and the output signal of the OR circuit Becomes “0”. In this case, each of the computing units 3A, 4A, 5A, 6A, 7A, and 8A shown in FIG. 3 operates repeatedly a plurality of times, so that the calculation accuracy of the setup circuit increases but the throughput decreases.
[0064]
FIG. 6 is a block diagram showing only the multiplier 3A and the adder 4A in FIG. A conventional block diagram corresponding to this block diagram is shown in FIG. 6 and 7, the number of bits of the multiplier 3A of the present invention is ½ of the number of bits of the conventional multiplier 3, and the adder 4A of the present invention The number of bits is ½ of the number of bits of the conventional adder 4.
[0065]
In general, the area of the multiplier and adder is tripled when the number of bits is doubled. Therefore, in the setup circuit of the present invention, the size of the multiplier is 1/3 of the conventional size, and the size of the adder is 1/3 of the conventional size. In the setup circuit of the present invention, the number of bits of the multiplier 3A and the adder 4A is smaller than the number of bits of the conventional multiplier 3 and the adder 4, but the multiplier 3A and the adder 4A are repeated a plurality of times. By operating, the calculation accuracy can be increased.
[0066]
FIG. 8 is a flowchart showing the operation of the setup circuit.
[0067]
First, the calculation accuracy changing circuit determines the calculation accuracy required for each calculator based on the difference in vertex coordinates or the difference in vertex parameters. Then, from this calculation accuracy, the number of repetition operations (the number of loops) of each calculator necessary for calculating the change amount of the parameter with respect to the change amount of the position in the polygon is determined (steps ST1 and ST2).
[0068]
This number of loops is transmitted to each arithmetic unit. Each arithmetic unit sets a loop variable based on the number of loops. The loop variable is set to N + 1 when the number of loops is N (N is a natural number) (step ST3).
[0069]
Thereafter, the first calculation is performed, and after the calculation is completed, the loop variable is decreased by “1” (steps ST4 to ST5). It is checked whether or not the loop variable is “0”. If it is “0” (the number of loops is “0”), the arithmetic operation in each arithmetic unit is terminated (step ST6). If the loop variable is not “0”, the second calculation is performed, and after the calculation is completed, the loop variable is decreased by “1” (steps ST4 to ST5).
[0070]
Then, the operations in steps ST4 to ST6 are repeated until the loop variable becomes “0”.
[0071]
In the setup circuit of the present invention, since the number of bits of each arithmetic unit is set small, the area is small. Further, when the calculation accuracy of each calculator may be low, for example, the loop variable is set to “1” and the calculation process is performed with high throughput. For each arithmetic unit, when a high calculation accuracy is required, the loop variable is set to a large value to ensure the required calculation accuracy. In this case, the throughput decreases as the loop variable increases.
[0072]
[Second Embodiment]
FIG. 9 shows a part of a setup circuit according to the second embodiment of the present invention.
[0073]
This example relates to a modified example of a computing unit including a part surrounded by a dotted line in the setup circuit of FIG. 3, that is, two multipliers and one adder.
[0074]
Each multiplier is an 8 × 8 bit type, and a selector is arranged in the preceding stage. The selector selects one of the two input data (16 bits each), and transfers the selected input data to the multiplier. The adder is a 16-bit type, and a circuit including a selector and a register is arranged in the subsequent stage.
[0075]
The controller 21 sets a loop variable based on a signal representing the number of loops output from the calculation accuracy changing circuit. The controller 21 controls the selector based on the value of the loop variable and determines whether or not to feed back the output data of the adder as its input data.
[0076]
When calculation processing is possible with the loop count “0” (loop variable “1”), the calculation accuracy is low, but the throughput is “1”. When the calculation process is performed with the number of loops “3” (loop variable “4”), the calculation accuracy is high, but the low-order x low-order, high-order x low-order, low-order high-order, high-order high-order calculation of the input data Since this must be done, the throughput is "1/4".
[0077]
Even in such a 3D graphics processing apparatus, since it is possible to calculate dp / dx and dp / dy of the polygon of the maximum size without maximizing the number of bits of each arithmetic unit constituting the setup circuit, the manufacturing cost is reduced. Can be realized.
[0078]
[Third Embodiment]
FIG. 10 shows a setup circuit according to the third embodiment of the present invention.
[0079]
This example relates to a modification of the calculation accuracy changing circuit.
[0080]
In the setup circuit of FIG. 3, the calculation accuracy (number of loops) of each arithmetic unit is determined based on the difference in vertex coordinates and the difference in vertex parameters, but in the setup circuit of this example, the calculation accuracy ( The number of loops) is determined based only on the vertex coordinate difference.
[0081]
In determining the calculation accuracy (number of loops) of each calculator, at least one difference among the plurality of vertex coordinate differences may be monitored.
[0082]
Naturally, in the setup circuit of FIG. 3, it is only necessary to monitor at least one difference among a plurality of vertex coordinate differences and at least one difference among a plurality of vertex parameter differences.
[0083]
The setup circuit 11 is based on the vertex coordinates A (x0, y0), B (x1, y1), C (x2, y2) of the polygon and the vertex parameters A (p0), B (p1), C (p2). A change amount (dp / dx, dp / dy) of the parameter with respect to the change amount of the position inside the polygon is obtained. The change amount of the parameter is supplied to the DDA processing circuit 12. The setup circuit 11 performs calculations as shown in FIG.
[0084]
The setup circuit 11 includes an adder 1A for obtaining a difference in polygon vertex coordinates, an adder 2A for obtaining a difference in polygon vertex parameters, a multiplier 3A for obtaining 1 / e0, an adder 4A and a divider 5A, and vertex coordinates. The multiplier 6A for multiplying the difference between the two and the vertex parameter difference, the adder 7A for adding the output signal of the multiplier 6A, the output signal of the adder 7A and 1 / e0, and multiplying the position inside the polygon A multiplier 8A for obtaining a change amount of the parameter with respect to the change amount.
[0085]
Further, in the present invention, the setup circuit 11 has a calculation accuracy changing circuit 10. The calculation accuracy changing circuit 10 monitors the difference between the vertex coordinates, and changes the calculation accuracy of each of the calculators 3A, 4A, 5A, 6A, 7A, and 8A based on the difference.
[0086]
The number of bits of each of the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A is fixed to the number of bits that can process dp / dx and dp / dy of polygons of a predetermined maximum size that are used at a high frequency with a predetermined throughput. Therefore, the calculation accuracy is changed by changing the number of times each of the calculators 3A, 4A, 5A, 6A, 7A, and 8A is repeatedly used. If the number of repeated use of each computing unit 3A, 4A, 5A, 6A, 7A, 8A can be freely changed, the number of bits of each computing unit 3A, 4A, 5A, 6A, 7A, 8A is fixed to a predetermined number of bits. Even so, dp / dx and dp / dy can be obtained for the maximum size polygon.
[0087]
It should be noted that the number of times each of the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A is repeatedly used is determined by the arithmetic accuracy changing circuit 10 and is calculated from the arithmetic accuracy changing circuit 10 via the arithmetic accuracy control line 9. It is transmitted to the arithmetic units 3A, 4A, 5A, 6A, 7A, 8A.
[0088]
As described above, according to the setup circuit of the present invention, the number of bits of each of the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A is dp / dx and dp of polygons of a predetermined maximum size that are frequently used. / Dy is fixed to the number of bits that can be processed with a predetermined throughput. That is, the number of bits of each of the arithmetic units 3A, 4A, 5A, 6A, 7A, and 8A is not fixed to the maximum number of bits for processing with the maximum size polygon dp / dx and dp / dy throughput “1”. The area of the setup circuit 11 does not increase, and an increase in cost can be suppressed.
[0089]
In the setup circuit 11 of the present invention, the calculation accuracy of each of the arithmetic units 3A, 4A, 5A, 6A, 7A, 8A is changed by the number of times each of the arithmetic units 3A, 4A, 5A, 6A, 7A, 8A is used repeatedly. This is done by changing In this case, the larger the polygon size, the greater the number of times each of the computing units 3A, 4A, 5A, 6A, 7A, and 8A is repeatedly used, and the throughput decreases.
[0090]
However, a decrease in throughput due to an increase in polygon size is not a problem unless the throughput of the DDA processing apparatus is lower than that described above.
[0091]
[Others]
The present invention is most effective when applied to a setup circuit of a 3D graphics processing apparatus, but the principle of the present invention can also be applied to other arithmetic circuits.
[0092]
【The invention's effect】
As described above, according to the present invention, it is possible to calculate dp / dx and dp / dy of a polygon of the maximum size without maximizing the number of bits of each arithmetic unit constituting the setup circuit. 3D graphics processing apparatus can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a system including a setup circuit of the present invention.
FIG. 2 is a diagram showing an example of a system including a setup circuit of the present invention.
FIG. 3 is a diagram showing a setup circuit according to the first embodiment of the present invention.
FIG. 4 is a diagram for explaining a calculation performed by a setup circuit.
FIG. 5 is a diagram illustrating an example of a calculation accuracy changing circuit.
FIG. 6 is a diagram showing a circuit for obtaining e0 of the present invention.
FIG. 7 is a diagram showing a conventional circuit for obtaining e0.
FIG. 8 is a diagram showing the operation of the setup circuit of the present invention.
FIG. 9 is a diagram showing a part of a setup circuit according to a second embodiment of the present invention.
FIG. 10 is a diagram showing a setup circuit according to a third embodiment of the present invention.
FIG. 11 is a diagram showing a part of a conventional setup circuit.
[Explanation of symbols]
1, 1A, 2, 2A, 4, 4A, 7, 7A: adder,
3, 3A, 6, 6A, 8, 8A: a multiplier,
5, 5A: Divider,
9: Calculation accuracy control line,
10: Calculation accuracy changing circuit,
11: Setup circuit,
12: DDA processing circuit,
13: Pixel pipeline circuit,
21: Controller.

Claims (1)

A setup circuit for calculating a change amount of a parameter with respect to a change amount of a position inside a polygon, a DDA processing circuit for rasterizing an output signal of the setup circuit, and a pixel for obtaining information on a pixel based on an output signal of the DDA processing circuit A pipeline circuit,
The setup circuit is
If the upper N−n (n is a natural number and satisfies N> n) bits of N (N is a natural number) input data is monitored and all the upper N−n bits have the same value, When one signal is output and the upper N−n bits include different values, a calculation accuracy changing circuit that outputs a second signal, and when the input data is input and the first signal is received, the input An arithmetic unit that performs an operation of data by a single operation and receives the second signal, and performs an operation of the input data by a plurality of repetitive operations;
The arithmetic unit constituting the setup circuit is an n-bit type arithmetic unit,
Throughput of the set-up circuit, regardless of the operation accuracy of said arithmetic unit, Ri always throughput or der of the DDA processing circuit,
3. The 3D graphics processing apparatus according to claim 1, wherein the input data input most frequently to the computing unit is n-bit data .

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