JP4199430B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for improving traceability in a semiconductor integrated circuit device, and more particularly to a technique effective when applied to shortening the test time of additional information written to improve traceability.
[0002]
[Prior art]
Generally, a semiconductor device such as a semiconductor integrated circuit device is provided with a relatively simple display such as a product type name by a marking method such as an ink printing method or a laser marking method. Such a display may include abbreviated product manufacturing time information and product lot information.
[0003]
Certain types of semiconductor integrated circuit devices are given specific information or additional information with a larger amount of information so as to enable more precise product management. That is, such specific information or additional information makes it possible to clarify the details of the product manufacturing history, for example, depending on the amount of information. Accordingly, the analysis including the history trace when the trouble of the semiconductor integrated circuit device occurs is facilitated. Such specific information or additional information is within the scope of technology for ensuring traceability of a semiconductor integrated circuit device.
[0004]
The specific information or additional information is written on a semiconductor chip or the like so as to be electrically readable.
[0005]
As a technique for recording additional information or the like on a semiconductor chip, as shown in Japanese Patent Laid-Open No. 04-111438, a plurality of fuses are formed on the semiconductor chip and additional information is stored by cutting arbitrary fuses. Alternatively, as disclosed in Japanese Patent Application Laid-Open No. 07-307257, there is a method in which a recording area composed of nonvolatile memory cells is formed in a semiconductor chip and additional information is stored in these memory cells.
[0006]
[Problems to be solved by the invention]
Specific information as described above needs to be checked to see if it was optimally written after it was written. Such a check may be performed independently, but it is more preferable that the check be performed at the time of a so-called function test for confirming whether the semiconductor integrated circuit device operates according to a predetermined function. That is, these tests or checks can use the same function test under the same test stage.
[0007]
However, the present inventors have found that the specific information confirmation technique in the semiconductor integrated circuit device as described above has the following problems.
[0008]
For example, when the code of the month in which the semiconductor wafer is manufactured is written on the semiconductor chip as one of the specific information, the tester can test the semiconductor chip for each month code from January to December. Twelve types of expected value patterns or function test programs are required. As a result, there is a problem that costs and man-hours increase.
[0009]
In addition, when semiconductor chips with different manufacturing months are mixed during the above-mentioned test, the test program must be changed to an appropriate test program for each manufacturing month for each semiconductor chip with a different manufacturing month. There is a risk of mistakes.
[0010]
Furthermore, when the number of bits of specific information is increased in order to improve traceability, the expected value pattern also increases, the test time becomes longer, and the manufacturing efficiency of the semiconductor integrated circuit device decreases. There is a problem.
[0011]
An object of the present invention is to provide a semiconductor integrated circuit device capable of confirming whether additional information is written correctly and easily in a short time even when the amount of specific information for improving traceability increases. Place It is to provide.
[0012]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0013]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
[0014]
That is, the semiconductor integrated circuit device of the present invention includes an information storage unit that stores specific information and error detection information that enables detection of an error in the specific information, and the specific information stored in the information storage unit and the error detection. An information inspection unit that inspects specific information by referring to the information.
[0015]
The specific information stored in the information storage unit is preferably digital data composed of a plurality of bits, the error detection information is a parity bit added to the specific information, and the information check unit includes the specific information and It comprises a parity check circuit that receives error detection information.
[0016]
Furthermore, the information storage unit is composed of a nonvolatile memory.
[0017]
The nonvolatile memory is composed of a fuse. When the semiconductor integrated circuit device has a configuration having a semiconductor memory and a redundant circuit for relieving a defect thereof, in other words, when having a specific circuit and a setting circuit for the specific circuit, the nonvolatile memory for the information storage unit And the setting elements for the setting circuit preferably have substantially the same structure. Specifically, when the setting element in the redundant circuit for the semiconductor memory is constituted by a defect repairing fuse, the nonvolatile memory is also constituted by a fuse. More preferably, the specific information fuse circuit is provided in the relief fuse.
[0018]
Further, preferably, the specific information fuses are linearly arranged in the same row as the relief fuses.
[0019]
The parity check circuit is formed in the vicinity of the relief fuse circuit.
[0020]
Further, the specific information composed of the plurality of bits is made into a plurality of groups for each bit unit, and a parity bit is provided for each group.
[0021]
Furthermore, the present invention is connected with A method of manufacturing a semiconductor integrated circuit device includes: an information storage unit that stores specific information and error detection information that enables detection of an error in the specific information; and the specific information and error detection information stored in the information storage unit. A semiconductor integrated circuit device provided with an information inspection unit for inspecting specific information by referring to the manufacturing method including the following steps:
(A) storing specific information and error detection information in an information storage unit;
(B) A step in which the information inspection unit inspects the content of the specific information from the specific information stored in the information storage unit and the error detection information.
[0022]
Furthermore, the present invention is connected with A manufacturing method of a semiconductor integrated circuit device replaces a defective bit with a redundant bit by setting or processing a fuse for repair, and a repair fuse circuit for the redundant circuit, specific information set by the fuse, and the specific information An information storage unit that stores parity bits that enable detection of errors, and an information inspection unit that performs parity check from specific information and parity bits stored in the information storage unit and inspects the specific information In the semiconductor integrated circuit device in which the relief fuse circuit and the information storage unit are arranged in substantially the same region, the manufacturing method includes the following steps:
(A) When the memory circuit is tested, if the memory circuit is defective, the repair fuse of the repair fuse circuit is subjected to fuse processing, redundancy repair is performed, and a specific information fuse is set by fuse setting. Writing information, as well as parity bits;
(B) A step in which the information checking unit performs the parity check of the specific information written in the information storage unit and the parity bit, and checks the specific information.
[0023]
As described above, whether the specific information stored in the information storage unit is correct can be tested in a short time and with high accuracy, and the test cost of the semiconductor integrated circuit device can be reduced.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0025]
FIG. 1 is a layout diagram of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a layout explanatory diagram of a redundant fuse relief unit provided in the semiconductor integrated circuit device of FIG. FIG. 4 is a plan view of a fuse provided in the additional information fuse circuit of the redundant fuse relief section of FIG. 2, FIG. 4 is a cross-sectional view of the fuse of FIG. 3, taken along line AB, and FIG. 5 is the semiconductor integrated circuit device of FIG. 6 is an explanatory diagram showing an example of the additional information writing layout of FIG. 5, and FIG. 7 is an explanatory diagram of parity check of the additional information written in the semiconductor integrated circuit device of FIG. FIG. 8 is a flowchart for explaining an inspection process in the semiconductor integrated circuit device of FIG.
[0026]
In the present embodiment, the semiconductor integrated circuit device 1 is a so-called logic embedded DRAM (Dynamic Random Access Memory) having a large number of I / Os (Input / Output).
[0027]
The semiconductor integrated circuit device 1 includes DRAM macros 2 to 9, a parity check logic unit (information check unit, parity check logic circuit) 10, and a logic circuit, which are laid out as shown in FIG.
[0028]
The DRAM macros 2 to 9 are circuit blocks that each function as a DRAM. The parity check logic unit 10 is a logic circuit that performs parity check on additional information (specific information) VB, which is information for improving the traceability of the semiconductor integrated circuit device 1, and is configured by, for example, an exclusive OR circuit (EOR). Has been.
[0029]
The logic circuit includes a logic control unit such as a microprocessor that controls all of the control in the semiconductor integrated circuit device 1 and a memory unit 11 that temporarily stores input / output data.
[0030]
The layout configuration of the semiconductor chip CH in the semiconductor integrated circuit device 1 will be further described below.
[0031]
In the semiconductor chip CH, for example, a semiconductor element is formed on a semiconductor substrate such as single crystal silicon. As shown in FIG. 1, four DRAM macros 2 to 5 are formed above the semiconductor chip CH. ing. Further, four DRAM macros 6 to 9 are formed below the semiconductor chip CH.
[0032]
Further, redundant fuse relief portions (relief fuse circuits) 12 to 19 are formed at predetermined positions of the DRAM macros 2 to 9. Redundant fuse relief units 12 and 13 are formed adjacent to lower portions of DRAM macros 2 and 3, respectively. Similarly, the redundant fuse relief portions 14 and 15 are formed adjacent to the lower portions of the DRAM macros 4 and 5, respectively.
[0033]
Further, the redundancy fuse relief units 16 and 17 and the redundancy fuse relief units 18 and 19 are formed adjacent to the upper portions of the DRAM macros 6 and 7 and the DRAM macros 8 and 9, respectively.
[0034]
The redundant fuse relief units 12 to 19 are provided with a plurality of relief fuses, and correspond to the defective portions in order to rescue the memory cells or lines that have become defective due to the defects by replacing them with spare lines. Used as a programming means for assigning addresses to spare parts.
[0035]
Further, the redundant fuse relief units 12 to 19 are provided with additional information fuse circuits (information storage units) 20 to 27 for storing the additional information VB, respectively.
[0036]
Near the center of the semiconductor chip CH, an I / O unit 28 provided in the DRAM macros 2 to 5 and an I / O unit 29 provided in the DRAM macros 6 to 9 are provided.
[0037]
The memory unit 11 includes, for example, nine memories 11a to 11i, and the memories 11a to 11h include SRAM (Static Random Access Memory).
[0038]
The memory 11a is provided in the center of the semiconductor chip CH between the I / O unit 28 and the I / O unit 29. The memories 11b to 11e are adjacent to the I / O unit 28 and are connected to the DRAM macro 2. It is formed in the vicinity of ˜5. The memories 11f to 11i are formed adjacent to the I / O unit 29 and in the vicinity of the DRAM macros 6 to 9, respectively.
[0039]
The parity check logic unit 10 includes four parity check logic circuits 10a to 10d. The parity check logic circuits 10a to 10d receive the digital data of the additional information VB written in the additional information fuse circuits 20 to 27. Perform exclusive OR operation and output as 1-bit check data.
[0040]
Here, the layout of the redundant fuse relief unit 12 provided in the DRAM macro 2 will be described.
[0041]
As shown in FIG. 2, the redundant fuse relief unit 12 includes six relief fuse circuits 12 arranged upward. ₁ ~ 12 ₆ The six relief fuse circuits 12 are also formed below. ₇ ~ 12 ₁₂ Is formed.
[0042]
Rescue fuse circuit 12 ₁ ~ 12 _Three , 12 _Five , 12 ₆ Are provided with 30 relief fuses, respectively, and a relief fuse circuit 12 is provided. ₇ ~ 12 ₁₂ Each is provided with 22 relief fuses.
[0043]
Then, the relief fuse circuit 12 _Four 30 fuses are also provided. Of these 30 fuses, 23 are relief fuses, and the remaining 7 fuses F (FIG. 3) constitute the additional information fuse circuit 20. Yes. Therefore, 7-bit additional information VB is written in the additional information fuse circuit 20.
[0044]
These relief fuse circuits 12 ₁ ~ 12 ₆ , 12 ₇ ~ 12 ₁₂ The relief fuses are formed in a line in the vertical direction of FIG. Also, the relief fuse circuit 12 _Four The seven fuses F are also formed in the same column as the 23 relief fuses.
[0045]
Accordingly, the fuse F of the additional information fuse circuit 20 can be fuse-processed in the process of fuse-processing the relief fuse, and alignment of the laser beam or the like during the fuse process can be easily performed.
[0046]
In FIG. 2, the redundancy fuse relief unit 12 provided in the DRAM macro 2 has been described. However, the redundancy fuse relief units 13 to 19 provided in the DRAM macros 3 to 9 have the same configuration, and additional information is provided. The fuse circuits 21 to 27 are each provided with seven fuses F.
[0047]
Therefore, it is possible to write a total of 56 bits of additional information VB in the additional information fuse circuits 20 to 27. Of the 56 bits of additional information VB, the lower one bit is a parity bit (error detection information). ) Written as PB.
[0048]
As described above, the configuration in which the additional information VB is distributed and arranged in the redundant fuse relief units 12 to 19 of the DRAM macros 2 to 9 makes it possible to appropriately use the fuse relief unit area. Unlike the case where the fuses for the additional information VB are concentratedly arranged at a specific location, this distributed arrangement does not require a significant change in the layout of a plurality of DRAM macros and logic circuits. This feature is advantageous in that, for example, a subtle change in the operation timing of each DRAM macro can be avoided.
[0049]
The fuse F used in the additional information fuse circuit 20 (-27) will be described.
[0050]
The fuse F is not particularly limited, but is a fusing type fuse. The fusing type fuse is processed by fusing energy such as a laser beam. As shown in FIGS. 3 and 4, the fuse F includes a semiconductor device, a wiring layer, and the like, and an insulating film Z1 made of silicon nitride (Si—N) or the like and an insulating film Z2 made of polyimide or the like on the top. It is formed in the uppermost wiring layer H of the formed semiconductor substrate.
[0051]
The uppermost wiring layer includes a gold (Au) wiring H1, a nickel (Ni) wiring H2, and a chrome (Cr) wiring H3 from the top to the bottom.
[0052]
One connection portion of the fuse F is connected to a power supply wiring supplied with a power supply voltage formed in the lower aluminum wiring layer via a contact hole C1 made of tungsten or the like, for example. The other connecting portion is connected to a predetermined signal wiring formed in the aluminum wiring layer through a contact hole C2.
[0053]
The fuse F is formed only by the chrome wiring H3, and the gold wiring H1 and the nickel wiring H2 are not formed. Thereby, the fuse F can be easily cut.
[0054]
Next, with respect to the inspection process of the semiconductor integrated circuit device 1 according to the present embodiment, FIG. 1, FIG. 2 and FIG. 5 are explanatory diagrams of the additional information, FIG. The parity check will be described with reference to an explanatory diagram and a flowchart of FIG.
[0055]
First, a logic test for measuring a logic function such as a microprocessor provided in a logic circuit in the semiconductor integrated circuit device 1 and electrical characteristics is performed using a logic tester or the like (step S101). (Step S102), the semiconductor integrated circuit device 1 is selected into a defective product and a non-defective product.
[0056]
Thereafter, an SRAM memory test in the memory unit 11 is performed using a memory tester or the like (step S103), and it is determined whether or not the memory unit 11 has a defect (step S104). The device 1 is selected.
[0057]
Thereafter, in the non-defective semiconductor integrated circuit device 1, the DRAM memory test in the memory devices of the DRAM macros 2 to 9 is performed by the memory tester (step S105).
[0058]
When the memory device has a defect, redundant relief is performed by cutting any relief fuse provided in the redundancy fuse relief sections 12 to 19 with, for example, a laser beam (step S106).
[0059]
At the time of this redundant relief, the fuse F of the additional information fuse circuits 20 to 27 is cut at the same time, and arbitrary additional information VB is written. This eliminates the need for a new process by writing the additional information VB, and allows the additional information VB to be written efficiently.
[0060]
Here, the additional information VB will be described.
[0061]
As shown in FIG. 5, the additional information VB includes, for example, a format code, a wiring start year, a wiring lot month code, a wiring lot number, a wiring lot number suffix, a wafer number, a chip address (X), a chip address (Y), And timing trimming.
[0062]
The format code is a code that defines the writing order of items to be written as additional information VB, and 2 bits are allocated. The wiring start year is a code indicating the start year of the wiring lot by the last digit of the year, and 3 bits are assigned. In addition, in this wiring start year information, not only the start year but also the number of bits to be allocated may be increased to indicate the start date of the wiring lot.
[0063]
The wiring lot month code is a code indicating the monthly lot of the semiconductor wafer, and 4 bits are allocated. The wiring lot number is, for example, a code indicating a semiconductor wafer lot consisting of a 4-digit decimal lot number, and 14 bits are assigned thereto.
[0064]
The wiring lot number suffix is a code indicating the number of times the memory tests of the DRAM macros 2 to 9 are performed, and 5 bits are allocated. The wafer number is a number assigned to the semiconductor wafer in each lot, and 5 bits are assigned.
[0065]
Furthermore, the chip address (X) and the chip address (Y) are position data indicating the X coordinate and the Y coordinate in each semiconductor chip CH on the semiconductor wafer, and 4 bits are assigned to each.
[0066]
Therefore, 49 bits out of 56 bits provided in the additional information fuse circuits 20 to 27 are used for the additional information VB, and the other 1 bit is used as the parity bit PB.
[0067]
Further, FIG. 6 shows an example of writing the additional information VB.
[0068]
FIG. 6 shows seven fuses F for writing additional information VB provided in the additional information fuse circuits 20 to 27 of the DRAM macros 2 to 9, respectively, from the left side to the right side of FIG. Each is written as additional information VB.
[0069]
Trimming information in which the clock phase of the DRAM clock is adjusted is written in Bit 4 and Bit 5 of the additional information fuse circuit 20 in the DRAM macro 2. Trimming information adjusted for the local clock is written in Bit 6 of the additional information fuse circuit 20 and Bit 0 of the additional information fuse circuit 21.
[0070]
Trimming information in which the clock phase of the DRAM macro is adjusted is written in Bit 1 and Bit 2 of the additional information fuse circuit 21 in the DRAM macro 3, and the clock of the SRAM pulse is written in Bit 3 and Bit 4 of the additional information fuse circuit 21. Trimming information with phase adjusted is written.
[0071]
A format code is written in Bit 5 and Bit 6 of the additional information fuse circuit 21, and a wiring start year is written in Bit 0 to Bit 2 of the additional information fuse circuit 22 in the DRAM macro 4.
[0072]
Further, a wiring lot month code is written in Bit 3 to Bit 6 of the additional information fuse circuit 22. Wiring lot numbers are written in Bit 0 to Bit 6 of the additional information fuse circuit 23 in the DRAM macro 5 and Bit 0 to Bit 6 of the additional information fuse circuit 24 in the DRAM macro 6.
[0073]
Wiring lot number suffixes are written in Bit 0 to Bit 4 of the additional information fuse circuit 25 in the DRAM macro 7, and Bit 5 and Bit 6 of the additional information fuse circuit 25, and Bit 0 to Bit 2 of the additional information fuse circuit 26 in the DRAM macro 8. Has a wafer number written therein.
[0074]
The X coordinate chip address is written in Bit 3 to Bit 6 of the additional information fuse circuit 26, and the Y coordinate chip address is written in Bit 0 to Bit 3 of the additional information fuse circuit 27 in the DRAM macro 9. A parity bit PB for performing a parity check is written in Bit 4 of the additional information fuse circuit 27.
[0075]
When the redundancy repair in the process of step S106 is completed, it is determined whether or not the DRAM macros 2 to 9 are defective (step S107), and the semiconductor integrated circuit device 1 is selected.
[0076]
Thereafter, a function test of the semiconductor integrated circuit device 1 is performed (step S108), and it is determined whether or not the semiconductor integrated circuit device 1 has a defect (step S109).
[0077]
This function test is a test for confirming whether or not the semiconductor integrated circuit device 1 operates according to a predetermined function. A test pattern is sequentially applied to an input terminal, and a pattern appearing at an output terminal is as expected. Perform a comparison check.
[0078]
Thereafter, a parity check of the additional information VB is performed (step S110), and it is checked whether or not the additional information VB is correctly written (step S111). In this case, since it is confirmed whether the additional information VB is correctly written by the parity check, even the additional information VB having a large number of bits can be efficiently and easily confirmed in a short time.
[0079]
Here, a confirmation test technique in the parity check of the additional information VB will be described.
[0080]
In the semiconductor integrated circuit device 1, as shown in FIG. 7, latches L are respectively connected to the fuses F of the additional information fuse circuits 20 to 27 provided in the DRAM macros 2 to 9.
[0081]
In these latches L, “1” (high level) is written when the fuse F is cut, and “0” (low level) is written when the fuse F is not cut.
[0082]
The latch L is connected to the parity check logic unit 10 that performs the parity check via the latch LP. The parity check logic unit 10 performs an exclusive OR operation on the input additional information VB and the parity bit PB to perform a parity check.
[0083]
When the parity check by the parity check logic unit 10 is completed, a 1-bit check signal after the parity check is output to the tester TE via the output buffer B1, and it is determined whether or not the additional information VB is correct.
[0084]
The latch LP is a boundary scan latch, and can perform a shift register operation at the time of failure analysis or the like, and read the additional information VB via the buffer B2.
[0085]
In step S110, the non-defective semiconductor integrated circuit device 1 determined to have the additional information VB written correctly by the parity check is shipped (step S112).
[0086]
Thereby, in the present embodiment, the additional information VB written in the additional information fuse circuits 20 to 27 of the semiconductor integrated circuit device 1 is confirmed by a parity check, thereby greatly reducing the test time of the additional information VB. can do.
[0087]
Further, since the additional information VB having a large number of bits can be tested in a short time, the amount of the additional information VB can be increased, the traceability of the semiconductor integrated circuit device 1 can be further improved, and failure analysis can be performed. It can be carried out easily and in a short time.
[0088]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0089]
For example, in the above-described embodiment, the parity bit PB is added to the least significant bit of the additional information. Even in this embodiment, sufficient checking is possible if the level of the fuse programming technique is followed, but it is determined as normal as a result of the parity check despite an error such as a 2-bit error. If it is necessary to avoid this, as shown in FIG. 9, the additional information VB may be divided for each bit, and a parity bit PB may be provided for each divided bit.
[0090]
Thereby, even when the number of bits of the additional information VB is greatly increased in order to improve traceability, it is possible to confirm the writing of the additional information VB with high accuracy only by the parity check.
[0091]
The fuse may be a fuse that changes from a substantially interrupted state to a connected state by a fuse process called an antifuse instead of a blown fuse.
[0092]
Further, according to the embodiment, the additional information and the parity bit are written to the additional information fuse circuit provided in the relief fuse circuit. However, the additional information and the parity bit are written other than the fuse. Alternatively, for example, an additional information storage unit including a nonvolatile semiconductor memory may be provided, and the additional information and the parity bit may be stored in the additional information storage unit.
[0093]
Further, in the above embodiment, a parity bit is added to the written additional information to check the parity. However, information having the same content as the additional information or inversion information complementary thereto is stored as error detection information. When checking the additional information, the additional information and the error detection information may be read, and the additional information or its inverted information may be compared with the error detection information.
[0094]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.
[0095]
(1) Whether the additional information stored in the additional information storage unit is correct can be tested in a short time and with high accuracy, and the test cost can be reduced.
[0096]
(2) It is possible to increase additional information to be entered for improving traceability, and it is possible to easily perform a failure analysis of a semiconductor integrated circuit device.
[0097]
(3) According to the above (1) and (2), the reliability of the semiconductor integrated circuit device can be improved, and the manufacturing cost of the semiconductor integrated circuit device can be reduced.
[Brief description of the drawings]
FIG. 1 is a layout diagram of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention.
2 is a layout explanatory diagram of a redundant fuse relief section provided in the semiconductor integrated circuit device of FIG. 1; FIG.
3 is a plan view of a fuse provided in an additional information fuse circuit of the redundant fuse relief section of FIG. 2; FIG.
4 is a cross-sectional view of the fuse of FIG. 3 taken along the line AB.
FIG. 5 is an explanatory diagram of additional information written in the semiconductor integrated circuit device of FIG. 1;
6 is an explanatory diagram showing an example of a write layout of additional information in FIG. 5. FIG.
7 is an explanatory diagram of parity check of additional information written in the semiconductor integrated circuit device of FIG. 1. FIG.
8 is a flowchart illustrating an inspection process in the semiconductor integrated circuit device of FIG. 1. FIG.
FIG. 9 is an explanatory diagram showing another example of additional information written in a semiconductor integrated circuit device according to another embodiment of the present invention.
[Explanation of symbols]
1 Semiconductor integrated circuit device
2-9 DRAM macro
10 Parity check logic part (information check part, parity check circuit)
10a to 10d parity check logic circuit
11 Memory part
11a-11i memory
12 Redundant fuse relief part (Relief fuse circuit)
12 ₁ ~ 12 ₆ Rescue fuse circuit
12 ₇ ~ 12 ₁₂ Rescue fuse circuit
13-19 Redundant fuse relief part (Relief fuse circuit)
20-27 Additional information fuse circuit (information storage unit)
28, 29 I / O section
VB additional information (specific information)
CH Semiconductor chip
F fuse
Z1 insulating film
Z2 insulating film
H Upper wiring layer
C1, C2 contact hole
L Latch
LP latch
B1 buffer
B2 buffer
TE tester

Claims (2)

Specific information is set inside thereof, and the specific information is a semiconductor integrated circuit device that can be referred to from the outside in a predetermined operation,
An information storage unit that includes a non-volatile memory and stores the specific information and error detection information that enables detection of an error in the specific information;
An information inspection unit that inspects the specific information by referring to the specific information and the error detection information ;
A setting circuit which has a setting element and allows the circuit operation to be set by the setting element;
Equipped with a,
The specific information in the information storage unit is digital data composed of a plurality of bits, and the error detection information is a parity bit for the specific information,
The information inspection unit is composed of a parity check circuit that receives the specific information and the error detection information as inputs.
The setting circuit comprises a redundant circuit for a semiconductor memory,
The setting element and the nonvolatile memory are composed of fuse elements that can be written by the same writing method,
2. A semiconductor integrated circuit device according to claim 1, wherein the fuse element for the information storage unit is formed in a straight line in the same row as the fuse element for the redundant circuit . 2. The semiconductor integrated circuit device according to claim 1 , wherein the parity check circuit is formed in the vicinity of a fuse element for the redundant circuit.

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