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JP4199899B2 - Tuning device - Google Patents
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JP4199899B2 - Tuning device - Google Patents

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JP4199899B2
JP4199899B2 JP2000053203A JP2000053203A JP4199899B2 JP 4199899 B2 JP4199899 B2 JP 4199899B2 JP 2000053203 A JP2000053203 A JP 2000053203A JP 2000053203 A JP2000053203 A JP 2000053203A JP 4199899 B2 JP4199899 B2 JP 4199899B2
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Prior art keywords
tuning
circuit
signal
frequency
voltage
Prior art date
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Expired - Fee Related
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JP2000053203A
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JP2001244794A (en
Inventor
信弘 福岡
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Faurecia Clarion Electronics Co Ltd
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Clarion Co Ltd
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Description

【0001】
【発明の属する技術分野】
本発明は、RFフロントエンド回路における同調回路の同調ずれの補正技術に関する。
【0002】
【従来の技術】
図4は従来の同調方式の一例を示すブロック図である。
RFフロントエンド回路100’で、入力端子から入力されたRF信号(無線信号)はAGCアンプ(AGCAMP)1で増幅されて同調回路2に入る。同調回路2は後段のPLL回路A(図4で破線枠内の局部発振回路5、1/n分周器6、位相比較器8、1/N分周器9、基準発振器10及びLPF11で構成)で作られるチューニング電圧によって入力信号の中心周波数で共振する。
【0003】
また、同調回路2を通った信号はミキサー(MIX)回路3で局部発振器5から発振される局発信号(ローカル信号)と混合されBPF4を経てIF信号(中間信号)として取り出される。
【0004】
一方、局発信号は受信機のプリセット周波数に対応した制御信号がマイコン(マイクロコンピュータ)7から出力され、分周器6の分周比を可変にしてn分周される。このn分周された信号と基準発振器10の信号を分周器9でN分周した周波数とを位相比較器8で位相比較を行い、その差分をLPF11で平滑化して得られる電圧(チューニング電圧)を局部発振回路5及び同調回路2にフィードバックして入力信号周波数に同調させる。
【0005】
【発明が解決しようとする課題】
同調回路2の共振局部発振回路の発振周波数は、通常、図5に示すようなLC回路50を構成して可変容量ダイオード51の容量をチューニング電圧で制御し、周波数を変化させる。しかし、可変容量ダイオード51の非直線領域(図3参照)や可変容量ダイオード(可変容量素子)のばらつきにより同調回路2の共振周波数がずれて正確な同調が行えない場合が生ずるといった問題点があった。
【0006】
本発明は、上記従来の同調回路に問題点を解消するためになされたものであり、素子の非直線性や特性のばらつきによって生ずる同調ずれを補正して受信帯域内で安定した同調特性を得る同調方式の提供を目的とする。
【0007】
【課題を解決するための手段】
上記課題を解決するために、第1の発明の同調装置は、チューニング信号に基づき同調周波数を制御する同調手段と、同調手段からの同調周波数とチューニング信号を入力し、同調手段の同調ずれのずれ分に相当する電圧を検出して補正電圧を生成する補正電圧生成手段と、この補正電圧生成手段により生成された補正電圧を基に前記チューニング信号を補正する補正手段と、を備え、補正電圧生成手段は、チューニング信号に対応する同調周波数を基準として、その前後の周波数範囲の周波数信号を出力する周波数発振器と、同調手段からの同調信号と前記周波数発振器からの周波数信号を入力とし、入力信号を合成する合成手段と、合成手段からの出力信号に基づき補正電圧を生成する手段と、を備えたことを特徴とする。
【0010】
【発明の実施の形態】
本発明のRFフロントエンド回路では、受信した無線周波信号の同調処理時に従来方式(図1のPLL回路B)で作られるチューニング電圧に、本発明の補正電圧生成回路Cで得られる補正電圧を加算して同調回路を制御することにより、前述した可変容量ダイオード等の素子のばらつきにより起こる同調ずれを補正し受信帯域内で安定した同調特性を得る。
【0011】
図1は本発明の同調方式を適用したフロントエンド回路の一実施例を示すブロック図である。
RFフロントエンド回路100は、AGCアンプ21、同調回路22、ミキサー(MIX1)回路23およびBPF24からなる中間周波信号系Aと、局部発振回路25、1/n分周器26、位相比較器28、1/N分周器29、基準発振器30及びLPF31からなるPLL回路B(図4のPLL回路Aと同一構成)と、電圧制御発振回路(VCO回路)32、ミキサー(MIX2)回路33、LPF34、A/Dコンバータ35、メモリ36及びレベル比較器37からなる補正電圧生成回路Cと、受信機のプリセット周波数に対応した制御信号をPLL回路Bに与えるマイコン(マイクロコンピュータ)27と、PLL回路Bの出力(チューニング電圧)及び補正電圧生成回路Cの出力(補正電圧)を加算して同調回路22に与える加算器38を備えている。
【0012】
以下、RFフロントエンド回路100の動作について説明する。
入力端子から入力されたRF信号(無線信号)はAGCアンプ(AGCAMP)21で増幅されて同調回路22に入る。同調回路22は後段の加算器38からの出力電圧(PLL回路Bで作られるチューニング電圧及び補正電圧生成回路Cで生成される補正電圧の加算結果)によって入力信号の中心周波数で共振する。また、PLL回路Bで生成されるチューニング電圧は補正電圧生成回路Cに与えられる。
また、同調回路22を通った信号はミキサー(MIX)回路23で局部発振器25から発振される局発信号と混合されBPF42を経てIF信号(中間信号)として取り出される。
【0013】
一方、局発信号は受信機のプリセット周波数に対応した制御信号がマイコン27から出力されてPLL回路Bに与えられる。PLL回路Bでは、マイコン27から出力した制御信号が分周器26の分周比を可変にしてn分周する。このn分周された信号は基準発振器30の信号を分周器29でN分周した周波数と位相比較器28で位相比較を行い、その差分をLPF31で平滑化して得られる電圧(チューニング電圧)を局部発振回路25及び加算器38にフィードバックする。
【0014】
また、同調回路22の出力信号がa点で取り出され、補正電圧生成回路Cに与えられる。補正電圧生成回路Cは、後述するように、PLL回路Bで生成されるチューニング電圧と同調回路22からの出力を基に電圧ずれΔVを検出しこれをもとに補正電圧を出力して加算器38に入力する。
【0015】
(補正電圧生成回路Cの動作)
a点で取り出された同調回路22の出力信号は補正電圧生成回路Cでミキサー回路33に入力する。また、ミキサー回路33のもう一方の入力端子にはスイープ機能付き電圧制御発振回路32の出力信号(電圧制御発振回路32はPLL回路Bから出力されるチューニング電圧を入力する)を入力する。
【0016】
電圧制御発振回路32は、局部発振回路25と同様、チューニング電圧の変化によって発振周波数を変化させるが、局部発振回路25がRF信号周波数とIF信号周波数の和(又は差)の周波数で振動するのに対し、この回路ではRF信号周波数と同一周波数で発振するように設定してあり、更に、図3に示すようにRF信号の中心周波数fcを中心に±fの範囲でステップ状に周波数をスイープさせる。
【0017】
ミキサー回路33は上述した同調回路22の出力信号を電圧制御発振回路32の出力とミキサー回路33と混合し、その出力をLPF34に入力する。
LPF34は図3に示したようなRF信号の中心周波数fcを中心とした各ステップの周波数毎のレベル(電圧値)を取り出す。
LPF34の出力をA/Dコンバータ35でA/D変換してメモリ36に取り込み、レベル比較器37で中心周波数fcのレベル(電圧値)と、中心周波数fcに対し±fの範囲内でずれたときのレベル(電圧値)を比較する。この場合、図2に示すように正確に同調がとれていればfcで信号レベルがピークになり、補正電圧は0(ゼロ)となるが、同調がずれてfc+f1にピークがある場合には電圧のずれΔVが検出されるのでこれを補正電圧とする。レベル比較器37の出力(補正電圧)は加算器38に入力され、加算器38でPLL回路Bからのチューニング電圧と加算され、同調回路22の共振局部発振回路の可変容量ダイオード51(図5)に印加される。これにより、可変ダイオード51が加算回路の出力電圧によって制御され、同調ずれが補正される。
【0018】
なお、電圧制御発振回路32のスイープ周波数範囲や変化させる周波数のステップは変調方式や実際の帯域幅、及び同調回路の共振局部発信回路で使用する素子(可変容量ダイオード)の特性などを考慮して設定する。また、受信機の同調は一度設定すれば頻繁に変更するものではなく、特別高速な処理を要しない。 以上、本発明の一実施例について説明したが本発明は上記実施例に限定されるものではなく、種々の変形実施が可能であることはいうまでもない。
【0019】
【発明の効果】
上記説明したように、本発明によれば、同調装置(RFフロントエンド回路)において、同調手段の同調のずれ分を検出して補正電圧を生成する補正電圧発生手段を設けているので、従来方式のPLL回路で作られるチューニング電圧だけの同調で処理しきれない同調ずれに対し、そのずれ分を検出して補正することができる。これにより、使用する受信帯域全域で安定した同調特性を得ることができる。
【図面の簡単な説明】
【図1】本発明の同調方式を適用したRFフロントエンド回路の一実施例を示すブロック図である。
【図2】同調特性のずれの説明図である。
【図3】本発明で使用するVCO回路(電圧制御発振回路)のスイープ特性の説明図である。
【図4】従来の同調方式を適用したRFフロントエンド回路の構成例を示すブロック図である。
【図5】同調回路の共振局部発振回路の構成例を示す図である。
【図6】図5の共振局部発振回路で用いられる可変容量ダイオードの容量変化の説明図である。
【符号の説明】
22 同調回路
32 VCO回路(電圧制御発振回路)
33 ミキサー回路(可変容量素子)
38 加算器(補正手段)
100 RFフロントエンド回路(同調装置)
C 補正電圧生成回路
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for correcting a tuning error of a tuning circuit in an RF front end circuit.
[0002]
[Prior art]
FIG. 4 is a block diagram showing an example of a conventional tuning method.
In the RF front end circuit 100 ′, the RF signal (radio signal) input from the input terminal is amplified by the AGC amplifier (AGCAMP) 1 and enters the tuning circuit 2. The tuning circuit 2 is composed of a PLL circuit A in the subsequent stage (a local oscillation circuit 5, a 1 / n frequency divider 6, a phase comparator 8, a 1 / N frequency divider 9, a reference oscillator 10 and an LPF 11 in a broken line frame in FIG. ) Resonates at the center frequency of the input signal.
[0003]
The signal passing through the tuning circuit 2 is mixed with a local signal (local signal) oscillated from a local oscillator 5 by a mixer (MIX) circuit 3 and taken out as an IF signal (intermediate signal) through a BPF 4.
[0004]
On the other hand, the control signal corresponding to the preset frequency of the receiver is output from the microcomputer (microcomputer) 7 as the local oscillation signal, and the frequency division ratio of the frequency divider 6 is made variable and divided by n. A voltage (tuning voltage) obtained by performing phase comparison between the n-divided signal and the frequency obtained by dividing the signal of the reference oscillator 10 by N with the frequency divider 9 with the phase comparator 8 and smoothing the difference with the LPF 11. ) Is fed back to the local oscillation circuit 5 and the tuning circuit 2 to be tuned to the input signal frequency.
[0005]
[Problems to be solved by the invention]
The oscillation frequency of the resonant local oscillation circuit of the tuning circuit 2 is normally changed by configuring the LC circuit 50 as shown in FIG. 5 and controlling the capacitance of the variable capacitance diode 51 with the tuning voltage. However, there is a problem that the tuning frequency of the tuning circuit 2 may be shifted due to variations in the non-linear region of the variable capacitance diode 51 (see FIG. 3) and variable capacitance diodes (variable capacitance elements), and accurate tuning may not be performed. It was.
[0006]
The present invention has been made in order to solve the problems in the conventional tuning circuit described above, and obtains a stable tuning characteristic within the reception band by correcting the tuning deviation caused by the non-linearity of the element and variations in characteristics. The purpose is to provide a tuning method.
[0007]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, a tuning device according to a first aspect of the present invention is a tuning means for controlling a tuning frequency based on a tuning signal, a tuning frequency from the tuning means and a tuning signal are inputted, and a deviation in tuning deviation of the tuning means is detected. A correction voltage generating means for detecting a voltage corresponding to a minute and generating a correction voltage; and a correction means for correcting the tuning signal based on the correction voltage generated by the correction voltage generating means, The means includes a frequency oscillator that outputs a frequency signal in a frequency range before and after the tuning frequency corresponding to the tuning signal, a tuning signal from the tuning means, and a frequency signal from the frequency oscillator as inputs, and an input signal as and synthesizing for synthesizing means, means for generating a correction voltage based on the output signal from the combining means, further comprising a, wherein.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
In the RF front end circuit of the present invention, the correction voltage obtained by the correction voltage generation circuit C of the present invention is added to the tuning voltage generated by the conventional method (PLL circuit B in FIG. 1) during the tuning process of the received radio frequency signal. Then, by controlling the tuning circuit, the tuning deviation caused by the variation of the elements such as the variable capacitance diode described above is corrected, and a stable tuning characteristic is obtained within the reception band.
[0011]
FIG. 1 is a block diagram showing an embodiment of a front end circuit to which the tuning system of the present invention is applied.
The RF front end circuit 100 includes an intermediate frequency signal system A including an AGC amplifier 21, a tuning circuit 22, a mixer (MIX1) circuit 23, and a BPF 24, a local oscillation circuit 25, a 1 / n frequency divider 26, a phase comparator 28, PLL circuit B (same configuration as PLL circuit A in FIG. 4) comprising 1 / N frequency divider 29, reference oscillator 30 and LPF 31, voltage controlled oscillation circuit (VCO circuit) 32, mixer (MIX2) circuit 33, LPF 34, A correction voltage generation circuit C comprising an A / D converter 35, a memory 36 and a level comparator 37, a microcomputer 27 for giving a control signal corresponding to the preset frequency of the receiver to the PLL circuit B, and a PLL circuit B An adder that adds the output (tuning voltage) and the output (correction voltage) of the correction voltage generation circuit C to the tuning circuit 22 38.
[0012]
Hereinafter, the operation of the RF front end circuit 100 will be described.
An RF signal (wireless signal) input from the input terminal is amplified by an AGC amplifier (AGCAMP) 21 and enters a tuning circuit 22. The tuning circuit 22 resonates at the center frequency of the input signal by the output voltage from the adder 38 in the subsequent stage (the addition result of the tuning voltage generated by the PLL circuit B and the correction voltage generated by the correction voltage generation circuit C). The tuning voltage generated by the PLL circuit B is given to the correction voltage generation circuit C.
Further, the signal passing through the tuning circuit 22 is mixed with a local oscillation signal oscillated from a local oscillator 25 by a mixer (MIX) circuit 23 and taken out as an IF signal (intermediate signal) through a BPF 42.
[0013]
On the other hand, as the local signal, a control signal corresponding to the preset frequency of the receiver is outputted from the microcomputer 27 and given to the PLL circuit B. In the PLL circuit B, the control signal output from the microcomputer 27 divides the frequency by n while changing the frequency dividing ratio of the frequency divider 26. This n-divided signal is a voltage (tuning voltage) obtained by comparing the phase of the signal of the reference oscillator 30 by N with the frequency divider 29 and the phase comparator 28 and smoothing the difference with the LPF 31. Is fed back to the local oscillation circuit 25 and the adder 38.
[0014]
Further, the output signal of the tuning circuit 22 is taken out at point a and applied to the correction voltage generation circuit C. As will be described later, the correction voltage generation circuit C detects the voltage deviation ΔV based on the tuning voltage generated by the PLL circuit B and the output from the tuning circuit 22 and outputs a correction voltage based on this voltage difference ΔV. 38.
[0015]
(Operation of the correction voltage generation circuit C)
The output signal of the tuning circuit 22 taken out at the point a is input to the mixer circuit 33 by the correction voltage generation circuit C. Further, the output signal of the voltage controlled oscillation circuit 32 with a sweep function (the voltage controlled oscillation circuit 32 inputs the tuning voltage output from the PLL circuit B) is input to the other input terminal of the mixer circuit 33.
[0016]
The voltage controlled oscillation circuit 32 changes the oscillation frequency by changing the tuning voltage, as with the local oscillation circuit 25, but the local oscillation circuit 25 vibrates at the frequency of the sum (or difference) of the RF signal frequency and the IF signal frequency. On the other hand, this circuit is set to oscillate at the same frequency as the RF signal frequency. Further, as shown in FIG. 3, the frequency is swept in steps within a range of ± f around the center frequency fc of the RF signal. Let
[0017]
The mixer circuit 33 mixes the output signal of the tuning circuit 22 described above with the output of the voltage controlled oscillation circuit 32 and the mixer circuit 33, and inputs the output to the LPF 34.
The LPF 34 extracts the level (voltage value) for each frequency at each step with the center frequency fc of the RF signal as shown in FIG.
The output of the LPF 34 is A / D converted by the A / D converter 35 and taken into the memory 36. The level comparator 37 shifts the level (voltage value) of the center frequency fc within a range of ± f with respect to the center frequency fc. Compare the level (voltage value). In this case, as shown in FIG. 2, if the signal is accurately tuned, the signal level peaks at fc and the correction voltage becomes 0 (zero). However, if the signal is not tuned and there is a peak at fc + f1, Since this deviation ΔV is detected, this is used as a correction voltage. The output (correction voltage) of the level comparator 37 is input to the adder 38, and is added to the tuning voltage from the PLL circuit B by the adder 38, and the variable capacitance diode 51 of the resonance local oscillation circuit of the tuning circuit 22 (FIG. 5). To be applied. Thereby, the variable diode 51 is controlled by the output voltage of the adder circuit, and the tuning deviation is corrected.
[0018]
Note that the sweep frequency range of the voltage-controlled oscillation circuit 32 and the step of the frequency to be changed take into consideration the characteristics of the element (variable capacitance diode) used in the resonance local oscillation circuit of the tuning circuit, the actual bandwidth, and the tuning circuit. Set. Further, once the receiver tuning is set, it does not change frequently, and no special high-speed processing is required. As mentioned above, although one Example of this invention was described, this invention is not limited to the said Example, It cannot be overemphasized that various deformation | transformation implementation is possible.
[0019]
【The invention's effect】
As explained above, according to this onset bright, in the tuning device (RF front-end circuit), since by detecting the shift amount of the tuning of the tuning means it is provided a correction voltage generating means for generating a correction voltage, the conventional A tuning shift that cannot be processed by tuning only the tuning voltage generated by the PLL circuit of the type can be detected and corrected. Thereby, a stable tuning characteristic can be obtained over the entire reception band to be used.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an RF front-end circuit to which a tuning method of the present invention is applied.
FIG. 2 is an explanatory diagram of a shift in tuning characteristics.
FIG. 3 is an explanatory diagram of a sweep characteristic of a VCO circuit (voltage controlled oscillation circuit) used in the present invention.
FIG. 4 is a block diagram showing a configuration example of an RF front end circuit to which a conventional tuning method is applied.
FIG. 5 is a diagram illustrating a configuration example of a resonance local oscillation circuit of a tuning circuit.
6 is an explanatory diagram of a change in capacitance of a variable capacitance diode used in the resonant local oscillation circuit of FIG. 5;
[Explanation of symbols]
22 Tuning circuit 32 VCO circuit (voltage controlled oscillation circuit)
33 Mixer circuit (variable capacitance element)
38 Adder (correction means)
100 RF front-end circuit (tuning device)
C correction voltage generation circuit

Claims (1)

チューニング信号に基づき同調周波数を制御する同調手段と、
前記同調手段からの同調周波数と前記チューニング信号を入力し、前記同調手段の同調ずれのずれ分に相当する電圧を検出して補正電圧を生成する補正電圧生成手段と、
この補正電圧生成手段により生成された補正電圧を基に前記チューニング信号を補正する補正手段と、を備え、
前記補正電圧生成手段は、
前記チューニング信号に対応する同調周波数を基準として、その前後の周波数範囲の周波数信号を出力する周波数発振器と、
前記同調手段からの同調信号と前記周波数発振器からの周波数信号を入力とし、入力信号を合成する合成手段と、
前記合成手段からの出力信号に基づき補正電圧を生成する手段と、を備えたこと、
を特徴とする同調装置
Tuning means for controlling the tuning frequency based on the tuning signal;
A correction voltage generating means for inputting a tuning frequency from the tuning means and the tuning signal, detecting a voltage corresponding to a deviation of the tuning deviation of the tuning means, and generating a correction voltage;
Correction means for correcting the tuning signal based on the correction voltage generated by the correction voltage generation means,
The correction voltage generating means includes
A frequency oscillator that outputs a frequency signal in a frequency range before and after the tuning frequency corresponding to the tuning signal, and
A synthesizing unit that inputs a tuning signal from the tuning unit and a frequency signal from the frequency oscillator, and synthesizes an input signal;
Means for generating a correction voltage based on an output signal from the synthesizing means,
A tuning device characterized by.
JP2000053203A 2000-02-29 2000-02-29 Tuning device Expired - Fee Related JP4199899B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000053203A JP4199899B2 (en) 2000-02-29 2000-02-29 Tuning device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000053203A JP4199899B2 (en) 2000-02-29 2000-02-29 Tuning device

Publications (2)

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JP2001244794A JP2001244794A (en) 2001-09-07
JP4199899B2 true JP4199899B2 (en) 2008-12-24

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