JP4201202B2 - Low voltage modulation circuit for pass device - Google Patents

Abstract

Power supply voltages are selectively modulated to correspond with degraded input voltages to a logic device. Modulated power supply voltages are provided to transistors within the logic device, so that the degraded input voltages supplied to the transistors are sufficient to turn the transistors substantially on or off. Leakage currents are prevented thereby from flowing across the transistors.

Description

  The present invention relates to a semiconductor device. The present invention particularly relates to improvements in switched routing networks used in many semiconductor devices for signal routing through the device.

  In this specification, P and N channel MOS (Metal Oxide Semiconductor) devices (PMOS and NMOS) are described as gate nodes, drain nodes, and source nodes. This serves to clarify the structure and operation of other embodiments. The PMOS device transmits positive current when the gate signal is low and stops transmitting current when the gate signal is high. The NMOS device transmits positive current when the gate signal is high and stops transmitting current when the gate signal is low.

  According to standard practice, a positive current flows from the drain node to the source node in the NMOS device and from the source node to the drain node in the PMOS device. The convention of source and drain nodes is used only to help describe the structure and operation of embodiments of the present invention and is not intended to limit the scope of the present invention. In particular, if the source region and the drain region are symmetrical, the MOS transistor can be operated in reverse. Accordingly, the relative positions of the source and drain are not critical to the disclosure of embodiments of the present invention.

  Referring to FIG. 12, many semiconductor devices include a number of process elements 10 connected via a configurable routing network 20. For example, reconfigurable devices such as field programmable gate arrays (“FPGAs”), processor arrays, and reconfigurable arithmetic arrays (“RAA”) typically include many process elements. The process elements are connected together by a universal interconnect network that can form links between various combinations of process elements. Similarly, an integrated device comprises several processors, peripheral devices and memory connected via one or more shared buses. It is often beneficial to provide an input buffer circuit 80 between the configurable routing network 20 and the process element 10. These input buffer circuits 80 may be buffers that simply transmit input values. The input buffer circuit 80 can also be a simple logic device such as a CMOS inverter, NAND gate, or NOR gate. The input buffer circuit 80 can also be a more complex circuit for performing various functions by the designer of the semiconductor device.

The configurable routing network 20 communicates signals from one process element 10 to another process element. For CMOS circuits, these signals are typically a series of binary values. The sequence of binary values is represented by either a high voltage corresponding to logic “1” or a low voltage corresponding to logic “0”. The high voltage is usually equal to V _dd , ie the positive supply voltage 60. The low voltage is usually equal to Gnd, ie the ground supply voltage 70.

  In general, the routing network 20 comprises a set of wiring segments 30 and a set of active elements. The set of active elements is configured as a switch 40 that can connect or disconnect the connection between the wiring segments 30. By selectively connecting or disconnecting the wiring segments 30, the routing network 20 can make various connections between the various process elements 10 on the device. As the conditions of the process element 10 change, these connections can be changed dynamically. The switches 40 are controlled by signals on the control wiring 50 and are typically controlled by the state of the device that is itself a part, or sometimes the state of another device.

  There are various types of switches 40 that can be used in a switched routing network. One useful switch 40 in designing a routing network is a single transistor known as a pass transistor. The source and drain of a single transistor is connected to a pair of wiring segments 30 in the routing network. A pass transistor is a good choice. This is because it does not occupy a large space on the semiconductor device, can transmit a signal in either direction through the wiring segment 30, and there is no active circuit in the path, so the power consumption is not so large. The electric power is used only for charging and discharging the wiring segment 30.

There are also disadvantages due to the introduction of the switch 40 as a pass transistor. Depending on the type of pass transistor used, the maximum voltage that can pass the pass transistor is lower than the gate voltage ( _Vdd that normally turns on the NMOS transistor), or the lowest voltage that can pass the pass transistor is usually the gate voltage (normally the PMOS transistor is turned on) Is greater than Gnd). In the NMOS pass transistor, the reduced high signal is lower than the gate voltage by an amount equal to the transistor threshold voltage V _t , producing a reduced high signal of V _dd −V _t . In a PMOS pass transistor, the increased low signal is higher than the gate voltage by an amount equal to the absolute value of the transistor threshold voltage V _t , generating an increased low signal of Gnd−V _t (by convention, the PMOS transistor has a negative threshold voltage). because it has, _{Gnd-V t} is greater than Gnd). Therefore, the non-degraded signal that changes between V _dd and Gnd degrades when transmitted through the path transistor. Other active devices also change either high or low signals with the active devices as well. Because of the effect of this pass transistor voltage change, a logic device such as input buffer circuit 80 that receives the signal sent through the pass transistor is sufficient to ensure that the transistors in the logic device are turned on or off. Receive a signal that is not high or low.

For example, if a reduced high signal from an NMOS pass transistor is supplied to the gate of a PMOS transistor that is in the input buffer circuit 80 and is supplied with a positive supply voltage V _{dd at} its source, the reduced high signal is applied to the PMOS transistor. Insufficient to turn off completely, some current will leak through the PMOS transistor. Similarly, when an increased low signal is applied to the gate of an NMOS transistor that is in the input buffer circuit 80 and is supplied with the ground voltage Gnd at the source, the increased low signal is not sufficient to completely turn off the NMOS transistor. Sufficient and some current will leak through the NMOS transistor. This phenomenon is not unique to pass transistor switches in routing networks. Similar problems occur whenever a high or low signal is reduced or increased when transmitted through any active or powered device (eg, transistor, rectifier, amplifier, etc.).

Various means have been used in an attempt to solve the problem of voltage changes caused by active devices such as pass transistors in routing networks. For example, by decreasing the pass transistor threshold voltage V _t , the reduced output signal of the pass transistor is high enough to guarantee on / off of other devices attached to the output of the pass transistor. Can be raised.

To lower the voltage V _t is more complicated process for making a silicon substrate is required. It is also possible to design the device with a lower voltage V _t is an extra process steps are required. In addition, this extra step generally means that the lower V _t element must be physically located away from the normal V _t element, consuming valuable space on the silicon. End up. Also, a lower V _t device has means that there is a large leakage current when the transistor is turned off, power is wasted.

  Another solution to the voltage change problem is to use a level recovery circuit to pull the reduced high signal back to a high signal or the increased low signal back to a low signal. There are two well-known types of circuits for restoring voltage. First, a circuit known as a “weak pull-up” circuit can be used to pull up a decreasing high signal (similarly, a weak pull-down can pull down an increasing low signal). Second, a differential amplifier circuit can be used to return both the decreasing high signal and the increasing low signal to high or low values, respectively.

  The circuit of FIG. 1 is an example of a weak pull-up circuit. The circuit of FIG. 1 illustrates the use of inverter 140 as a logic device to which a reduced high signal is supplied. The weak pull-up circuit functions similarly for other devices such as NAND gates. However, weak pull-up circuits are not useful for devices such as NOR gates. In order for a weak pull-up to be useful, the input to which the pull-up is attached must be high and only then the output of the gate must be low. This condition is met for inverters and NAND gates, but not for NOR gates whose output can be low when other inputs are high.

Inverter 140 requires a high signal equal to V _dd to ensure that it is fully activated. A reduced high signal is received on input 110. This reduced high signal is transmitted to inverter 140, which generates an increased low signal that is slightly greater than the low signal that is the inverted signal of this reduced high signal (the low signal is equal to Gnd). This increased low signal is passed to the gate of the PMOS transistor 130 and turns on the PMOS transistor 130. The PMOS transistor 130 can pull up the input 110 to the full V _dd level present on the positive voltage supply input 120. In this way, the reduced high signal on input 110 is pulled up to the full V _dd level, inverter 140 is fully activated and transmits the full low voltage Gnd to output 150. Conversely, the increased low signal on input 110 can be pulled down to the total low voltage Gnd by replacing PMOS transistor 130 with an NMOS transistor and replacing the V _dd voltage on positive voltage supply input 120 with a Gnd voltage.

  However, this circuit has significant drawbacks. Selecting the proper strength of transistor 130 is important for the effective operation of the circuit and is not trivial. The strength of a transistor is measured as the resistance value of the transistor when current is conducted. A high strength transistor conducts a larger current than a low strength transistor. If transistor 130 is too low, it takes a long time for transistor 130 to pull up its input (or pull down for an NMOS pulldown transistor) during which time inverter 140 consumes power. If transistor 130 is too strong, it will take time for the drive circuit to pull to the transistor when attempting to drive low on input 110 to invert the inverter. Also, if transistor 130 is too strong, it will take time for NMOS to pull down the transistor when trying to drive high onto input 110. The need to pull from transistor 130 against a resistive load also increases power consumption.

  Choosing the appropriate strength for a transistor is particularly difficult with a reconfigurable array. This is because the optimum intensity depends on the resistance value of the path through the array from the original source of the signal to the signal target device. Since the array is reconfigurable, the length of this path varies depending on the application configured on the array, so the resistance value is changing and not constant. Therefore, the only way to choose a safe value for the pull-up transistor is guaranteed to be a safe value for the worst case path, that is, a sub-optimal value for most of the path. Value is used. This safety value is low enough that its resistance value is always inferior by any path through the array.

Another solution is the differential amplifier circuit illustrated in FIG. In this circuit, the input signal on input 210 is compared to a reference signal V _ref on reference input 280. V _ref is selected to be intermediate between high and low signals that are transmitted through the routing network. The positive voltage supply input 220 supplies a positive supply voltage V _dd to the two PMOS transistors 230 and 240. The ground voltage supply input 270 supplies the ground supply voltage Gnd to the two NMOS transistors 250 and 260. The drains of the two PMOS transistors 230 and 240 are connected to the ground 270 via the two NMOS transistors 250 and 260. The drains of the two PMOS transistors 230 and 240 are connected to the gates of the other PMOS transistors. The first NMOS transistor 250 is controlled by an input signal on the input 210. The second NMOS transistor 260 is controlled by V _ref on the reference input 280. Finally, the output 290 is connected to the drain of the second PMOS transistor 240.

The differential amplifier is configured such that both of the two PMOS transistors 230, 240 are not normally turned on at the same time. When one of the two PMOS transistors 230, 240 has a low drain voltage, that transistor raises the other drain voltage (and its own gate voltage) by turning on the other transistor. At this time, itself is off, ensuring that its own drain voltage remains low. The drain voltage is controlled by NMOS transistors 250 and 260 that attempt to pull the voltage down to Gnd. The higher of the two NMOS transistors 250, 260 that has a higher signal on its own gate pulls down more strongly, giving a lower voltage on the drain of the corresponding PMOS transistor 230, 240, resulting in other PMOS transistors. Turn on. Thus, when the signal on input 210 is lower than the V _ref signal on reference input 280, first PMOS transistor 230 is turned on, second PMOS transistor 240 is turned off, and output 290 drops to Gnd. When the signal on input 210 is greater than the V _ref signal at voltage input 280, second PMOS transistor 240 is turned on, first PMOS transistor 230 is turned off, and output 290 rises to V _dd . Thus, V _ref is chosen to be between the high and low input signal levels, so when the input signal is closer to high than low, any input signal will result in an output equal to V _dd When the signal is closer to lower than high, any input signal will result in an output equal to Gnd.

However, this circuit consumes power due to the resistive path from V _dd to Gnd through transistors 230, 240, 250, 260. Since the second NMOS transistor 260 is always partially conducting, there is a steady power drain through the amplifier whenever the output 290 is high. The extra power consumption of the differential amplifier circuit first cancels out the power advantage of using a pass transistor network.

  Therefore, the system needs to be able to easily and optimally compensate for the effects of the routing network on the voltage transmitted through the network with a small number of additional components without increasing power consumption in the semiconductor device.

  The accompanying drawings are provided for a better understanding of the embodiments and detailed description of the present invention and illustrate the principles of the disclosed embodiments.

FIG. 3 shows an example of a CMOS logic device. 3 is an inverter 300, those skilled in the art will appreciate that the embodiments disclosed herein may be used with any standard logic device or some combination of standard logic devices. In FIG. 12, the inverter 300 may be a component of the input buffer circuit 80 of the reconfigurable device, for example. For ease of explanation, the disclosed embodiments are described with reference to CMOS logic devices. Other embodiments using other forms of logic devices are also possible. The CMOS inverter shown in FIG. 3 is connected to an input 310, a positive voltage supply 320, a ground voltage supply 350 and an output 360. The positive voltage supply 320 supplies power with a high CMOS voltage V _dd . This power is used as a voltage indicating a high value (logic “1”) for the CMOS logic device. The ground voltage supply 350 supplies the ground value Gnd. The ground value Gnd is also used as a voltage indicating a low value (logic “0”) for the CMOS logic device. The inverter 300 includes a positive voltage supply input 325, a first PMOS transistor 330, a first NMOS transistor 340, and a ground voltage supply input 355.

Inverter 300 transmits an inverted signal of the signal on input 310 to output 360. When the signal on input 310 is low (eg, Gnd, CMOS low, etc.), the first PMOS transistor 330 is turned on and current flows from the positive voltage supply 320 through the positive voltage supply input 325 to the output 360. This sends a high signal to output 360. The first NMOS transistor 340 is turned off by a low signal, the path to the ground voltage supply 350 is blocked, and current is prevented from flowing to the ground voltage supply 350. When the signal on input 310 is high (ie, V _dd , CMOS high, etc.), the first PMOS transistor 330 is turned off, preventing current from flowing from the positive voltage supply 320. The first NMOS transistor 340 is turned on by a high value, which connects the output 360 to the ground voltage supply 350 through the ground voltage supply input 355. This sends a low signal to output 360.

  As shown in FIG. 4, the voltage modulation circuit 400 is used with a target circuit such as the inverter 300 to provide a high and / or low output signal. The voltage modulation circuit 400 is connected between the positive voltage supply 320 and the positive voltage supply input 325 of the inverter 300 so that the power supplied to the inverter 300 first passes through the voltage modulation circuit 400 and then is supplied to the inverter 300. It is connected. Since the voltage modulation circuit 400 is disposed between the positive voltage supply 320 and the positive voltage supply input 325 of the inverter 300, no additional current path is formed other than the existing path formed by the inverter 300. Therefore, the voltage modulation circuit 400 does not form anything that becomes an additional power consumption source other than the existing one in the inverter 300.

  The voltage modulation circuit 400 includes a converter and a bypass circuit. In one embodiment, the converter is a second NMOS transistor 410 and the bypass circuit is a second PMOS transistor 420. In other embodiments, the converter comprises other types of devices such as one or more transistors, diodes or other devices. These devices convert the voltage on the positive voltage supply 320 to a reduced level that is effective to ensure that the first PMOS transistor 330 is turned off, even if the signal on the input 310 is a reduced high signal. In other embodiments, the bypass circuit is comprised of other types of devices such as one or more switches or other devices. These devices selectively control the signal applied to the inverter 300 between a high value and a decreasing high value.

  The positive voltage supply 320 is connected to both the gate and drain of the second NMOS transistor 410 and is further connected to the source of the second PMOS transistor 420. The control input 430 is connected to the gate of the second PMOS transistor 420. The source of the second NMOS transistor 410 and the drain of the second PMOS transistor 420 are connected to the positive voltage supply input 325 of the inverter 300.

  When inverter 300 is in normal operation, the signal on input 310 changes between a low value and a decreasing high value. When the input signal has a low value, the control input 430 can supply a low value to the second PMOS transistor 420. When the input signal has a decreasing high value, the control input 430 can supply a high value to the second PMOS transistor 420. These control input values can be derived from other available sources of signals that invert the signal on output 360 or that are inverted signals of the output signal. More generally, in any logic device, the control input value is such that the second PMOS transistor 420 is off (ie, the control input is high) whenever there is no conduction path through the PMOS transistor in the logic device. When there is a conduction path through the PMOS transistor, the second PMOS transistor 420 is always turned on (low control). For standard CMOS gates (if there is a path through either an NMOS or PMOS device, but not both at the same time), the “PMOS conduction” state is equal to the high signal on the output, and the “PMOS non-conduction” state is the output Equal to the low signal above. Therefore, the value of the control signal is an inverted signal of the output signal. The voltage modulation circuit 400 is connected to the supply connection to the CMOS gate and not to the individual data inputs to the CMOS gate (eg, input 310), so that the control input 430 tracks the input 310. It is not always necessary. This is a difference from the weak pull-up circuit of FIG. Since the weak pull-up circuit attempts to control the individual inputs, it requires a control signal for pull-up that is low when the input is high. Therefore, the weak pull-up circuit can be supplied with the necessary control signals. Operates only on the gate. The circuit of FIG. 1 cannot be applied to, for example, a NOR gate, but the circuit of the embodiment of the present invention shown in FIG. 4 can be applied to any CMOS gate.

When the input signal is low and thus the control input 430 supplies a low value to the second PMOS transistor 420, the second PMOS transistor 420 transfers the full voltage V _dd from the positive voltage supply input 320 to the positive voltage supply input 325. . This total voltage V _dd takes precedence over the reduced voltage transmitted through the second NMOS transistor 410. Thus, the control signal on the control input 430 operates to select the second PMOS transistor 420 and supply the full positive supply voltage V _dd to the positive voltage supply input 325.

Since the input signal is low, the first PMOS transistor 330 supplies V _dd from the positive voltage supply input 325 to the output 360. The first NMOS transistor 340 is turned off by a low value, so there is no current path through the transistor 340 to the ground voltage supply 350. Thus, all CMOS high signals are provided on the output 360 of the inverter 300.

When the input signal is a decreasing high signal and therefore the control input 430 provides a high signal to the second PMOS transistor 420, the second PMOS transistor 420 is turned off, thereby preventing current from flowing through the second PMOS transistor 420. However, there is still a connection to the positive voltage supply 320 through the second NMOS transistor 410. This is because the gate of the second NMOS transistor 410 is connected to V _dd and therefore the second NMOS transistor 410 is always conductive. Recall that an NMOS transistor cannot transmit a high signal that is greater than its gate voltage and less than its threshold voltage. What an NMOS transistor can do is to transmit a decreasing high signal at most, in this case V _dd −V _{t (N 2)} , where V _{t (N 2)} is the threshold voltage of the second NMOS transistor 410. This reduced high signal is supplied to the positive voltage supply input 325. In this way, the control signal on the control input 430 operates to select the second NMOS transistor 410 and supply a reduced high signal to the positive voltage supply input 325.

The positive voltage supply input signal has a decreasing high value of V _dd -V _{t (N2)} , and the input signal from the input 310 has a decreasing high value of V _dd -V _{t (pass)} (where V _{t (pass)} is Through which the input signal is the threshold voltage of one or more devices connected to the input 310). Here, assuming that the threshold voltage of the second NMOS transistor 410 is selected to be approximately equal to the threshold voltage of one or more devices connected to the input 310, the input signal and the positive voltage supply input signal are It is approximately the same voltage. Therefore, the voltage difference between both ends of the first PMOS transistor 330 between the gate and the source is substantially zero, and the first PMOS transistor 330 is turned off. V _{t (N2)} and V _{t (pass)} need not be exactly equal. The required condition is a gate-source voltage that ensures that the current flowing through the first PMOS transistor 330 is negligible. This condition is typically satisfied when the gate-source voltage exceeds 1/2 Vt _(P1) . This is equivalent to the condition Vt _(N2) −Vt _(pass) ≧ 1 / 2Vt _{(P1) (} rethink that the PMOS transistor is turned on by a sufficiently low gate voltage and turned off by a high gate voltage. ).

Even if the positive voltage supply 320 supplies the full V _dd voltage, there is no leakage current through the first PMOS transistor 330. This is because the entire V _dd voltage signal is converted to a reduced high signal by the second NMOS transistor 410. Since the reduced high signal on input 310 is still strong enough to exceed the threshold voltage on first NMOS transistor 340, the transistor is turned on and the signal on output 360 is lowered to Gnd by ground voltage supply 350. Thus, all CMOS low is supplied to the output 360 of the inverter 300.

  In the second embodiment shown in FIG. 5, a variation of the voltage modulation circuit is used to address the situation where the input 310 can supply a high signal, but can only supply an increased low signal rather than a low signal. The second voltage modulation circuit 500 is used with the inverter 300 to provide a high and / or low output signal. The second voltage modulation circuit 500 includes a ground voltage supply 350 and a ground voltage supply input of the inverter 300 such that the current drawn from the inverter 300 first flows through the second voltage modulation circuit 500 and then flows to the ground voltage supply 350. 355 is connected. Since the second voltage modulation circuit 500 is disposed between the ground voltage supply 350 and the ground voltage supply input 355 of the inverter 300, there is no additional current path other than the existing path formed by the inverter 300. Therefore, the second voltage modulation circuit 500 does not form an additional power consumption source other than the existing one in the inverter 300.

  The second voltage modulation circuit 500 includes a converter and a bypass circuit. In one embodiment, the converter is a third PMOS transistor 510 and the bypass circuit is a third NMOS transistor 520. In other embodiments, the converter is comprised of other types of devices, such as one or more transistors, diodes or other devices. These devices convert the low signal on ground voltage supply 350 to an increased low level that is effective to ensure that the first NMOS transistor 340 is turned off, even if the signal on input 310 is an increased low signal. . In other embodiments, the bypass circuit comprises other types of devices such as one or more switches or other devices. These devices selectively control the voltage supplied to the inverter 300 between a low value and an increased low value.

  The ground voltage supply 350 is connected to both the gate and drain of the third PMOS transistor 510 and is further connected to the source of the third NMOS transistor 520. The second voltage modulation circuit 500 also has a control input 530 connected to the gate of the third NMOS transistor 520. The source of the third PMOS transistor 510 and the drain of the third NMOS transistor 520 are both connected to the ground voltage supply input 355 of the inverter 300.

  When inverter 300 is in normal operation, the signal on input 310 changes between an increasing low value and a high value. When the input signal has a high value, the control input 530 can supply the high value to the third NMOS transistor 520. When the input signal has an increased low value, the control input 530 can supply a low value to the third NMOS transistor 520. These control input values are derived from a signal source that inverts the signal on output 360 or is the inverse of another available output signal. More generally, in any logic device, the control input value is such that the third NMOS transistor 520 is off (ie, the control input is low) whenever there is no conduction path through the NMOS transistor in the logic device, and the NMOS in the logic device. The third NMOS transistor 520 is configured to be on (control high) whenever there is a conduction path through the transistor. For standard CMOS gates (if there is a path through an NMOS or PMOS device, but not both), the “NMOS conduction” state is equal to a low signal on the output and the “NMOS non-conduction” state is Equal to high signal on output. Therefore, the value of the control signal is an inverted signal of the output signal. The control input 530 tracks the input 310 because the second voltage modulation circuit 500 is connected to the CMOS gate supply connection and not to the individual data inputs to the CMOS gate (ie, input 310). Is not always necessary. This is the difference from the weak pull-up circuit of FIG. The weak pull-up circuit attempts to control individual inputs and requires a control signal for pull-up that is low when the input is high. Thus, the control signal operates only on the gate that can be supplied with the required control signal. For example, the circuit of FIG. 1 cannot be applied to a NOR gate, but the circuit of the embodiment of the present invention shown in FIG. 5 can be applied to any CMOS gate.

  When the input signal is high and therefore the control input 530 supplies a high value to the third NMOS transistor 520, the third NMOS transistor 520 transfers the entire ground voltage Gnd from the ground voltage supply 350 to the ground voltage supply input 355. This total ground voltage Gnd takes precedence over the increased low signal being transmitted through the third PMOS transistor 510. Thus, the signal on the control input 530 operates to select the third NMOS transistor 520 and supply the ground signal to the ground voltage supply input 355.

  Since the input signal is high, the first PMOS transistor 330 is turned off and no current flows from the positive voltage supply 320 to the output 360. The first NMOS transistor 340 is turned on by a high value, and the ground voltage supply 350 is connected to the output 360. As a result, the output 360 is pulled down to Gnd. Thus, all CMOS low values are provided on the output 360 of the inverter 300.

If the input signal is an increasing low value and therefore the control input 530 provides a low value to the third NMOS transistor 520, the third NMOS transistor 520 is turned off, thereby preventing current from flowing through the third NMOS transistor 520. However, there is still a connection to the ground voltage supply 350 through the third PMOS transistor 510 because the gate of the third PMOS transistor 510 is connected to Gnd and the third PMOS transistor 510 is therefore always conducting therefor. Recall that a PMOS transistor cannot carry a full low signal. The PMOS transistor can only carry a decreasing low signal at most, in this case -Vt _(P2) , where Vt _(P2) is the threshold voltage of the third PMOS transistor 510 (the PMOS transistor is typically a negative threshold voltage). -Vt _(P2) is therefore positive). This increased low signal is supplied to the ground voltage supply input 355. Thus, the signal on control input 530 selects third PMOS transistor 510 and provides an increased low signal to ground voltage supply input 355.

A ground voltage supply input signal is increased low value of _{-V t (P2),} the input signal from the input 310 is increased low value of _{-V t (pass) (V t} (pass) , the input signal through it Is the threshold voltage of one or more devices connected to input 310 and is also negative for the PMOS device). Here, assuming that the threshold voltage of the third PMOS transistor 510 is selected to be approximately equal to the threshold of one or more devices that have passed before the input signal is connected to the input 310, the input signal The ground voltage supply input signal is substantially the same voltage. The gate-source voltage across the first NMOS transistor 340 is therefore approximately zero and the first NMOS transistor 340 is turned off. V _{t (P2)} and V _{t (pass)} need not be exactly equal if the gate-source voltage is sufficiently low to ensure that the current flowing through the first NMOS transistor 340 is negligible. This condition is typically satisfied when the gate-source voltage is less than 1/2 V _{t (N1)} . This is equivalent to the condition of Vt _(P2) −Vt _(pass) ≦ 1 / 2Vt _(N1) .

Since the entire Gnd voltage signal is converted to an increased low signal by the third PMOS transistor 510, there is substantially no leakage current through the first NMOS transistor 340 even if the ground voltage supply 350 continues to supply the entire Gnd voltage signal. . The increased low signal on input 310 is still low enough to keep the gate-source voltage of the first PMOS transistor 330 below the threshold voltage, thereby turning it on, and the signal on output 360 is thus _Pulled to V _dd . Thus, the full CMOS height is provided on the output 360 of the inverter 300.

  The voltage modulation circuit 400 and the second voltage modulation circuit 500 can be combined and used to handle situations where the input 310 provides a signal that does not reach a high or low value. This combination is illustrated in FIG.

Either or both of the voltage modulation circuits 400, 500 can be used with any CMOS logic device. For example, FIG. 7 shows a voltage modulation circuit 400 used with a CMOS NAND gate 700. The NAND gate generates a high output signal whenever either input signal is low and generates a low output signal when both input signals are high. Therefore, when either the first input 730 (IN1) or the second input 740 (IN2) provides a low signal, the corresponding PMOS transistor 710, 720 is turned on and the V _dd voltage is supplied from the positive voltage supply 320 to the first. 2 is transmitted to the output 780 through the PMOS transistor 420 and then through the PMOS transistors 710 and 720 that are turned on. Since at least one of the inputs 730, 740 is providing a low signal, at least one of the corresponding NMOS transistors 750, 760 is turned off, thus preventing any current from flowing to the ground voltage supply 350. . When both input signals are high, both PMOS transistors 710, 720 are turned off and both NMOS transistors 750, 760 are turned on. This blocks the V _dd voltage and creates a connection between the ground voltage supply 350 and the output 780, thereby pulling the output signal down to Gnd.

If both input signals are reduced high signals, the control input 430 provides a high signal and the voltage modulation circuit 400 supplies the reduced high signal to the PMOS transistors 710, 720 as described above. The control signal on control input 430 is an inverted signal of the output signal on output 780 generated as described above. This prevents any non-negligible current from leaking through the PMOS transistors 710, 720, thus saving power. Again, it should be noted that since the voltage modulation circuit 400 is arranged along the existing current path between V _dd and Gnd, no additional current path is formed. The reduced high signal on inputs 730, 740 is sufficient to form a connection between ground voltage supply 350 and output 780, so that a low signal is properly provided on output 780.

As another example, a voltage modulation circuit 400 is used with a CMOS NOR gate 800 as shown in FIG. The NOR gate always generates a low output signal when either input signal is high, and generates a high output signal when both input signals are low. Thus, when either the first input 850 or the second input 860 provides a high signal, the corresponding NMOS transistor 810, 820 is turned on, the connection from the ground voltage supply 350 to the output 870 is closed, and the output 870 is Pulled down to Gnd. Since at least one of the inputs 850, 860 is supplied with a high signal, at least one of the corresponding PMOS transistors 830, 840 is turned off, preventing any current from flowing from the positive voltage supply 320. When both input signals are low, both NMOS transistors 810, 820 are turned off and both PMOS transistors 830, 840 are turned on. This blocks the connection between the ground voltage supply 350 and the output 870 and creates a connection between the positive voltage supply 320 and the output 870, causing the output signal to be V _dd .

If any input signal is a reduced high signal, the control input 430 provides a high value and the voltage modulation circuit 400 provides the reduced high signal to the PMOS transistor 840 as described above. The control signal on control input 430 is an inverted signal of the output signal on output 870 generated as described above. This prevents any non-negligible current from leaking through the PMOS transistor 840, thus saving power. It should be noted that since the voltage modulation circuit 400 is arranged along the existing current path between V _dd and Gnd, no additional current path is formed. The reduced high signal on inputs 850, 860 is sufficient to form a connection between ground voltage supply 350 and output 870, and a low signal is suitably provided on output 870.

  Referring to FIG. 9, the control input 430 can be alternatively connected to either one of the gates of the second NMOS transistor 410 and the second PMOS transistor 420 as shown. The result is a capacitive load on the control input 430. Since the transistor gate has its own capacitance, the capacitance increases because of the connection to the additional transistor gate. However, this configuration is compatible with certain silicon configurations, such as those used in metal mask programmable gate arrays that tend to place transistors in N / P pairs with their gates coupled together. Good.

  The advantage of the voltage modulation circuit 400, 500 described above compared to a weak pull-up transistor is that the device strength relative to the voltage modulation circuit 400, 500 is independent because the optimum device strength does not depend on the resistance in the signal path connected to the input 310. It is easy to select. FIG. 10 shows a circuit 1000 similar to the circuit of FIG. 4, where the control signal is supplied by the inverted output of inverter 300 via connection 1020 and output inverter 1010.

In order for circuit 1000 to function, the change in the input signal at input 310 needs to be communicated to output 1030. This conversely means that the output inverter 1010 must be able to invert even if the control signal on connection 1020 is in the wrong state. Since the control signal is derived from the output inverter 1010, a non-zero propagation delay can occur where the input to the output inverter 1010 is high at the same time as the signal on connection 1020 is high. Since the control signal on connection 1020 is high, voltage modulation circuit 400 is only providing a reduced high signal V _dd −V _{t (N2)} to inverter 300. When input 310 is low, inverter 300 provides a decreasing high signal to the output of inverter 300, which becomes the input to output inverter 1010. Thus, the output inverter 1010 can be switched threshold voltage lower than V _dd −V _{t (N2)} to ensure that the output inverter 1010 can invert in all possible situations (the output inverter 1010 transitions from high to low. Voltage). This is a restriction on the relative strength of the device in the output inverter 1010 and does not depend on anything connected to the input 310.

  The restrictions on the strength of the second NMOS transistor 410 and the second PMOS transistor 420 are more relaxed than those of the output inverter 1010. If either transistor 410, 420 is formed above or below optimum strength, the circuit 1000 operates at a lower speed but still functions normally. The constraints on the size of the transistors 410, 420 are similar to the constraints on the size of any other transistor in the logic circuit and can be approached in the same way. Those skilled in the art will readily be able to evaluate these constraints and make an appropriate selection for the strength of the transistors 410,420. For the circuit of FIG. 10, it is typically functional to select the second NMOS transistor 410 the same as the strength of the first NMOS transistor 340 and the second PMOS transistor 420 the same as the strength of the first PMOS transistor 330. The result is that it is easy to be physically compact (more generally, for any logic circuit, selecting a transistor of a voltage modulation circuit to be as strong as a transistor of a logic device is typically Is a functionally favorable result).

  As mentioned above, the optimum size of the pull-up transistor 130 in FIG. 1 depends on the resistance of the circuit driving the input, which is a function of the path through the routing network the signal has followed. In voltage modulation circuit 400, input 310 is connected to the gates of transistors 330 and 340 forming inverter 300 rather than the source or drain of the transistor. The correct operation of the inverter 300 depends on a switching threshold that is between the maximum and minimum voltages that can be transmitted through the routing network. These voltages do not depend on the path that the signal follows through the routing network, so the required inverter threshold is independent of the input signal route. Similarly, the required threshold of the second NMOS transistor 410 also depends on the highest voltage transmitted through the routing network, but otherwise is independent of the network characteristics.

A further consideration is the selection of the length of the second NMOS transistor 410. As described above, the leakage current through the first PMOS transistor 330 depends on the threshold voltage difference between the second NMOS transistor 410 and the device connected to the input 310 (eg, an NMOS pass transistor in the routing network). The threshold voltage of the second NMOS transistor 410 is preferably higher than the threshold voltage of the device connected to the input 310 in order to prevent leakage current from flowing through the first PMOS transistor 330. The higher V _{t (N2)} , the lower the source voltage V _dd -V _{t (N2)} of the first PMOS transistor 330 and the gate voltage V _dd -V _{t (pass)} (supplied by the input 310) is the source. Leakage is less likely to occur due to the fact that a situation where the voltage is lower than the voltage is less likely to occur.

  In many CMOS processes, the threshold voltage of a transistor is a function of the length of the transistor. The graph of FIG. 11 shows an example of this function when one CMOS process is taken as an example. The vertical line represents the minimum transistor length actually produced by this CMOS processing example. In the region near the minimum length, the threshold voltage increases rapidly as the transistor length increases. The curve becomes flat at about twice the minimum length and eventually decreases slightly. An NMOS pass transistor, such as that connected to input 310 in some embodiments, is typically the minimum length. Therefore, by selecting the length of the second NMOS transistor 410 to match the higher point on the threshold voltage curve, the second NMOS transistor 410 will be selected to have a relatively high threshold. The risk of variations in the length of pass transistors or other devices connected to the input 310 that cause leakage can be minimized.

In other embodiments, the voltage degradation effects of active devices in the configurable routing network are compensated by supplying different voltages to the active devices rather than logic circuits. For example, the second high supply voltage is supplied to the pass transistor using an NMOS pass transistor routing network such that the gate voltage of the pass transistor is higher than the first high supply voltage V _dd supplied to the logic circuit. The first high supply voltage V _dd may be set lower than most positive allowable operating voltages for circuit technology to obtain the required difference between the first and second high supply voltages. This second high supply voltage is supplied to the gate of the pass transistor so that the pass transistor can transmit the highest voltage up to V _dd . Similarly, for the PMOS pass transistor routing network, the second low supply voltage is supplied to the pass transistor, so that the gate voltage of the pass transistor is lower than the first low supply voltage Gnd supplied to the logic circuit. The first low supply voltage Gnd may be set higher than most negative allowable operating voltages for circuit technology in order to obtain the required difference between the first and second low supply voltages. This second low supply voltage is supplied to the gate of the pass transistor, reducing the minimum voltage that can be transmitted by the pass transistor to Gnd. A second high or low supply voltage routing network may be provided, and the level shift buffer may be provided on signals that communicate between elements using different supply voltages. For active devices that degrade high and low, both a second high supply voltage and a second low supply voltage are provided.

Referring to FIG. 12 again, the second supply voltage V _control is supplied onto the control wire 50. In the description so far, it has been assumed that V _control is equal to V _dd , that is, the NMOS pass transistor 40 can transmit only a reduced high signal of V _dd −V _{t (pass)} . In this alternative embodiment, where the second supply voltage V _control is not equal to V _dd , the NMOS pass transistor 40 can transmit a high signal of V _control −V _{t (pass)} . If V _control is selected to be greater than or _equal to V _dd + V _{t (pass)} , the high signal transmitted by the NMOS pass transistor can be up to V _dd . Therefore, the reconfigurable network including the NMOS pass transistor can transmit a non-degraded high signal of V _dd if V _control is selected to be V _dd + V _{t (pass)} or higher. Similarly, a reconfigurable network including a PMOS pass transistor has a negative value of V _{t (pass)} , and if the second supply voltage V _control is selected to be less than or equal to Gnd + V _{t (pass)} , the non-degraded low signal of Gnd Can be transmitted.

  In the foregoing specification, the invention has been described with reference to specific embodiments. However, it will be apparent that various changes and modifications may be made to the invention without departing from the broader spirit and scope of the invention. For example, the specific configurations and combinations of elements shown in the circuit diagrams described herein are merely illustrative, and the invention may be practiced using different or additional elements, or different configurations or combinations of elements. It will be understood that this is possible. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive, and the invention is not to be restricted or restricted except in accordance with the appended claims and their legal equivalents. .

A weak pull-up circuit is shown. 1 shows a differential amplifier. An inverter introduced into CMOS logic is shown. Fig. 4 shows a voltage modulation circuit connected to the positive voltage supply input of the inverter of Fig. 3 according to one embodiment of the present invention. Fig. 4 shows a voltage modulation circuit connected to the ground of the inverter of Fig. 3 according to a second embodiment of the present invention. 4 shows a voltage modulation circuit according to a third embodiment of the present invention, which is connected to the positive voltage supply input and the ground voltage supply input of the inverter of FIG. Fig. 4 illustrates a voltage modulation circuit connected to a CMOS NAND gate and according to one embodiment of the present invention. Fig. 4 illustrates a voltage modulation circuit connected to a CMOS NOR gate and according to one embodiment of the present invention. Fig. 2 shows a voltage modulation circuit according to one embodiment of the present invention having a control signal connected to both a converter and a bypass circuit. The control signal is derived from the inverted signal of the output signal of the target circuit, and shows a voltage modulation circuit according to one embodiment of the present invention. 3 shows a graph representing the relationship between transistor length and transistor threshold voltage. A reconfigurable device is shown.

Claims (25)

A reconfigurable device,
A plurality of processing devices each having a processing device input and a processing device output;
A configurable routing network connecting at least one of the processing device outputs to at least one of the processing device inputs;
Located between the configurable routing network and the processor input, at least one of which comprises a plurality of input buffer circuits comprising logic circuits and voltage modulation circuits;
The configurable routing network is a reconfigurable device that provides a degraded voltage input signal to one or more input buffer circuits.   The reconfigurable device of claim 1, wherein the configurable routing network comprises a plurality of pass transistors. The voltage modulation circuit receives a non-degraded supply voltage signal and supplies an output supply voltage signal to the logic circuit;
The reconfigurable device of claim 1, wherein the output supply voltage signal comprises either the non-degraded supply voltage signal or a degraded supply voltage signal. The logic circuit is:
A logic circuit input for receiving the degraded voltage input signal from the configurable routing network;
A supply voltage input for receiving the output supply voltage signal from the voltage modulation circuit;
With logic circuit output,
The voltage modulation circuit includes:
A voltage modulation circuit input for receiving the non-degraded supply voltage signal;
A voltage modulation circuit output for supplying the output supply voltage signal to the supply voltage input;
A converter that converts the non-degraded supply voltage signal into the degraded supply voltage and supplies the degraded supply voltage signal to the voltage modulation circuit output;
A bypass circuit that bypasses the converter and supplies the non-degraded supply voltage signal to the voltage modulation circuit output;
4. A control input for receiving a control signal for selection between the converter and the bypass circuit to supply the output supply voltage signal to the voltage modulation circuit output. Reconfigurable device.   The reconfigurable device of claim 4, wherein the converter comprises a transistor.   6. The reconfigurable device of claim 5, wherein the transistor comprises a gate input and the control input is connected to the gate input of the transistor.   6. The reconfigurable device of claim 5, wherein the transistor has a gate input, and the voltage modulation circuit input is connected to the gate input.   The reconfigurable device of claim 4, wherein the bypass circuit comprises a transistor.   9. The reconfigurable device of claim 8, wherein the transistor has a gate input, and the control input is connected to the gate input of the transistor.   The reconfigurable device of claim 4, wherein the bypass circuit comprises a resistor.   The reconfigurable device of claim 4, wherein the non-degraded supply voltage has a high value, and the deteriorated supply voltage has a decreasing high value lower than the high value.   12. The reconfigurable device of claim 11, wherein the voltage modulation circuit is connected to a positive supply voltage and the high value is substantially equal to the positive supply voltage.   The reconfigurable device of claim 11, wherein the high value comprises a high CMOS voltage.   12. The reconfigurable device of claim 11, wherein the configurable routing network comprises a device having a threshold voltage, and the reduced high value is approximately equal to the high value minus an absolute value of the threshold voltage.   5. The reconfigurable device of claim 4, wherein the non-degraded supply voltage comprises a low value, and the degraded supply voltage comprises an increased low value that is higher than the low value.   16. The reconfigurable device of claim 15, wherein the voltage modulation circuit is connected to a ground voltage, and the low value is substantially equal to the ground voltage.   The reconfigurable device of claim 15 wherein the low value comprises a low CMOS voltage.   16. The reconfigurable of claim 15, wherein the configurable routing network comprises a device having a threshold voltage, and the increased low value is approximately equal to the low value plus an absolute value of the threshold voltage. apparatus.   The at least one input buffer circuit is connected to a positive supply voltage and a ground voltage, and the voltage modulation circuit does not form any additional current path between the positive supply voltage and the ground voltage, but between the ground voltage logic. The reconfigurable device of claim 1, wherein the reconfigurable device is connected to a circuit.   5. The reconfigurable device of claim 4, wherein the control signal is based on an output signal provided on the logic circuit output.   21. The reconfigurable device of claim 20, wherein the control signal is equal to an inverted signal of the output signal.   5. The reconfigurable device of claim 4, wherein the voltage modulation circuit output is connected to the supply voltage input to allow current to flow from the voltage modulation circuit output to the supply voltage input.   23. The reconfigurable device of claim 22, wherein the voltage modulation circuit output is connected to the supply voltage input to allow current to flow from the voltage modulation circuit input to the logic circuit output. The voltage modulation circuit receives a second non-degraded supply voltage signal and supplies a second output supply voltage signal to the logic circuit;
The reconfigurable device of claim 4, wherein the second output supply voltage signal comprises either the second non-degraded supply voltage signal or a second degraded supply voltage signal. The logic circuit further comprises a second supply voltage input for receiving a second output supply voltage signal,
The voltage modulation circuit includes:
A second voltage modulation circuit input for receiving the second undegraded supply voltage signal;
A second voltage modulation circuit output for supplying the second output supply voltage signal to the second supply voltage input;
A second converter for converting the second non-degraded supply voltage signal to the second degraded supply voltage and supplying the second degraded supply voltage signal to the second voltage modulation circuit output;
A second bypass circuit that bypasses the second converter and supplies the second non-degraded supply voltage signal to the second voltage modulation circuit output;
A second control input for receiving a second control signal for selecting between the second converter and the second bypass circuit to supply the second output supply voltage signal to the second voltage modulation circuit output; 25. The reconfigurable device of claim 24, comprising:

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