JP4201665B2 - Signal transmission device - Google Patents

Description

  The present invention relates to a signal transmission device, and more particularly to a signal transmission device that transmits a differential signal having a small amplitude. More particularly, the present invention relates to an LVDS (Low Voltage Differential Signal) drive circuit.

  In a data transfer interface or the like, a small amplitude signal is transferred. One such interface standard is LVDS (Low Voltage Differential Signal). LVDS is a differential signal transmission standard characterized by high transmission speed, small signal amplitude, low power consumption, and small electromagnetic interference. A cable or the like is used as a transmission path for transmitting the differential signal.

  In order to achieve impedance matching in the transmission path, a terminating resistor is disposed between the differential signal lines on the receiving circuit side. A potential difference generated at both ends of the terminating resistor is detected on the receiving circuit side. A current is transmitted from the transmission circuit side through the differential signal transmission path in a direction corresponding to the transmission signal. The voltage generated between the terminating resistors when the current flows through the terminating resistor, that is, the differential amplitude VOD of the transmission side output signal is kept constant. In the LVDS standard, the resistance value of the termination resistor is 100Ω and the output amplitude VOD is 350 mV.

  Such transmission devices for transmitting differential signals with a small amplitude are disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2000-59443), Patent Document 2 (Japanese Patent Laid-Open No. 6-104936), and Patent Document 3 (Japanese Patent Laid-Open No. Hei 3). No. 209829).

  Patent Document 1 discloses an interface in which a terminating resistor is connected to each of a transmission side and a reception side of a differential transmission line. By arranging termination resistors at both ends of the differential transmission path, the differential transmission path is used as a bidirectional transmission path. In such an interface, in particular, in Patent Document 1, when data is transmitted from the transmission side device, the termination resistor provided in the transmission side output unit is separated from the transmission line, and current is supplied only to the termination resistor on the reception side. Thus, the power consumption during data transfer is reduced.

  In the configuration disclosed in Patent Document 2, a one-shot pulse signal is generated in response to the transition of transmission data, and this pulse signal is transmitted according to the NRZ (non-return-to-zero) method. A resistive element is arranged in series on the differential signal transmission line on the transmission side, and a resistive element (termination resistive element) is connected between the differential signal line pair on each of the transmitting side and the receiving side. At the time of data transmission, a small amplitude signal is transmitted by the partial pressure of the series resistance and the terminating resistance on the transmission side. At the time of signal transmission, a ternary differential signal of 1, 0, −1 is transferred to identify the rising edge and falling edge of the data signal. On the receiving side, the original pulse signal, that is, transmission data is restored from the ternary differential signal. A small-amplitude signal is transmitted by dividing the series resistance and termination resistance on the transmission side, and a signal that does not include a DC fluctuation component in the signal pattern is transmitted, so that charging / discharging of the line capacitance and the reception side are performed. It is possible to prevent a direct current shift from occurring in the signal identification level and to transfer data over a long distance signal transmission line at high speed.

In Patent Document 3, a signal transmission path is formed of a twisted wire pair, the twisted wire is terminated on the transmitting side, and a resistance element is connected between the twisted wires on the receiving side. This patent document 3 uses the fact that the current flowing through the transmission line is determined by the parallel resistance of the resistance between the terminating resistor and the twisted wire on the receiving side, to reduce current consumption during data transfer. Plan. Further, the resistance element between the pair of differential lines on the receiving side is used to increase the rate of change of the current signal on the receiving side, thereby realizing high-speed signal transmission.
JP 2000-59443 A JP-A-6-104936 Japanese Patent Laid-Open No. 3-209829

  In any of Patent Documents 1 to 3 described above, a termination resistor having a resistance value that matches the characteristic impedance of the transmission line is arranged to prevent the generation of a reflected wave due to impedance mismatch of the transmission line. In other words, it is assumed that the impedances of the terminating resistor and the transmission line match.

  In the configuration shown in Patent Document 1, the terminating resistor is built in a module (chip). Therefore, when the resistance value of the termination resistor fluctuates due to variations in the manufacturing process, impedance mismatching occurs in the transmission line, causing a problem of signal quality degradation due to reflected waves. This Patent Document 1 does not take into consideration the problem of variation in the resistance value of the internal termination resistor due to variations in manufacturing parameters.

  Japanese Patent Laid-Open No. 2004-228561 uses an externally attached resistance element (connected to the outside of the apparatus) as a terminal resistance and a series resistance for limiting the amplitude. When individual elements are used as such external resistance elements, their resistance values vary within a certain range. Therefore, even in the configuration shown in Patent Document 2, there arises a problem of impedance mismatch due to variation in resistance value. Further, the signal amplitude is determined by a voltage dividing circuit of a series resistor and a terminating resistor. Therefore, when the resistance value of the series resistor fluctuates, there arises a problem that the signal amplitude on the receiving side changes and the operation margin of the receiving side input circuit changes. This Patent Document 2 also does not consider the problem of variation in resistance value.

  Patent Document 3 transmits a signal in the form of a differential signal between circuit cells in an integrated circuit device. Therefore, when the resistance value of the termination resistance of the transmission line varies due to variations in manufacturing parameters, a problem of impedance mismatch of the transmission line occurs. The received signal amplitude is set by dividing the resistance between the terminating resistor on the transmitting side and the differential signal line on the receiving side. Therefore, when the resistance value varies, the signal amplitude similarly changes. Patent Document 3 also presupposes that impedance matching is established between the signal transmission path and the termination resistor, and does not consider any problem of resistance value variation due to parameter variations during manufacturing.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a signal transmission device capable of reliably transmitting a differential signal having a constant amplitude without generating a reflected wave even when a transmission-side termination resistor is incorporated.

  Another object of the present invention is to provide a signal transmission device capable of accurately transmitting a small-amplitude signal without causing a reflected wave without being affected by variations in the resistance value of the transmission-side termination resistor. is there.

A signal transmission device according to a first aspect of the present invention is a device formed on a semiconductor chip, and includes a differential signal output node pair coupled to a differential signal line pair, and the differential signal output node pair. A first resistance element coupled between the current supply circuit, a current supply circuit, a drive stage that receives the current of the current supply circuit as an operating current and drives a differential signal output node according to a given signal, and a current supply circuit Is connected to an external adjustment node for externally adjusting the current supplied by the current supply circuit, and includes a second resistance element for internally adjusting the current supplied by the current supply circuit. A termination resistor of the receiving side device is connected to the differential signal line pair. An external adjustment resistor is connected to the external adjustment node in parallel with the second resistance element outside the semiconductor chip. The resistance ratio between the external adjustment resistor and the second resistance element is made substantially equal to the resistance ratio between the termination resistor and the first resistance element.

A signal transmission device according to another aspect of the present invention is a device integrated on a semiconductor chip, and drives a differential output node according to a given signal, and supplies an operating current to the drive stage. The second current for adjusting the amount of current supplied from the first current source, the second current source, the first resistance element, and the second current source whose amount of supply current can be adjusted from the outside of the chip . And the supply current from the second current source to the drive stage in parallel with the first current source according to the given signal, and the first resistance element is connected between the differential signal output nodes Control circuit. The first current source supplies a current having a magnitude corresponding to the current flowing through the terminating resistor of the receiving device. The termination resistor is connected between the signal line pair connected to the differential output node.

  The operating current of the transmission side drive stage is adjusted by the second resistance element. The first and second resistance elements are formed in the vicinity region on the same semiconductor chip. Therefore, even if the resistance value of the transmission-side termination resistor varies due to variations in parameters during manufacturing, the same variation occurs in the second resistance element. The external resistance element determines the amount of current corresponding to the current flowing through the reception-side termination resistor, and the amount of current flowing through the first resistance element is determined by the second resistance element. A current flows through the reception-side termination resistor and the first resistor element at a ratio corresponding to the resistance ratio between the external resistor and the second resistor element. Therefore, since the same variation as the variation of the first resistance element occurs in the second resistance element, the drive current of the drive stage can be adjusted so as to offset the influence of the variation in the resistance value of the first resistance element. In response, a constant current can be supplied to the receiving side. As a result, it is possible to cancel the influence of the variation in the resistance value of the transmission-side termination resistor, and to reliably suppress the reflected wave and transmit a signal having a constant amplitude.

  In addition, current consumption can be reduced by supplying an operating current to the drive stage only for a predetermined period.

  A resistor element is connected between the differential signal output nodes of the signal transmission device, and the resistor element is connected to the current supply circuit in parallel with the resistor element that sets the supply current to the receiving-side termination resistor on the same semiconductor chip as the resistor element Configure to connect. Therefore, even when the impedance of the differential transmission line does not match the resistance value of the reception-side termination resistor, a differential voltage with the same amplitude can be generated on the transmission side and the reception side of the differential transmission line, and the reflected wave It is possible to accurately transmit the signal / data without causing the error.

  In addition, the resistance element for absorbing the reflected wave and the resistance element for setting the supply current of this resistance element are integrated on the same semiconductor chip. Even if the manufacturing parameters vary, the resistance value varies in the same direction and the manufacturing Even if there is a variation in parameters, it is possible to maintain the predetermined resistance ratio and accurately set the supply current so that the same differential voltage is generated in the reflected wave absorption resistance element and the reception-side termination resistor. it can.

  In addition, during signal / data transfer, the supply current to the reflected wave absorption resistance element is supplied to the drive circuit only for a predetermined period in response to the signal / data transition, and the reflected wave absorption resistance element is used as a differential signal. Connected between output terminals. Therefore, the current for absorbing the reflected wave is consumed only during the necessary period, and the current consumption can be reduced.

[Embodiment 1]
1 is a diagram showing a configuration of a signal transmission apparatus according to Embodiment 1 of the present invention. In FIG. 1, the signal transmission device 1 is connected to a reception unit 10 via an LVDS cable (differential signal transmission path) 5. The LVDS cable 5 includes differential signal lines GLa and GLb, and transmits a differential signal transferred from the signal transmission device 1 via the differential terminals (D +, D−) to the receiving unit 10. The signal transmission device 1 is integrated on a semiconductor chip.

  The signal transmission device 1 is supplied with current from the current supply circuit 20 that supplies current supplied to the LVDS cable 5 during signal transmission and the current supply circuit 20, and supplies current to the LVDS cable 5 according to the input signal (data) IN. A resistance element R3 connected between the drive circuit 30 to be supplied and the output nodes (differential terminals D + and D−) of the signal transmission device 1, and a resistance element R4 for adjusting the amount of current supplied by the current supply circuit 20 including. Resistance elements R3 and R4 are integrated on a semiconductor chip on which signal transmission device 1 is formed.

  In the input unit of the receiving unit 10, a termination resistor R2 is connected between the differential signal lines GLa and GLb. In the adjustment node S2 of the signal transmission device 1, the resistor element R1 is connected in parallel with the resistor element R4 so that the current supply circuit 20 supplies the current I2 flowing through the termination resistor R2. The resistance element R1 is an external resistor connected to the outside of the semiconductor chip on which the signal transmission device 1 is formed. On the other hand, the resistance element R4 is provided inside the chip so that the current supply circuit 20 supplies the current I3 flowing through the resistance element R3. Therefore, the ratio of the resistance values of the resistance elements R1 and R4 is set to be equal to the ratio of the resistance values of the resistance elements R2 and R3. As a result, the ratio of the current flowing through the resistance elements R1 and R4 is made equal to the ratio of the current flowing through the resistance elements R2 and R3.

  The current supply circuit 20 includes a reference voltage generation circuit (bandgap reference) circuit BGR that generates a reference voltage VBGR, a differential amplifier AMP that differentially amplifies the voltage VFB and the reference voltage VBGR on the node S2, and a differential amplifier An N-channel MOS transistor (insulated gate field effect transistor) TR1 whose conductance is adjusted in accordance with the output signal of AMP to pass a current between node S1 and node S2, and connected between the power supply node and node S1 and P channel MOS transistor TR2 having a gate connected to node S1 and P channel MOS transistor TR3 connected between the power supply node and operating power supply node S3 of drive circuit 30 and having its gate connected to node S1.

  The ratio of the sizes of MOS transistors TR2 and TR3 (ratio of channel width to channel length) is set to 1: k. These MOS transistors TR2 and TR3 form a current mirror circuit. Therefore, a current k times the current flowing through the MOS transistor TR2 flows through the MOS transistor TR3.

  In the current supply circuit 20, the differential amplifier AMP compares the voltage VFB on the node S2 with the reference voltage VBGR. When the reference voltage VBGR is higher than the voltage VFB on the node S2, the differential amplifier AMP outputs a high level signal, increases the conductance of the MOS transistor TR1, and the current flowing from the node S1 to the node S2. To increase the voltage level of the voltage VFB. On the other hand, when the voltage VFB on the node S2 is higher than the reference voltage VBGR, the differential amplifier AMP outputs a low level signal, reduces the conductance of the MOS transistor TR1, and connects the node S1 to the node S2. Reduce (or stop) supply current.

  Therefore, the differential amplifier AMP adjusts the amount of current flowing through the MOS transistor TR1 so that the voltage VFB on the node S2 becomes equal to the reference voltage VBGR.

  The current Ir flowing through the MOS transistor TR1 is supplied to the resistance elements R1 and R4. The resistance values of the resistance elements R1 and R4 are set so that the ratio of the resistance values of the resistance elements R1 and R4 is equal to the ratio of the resistance values of the resistance elements R2 and R3. Voltage VFB on node S2 is given by the following expression when the combined resistance of resistance elements R1 and R4 is represented by R1 // R4.

VFB = Ir · (R1 // R4)
The voltage level of voltage VFB is adjusted to be equal to reference voltage VBGR. The resistance values of the resistance elements R1 and R4 are fixed. Therefore, the current Ir flowing through the MOS transistor TR1 becomes a constant current when stabilized.

  The current Ir flowing through the MOS transistor Tr1 is supplied from the MOS transistor TR2. Therefore, the current supplied by the MOS transistor TR3 is k · Ir. MOS transistor TR3 supplies currents I2 and I3 flowing through resistance elements R2 and R3, respectively. Therefore, a current (I2 + I3) flows through the MOS transistor Tr3, and a current (I2 / k + I3 / k) flows through the MOS transistor TR2.

  Drive circuit 30 is connected between operating power supply node S3 and node S4 and connected between operating power supply node S3 and node S5, with P channel MOS transistor TR4 receiving a signal IN through inverter IU at its gate, and P channel MOS transistor TR5 receiving signal IN at its gate via buffer BF, N channel MOS transistor TR6 connected between nodes S4 and S6 and receiving the output signal of inverter IV at its gate, and nodes S5 and S6 N channel MOS transistor TR7 connected in between and receiving the output signal of buffer BF at its gate, and a resistance element R5 connected between node S6 and the ground node. The resistance element R5 limits the output signal amplitude of the drive circuit 30. kS4 and S5 are connected to current source differential terminals D; and D-, respectively.

  When signal IN is at H level (logic high level), the output signal of inverter IV is at L level (logic low level), the output signal of buffer circuit GF is at H level, MOS transistors TR4 and TR7 are on, and MOS Transistors Tr5 and TR7 are turned off. Therefore, in the MOS transistor TR4, the current from the current supply circuit 20 is transferred to the receiving unit 10 via the LVDS cable 5 via the node S4 and the node D +.

  The current flowing through the differential signal line GLa of the LVDS cable 5 flows to the output terminal D− through the termination resistor R2 and the differential signal line GLb on the receiving unit 10 side. At this time, the current I3 flows through the resistance element R3 between the current source differential terminals D + and D−. Resistive elements R3 and R2 are connected in parallel to the signal lines GLa and GLb of the LVDS cable 5.

  When the current source differential terminals D + and D− are driven by the drive circuit 30, in the current supply circuit 20, the amount of current flowing through the resistance elements R2 and R3 flows to the resistance elements R1 and R4 via the MOS transistors TR2 and TR1. It is determined by the current Ir. The resistance values of the resistance elements R1 and R4 are equal to the ratio of the resistance values of the resistance elements R2 and R3. Therefore, the ratio of currents flowing through these resistance elements R1 and R4 is equal to the ratio of currents flowing through resistance elements R2 and R3. Therefore, the current I2 / k flows through the resistance element R1, and the current I3 / k flows through the resistance element R4. The following equation (1) is established between the resistance values of the resistance elements R1 and R4 and the current.

R1 (I2 / k) = R4 (I3 / k) = VFB = VBGR (1)
From the above equation (1), the following equation (2) is obtained.

I2: I3 = R4: R1 = R3: R2 (2)
Therefore, the following expression (3) is established in the termination resistors R3 and R2 at both ends of the transmission line, and the voltages at both ends of the termination resistors R3 and R2 are equal.

I3 · R3 = I2 · R2 (3)
Therefore, even if the voltages at both ends of the termination resistors R2 and R3 are equal, the impedance of the LVDS cable 5 is different from the specified value, and the impedances of the termination resistor R2 and the LVDS cable 5 are mismatched, the reflected wave from the receiving unit 10 Can be absorbed by the current I3 flowing through the resistance element R3, and signals having the same amplitude are transferred on the transmission side and the reception side. Therefore, the voltage VOD between the current source differential terminals D + and D− becomes a constant voltage level that is not affected by the reflected wave, and signal quality deterioration due to impedance mismatch of the signal transmission path can be prevented.

  Also, the resistance elements R3 and R4 are integrated in the signal transmission device 1, and the resistance elements R3 and R4 are made of the same material and are manufactured in the same manufacturing process. Even if the resistance value of the resistance element R3 varies in the manufacturing process, the same resistance value variation occurs in the resistance element R4. The ratio of the resistance values of the resistance elements R2 and R3 is represented by the ratio of the resistance values of the resistance elements R1 and R4, and the resistance ratio is maintained. Therefore, the ratio of the currents flowing through the resistance elements R2 and R3 can be maintained at the ratio of the currents flowing through the resistance elements R1 and R4, and the influence of fluctuations in resistance values due to parameter variations during the manufacturing process can be offset. In other words, the influence of the variation in resistance value on the differential voltage VOD can be offset.

  Therefore, the voltage VOD between the current source differential terminals D + and D− can be maintained at a constant voltage level without being affected by variations in parameters of the manufacturing process. Also in the receiving unit 10, the voltage between both ends of the resistance element R2 can be maintained at a constant voltage level, and the reflected wave can be suppressed and accurate signal transmission can be realized.

  As described above, according to the first embodiment of the present invention, the resistance element is arranged between the differential output nodes of the signal transmission device that transmits the differential signal, and the supply current of the differential signal current source is adjusted. The resistance element is integrated in the signal transmission device, so that fluctuations in the differential output voltage due to process variations can be suppressed, and differential signals with a constant amplitude can be transmitted stably. .

[Embodiment 2]
FIG. 2 shows a configuration of the signal transmission apparatus according to the second embodiment of the present invention. The configuration of the signal transmission device 1 shown in FIG. 2 differs from the signal transmission device 1 shown in FIG. 1 in the following points. That is, the switching transistor SW1a and the resistance element R3 are connected in series between the current source differential terminals D + and D−, and the resistance element R4 is connected to the node S2 via the switching element SW1b. The switching elements SW1a and SW1b are controlled to be conductive / non-conductive by the control circuit 40. The other configuration of the signal transmission device shown in FIG. 2 is the same as the configuration of the signal transmission device shown in FIG. 1, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  Each of switching elements SW1a and SW1b is formed of an N-channel MOS transistor as an example, and the channel resistance (on-resistance) during conduction has a value sufficiently smaller than the resistance values of resistance elements R3 and R4, or Resistance values of the resistance elements R3 and R4 are determined in consideration of the on-resistances of the switching elements SW1a and SW1b. The relationship between the resistance values of the paths of the resistance elements R1 to R4 is the same as that in the first embodiment. A voltage having the same amplitude as the tea ceremony voltage VOD between the current source differential terminals D + and D− is generated at both ends of the reception-side termination resistor R2.

  By satisfying this relationship, when switching elements SW1a and SW1b are turned on, current I3 / k corresponding to current I3 flowing through resistance element R3 flows through resistance element R4. Further, a current I2 / k corresponding to the current I2 flowing through the termination resistor R2 flows through the resistance element R1.

  When these switching elements SW1a and SE1b are non-conductive, the current path between the current source differential terminals D + and D− is cut off in the signal transmission device 1 and the current supply path to the resistance element R4 is cut off. In this case, the supply current I2 from the current supply circuit 20 flows through the termination resistor R2 provided on the receiving unit 10 side. Therefore, the amount of current supplied from the current supply circuit 20 can be reduced, and the current consumption of the signal transmission device can be reduced accordingly.

  This signal transmission device 1 is applied to various systems. When the transmission line length of the LVDS cable 5 is short, even if impedance mismatching occurs, the generated reflected wave is small and the possibility that the reflected wave is generated is small. Therefore, in this case, it is not particularly required to absorb the reflected wave using the resistance element R3. For such applications, the control circuit 40 sets the switching elements SW1a and SW1b to a non-conducting state.

  The control circuit 40 may be configured by a circuit that electrically stores a control signal, such as a register circuit, or the voltage level of the output signal is fixedly set by a fuse element or the like. Also good. Further, the control circuit 40 may set the voltage level of the output signal by setting the potential of a specific bonding pad, or may be configured by a mask wiring.

  In addition, the control circuit 40 sets the switching elements SW1a and SW1b to the non-conductive state at the time of low-speed data transfer where the influence of the reflected wave is small, and sets the switching elements SW1a and SW1b to the conductive state at the time of high-speed data transfer. It may be configured to reliably prevent the effects of waves. In this case, the voltage level of the switch control signal output from the control circuit 40 is set according to the data transfer mode.

  As described above, according to the second embodiment of the present invention, a switching element is connected in series with a transmission-side termination (reflected wave absorption) resistance element and a current is supplied to the resistance element. Similarly, switching elements are provided, and these switching elements are selectively set to a conductive / non-conductive state. Therefore, signal / data transfer can be performed with low current consumption in an environment where the generation of reflected waves is small, and the generation of reflected waves can be reliably suppressed in an operating environment where the generation of reflected waves is large.

[Embodiment 3]
FIG. 3 shows a configuration of the signal transmission apparatus according to the third embodiment of the present invention. The signal transmission device 1 shown in FIG. 3 is different from the signal transmission device shown in FIG. 2 in the following points. That is, a series body of the switching element SW2a and the resistance element R6 is connected between the current source differential terminals D + and D− in parallel with the switching element SW1a and the resistance element R3. Switching element SW2b and resistance element R7 are connected in parallel with switching element SW1b and resistance element R4 between current amount adjustment node S2 and ground node of current supply circuit 20. Switching elements SW1a and SW1b are controlled to be conductive / non-conductive by control circuit 42, and switching elements SW2a and SW2b are controlled to be conductive / non-conductive by control circuit 44.

  The ratio of the resistance values of the resistance elements R2, R3 and R6 is set to be equal to the ratio of the resistance values of the resistance elements R1, R4 and R7 when the on-resistance of the corresponding switching element can be ignored. That is, the relationship of R2: R3: R6 = R1: R4: R7 is satisfied. When the on-resistances of these switching elements cannot be ignored, the resistance values of the resistance elements R1-R4, R6, and R7 take into account the on-resistances of the switching elements SW1a, SW2a, SW1b, and SW2b. The voltage drop in the current path of the series body of the element and the switching element or the resistance element is set to be the same.

  In current supply circuit 20, resistance elements R1, R4 and R7 are connected in parallel to current amount adjustment node S2 when switching elements WS1b and SW2b are turned on. Therefore, the maximum current I2 / k + I3 / k + I6 / k flows through the MOS transistor TR2, and accordingly, the MOS transistor TR3 supplies the maximum current I2 + I3 + I6.

  Switching elements SW1a and SW1b are, for example, configured by N-channel MOS transistors, and channel resistances when conducting are set equal to each other. Switching elements SW2a and SW2b are also configured by N-channel MOS transistors and Channel resistances are set equal to each other.

  By setting the ratio of the resistances of the resistance elements R2, R3 and R6 (including the on-resistance of the switching element) equal to the ratio of the resistances of the resistance elements R1, R4 and R7 (including the on-resistance of the switching element), the resistance Currents I2 / k, I3 / k, and I6 / k corresponding to currents I2, I3, and I6 that flow through resistance elements R2, R3, and R6, respectively, can flow through elements R1, R4, and R7. Thereby, when the switching elements SW1a, SW1b, SW2a, and SW2b are turned on, the same voltage drop can be generated in these resistance elements R2, R3, and R6 without fail.

  The other configuration of the signal transmission device shown in FIG. 3 is the same as the configuration of the signal transmission device shown in FIG. 2, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  When the LVDS cable 5 and the termination resistor R2 are not matched and a reflected wave is generated, the control circuits 42 and 44 selectively set the switching elements SW1a and SW2a to the conductive state. When the reflected wave in the LVDS cable 5 is large, both the switching elements SW1a and SW2a are set in a conducting state, and the resistance elements R3 and R6 are connected between the current source differential terminals D + and D−, and the reflected wave absorption capability Is increased (the drive current amount is increased). At this time, since both switching elements SW1b and SW2b are in a conductive state, it is possible to reliably supply a current to resistance elements R3 and R6 to cause a voltage drop of the same magnitude in resistance elements R3 and R6.

  When the reflected wave is not so large, one of the switching elements SW1a and SW2a is set to a conductive state and the other is set to a non-conductive state, and one of the resistance elements R3 and R6 is set between the current source differential terminals D + and D−. Connecting. In this case, when the current values of the currents I3 and I6 flowing through the resistance elements R3 and R6 are different, the reflected wave can be reliably absorbed with finer accuracy according to the influence of the reflected wave.

  When there is almost no influence of the reflected wave, both the switching elements SW1a and SW2a are set to the non-conductive state, and the current supply to the resistance elements R3 and R6 is stopped.

  Control circuits 42 and 44 may monitor the transmission signal quality by a central controller (for example, CPU) (not shown) and set the output signal voltage level in an initialization sequence at the time of system startup.

  Further, a switching element conduction state control signal may be set in the control circuits 42 and 44 under the control of the central processing unit (CPU) according to the type of the LVDS cable 5 used in the applied system.

  The logic levels of the output signals of these control circuits 42 and 44 may be fixedly set by a fuse program circuit or the like.

  In the configuration shown in FIG. 3, two series elements of a switching element and a resistance element are connected in parallel between the differential output nodes of the drive circuit 30. However, a larger number of series bodies of switching elements and resistance elements may be provided. In this case, the resistance value of the corresponding resistance element is set so that a current of a magnitude corresponding to the resistance element connected to the switching element that conducts simultaneously flows in the reflected wave absorption resistance and the current amount adjustment resistance. (Including the on-resistance of the switching element).

  As described above, according to the third embodiment of the present invention, the plurality of resistance elements are configured to be selectively connected between the differential output nodes of the drive circuit, and the reflected wave is reliably suppressed. Signals / data can be transmitted under conditions with the best signal quality.

[Embodiment 4]
FIG. 4 shows a configuration of the signal transmission apparatus according to the fourth embodiment of the present invention. The signal transmission device shown in FIG. 4 differs from the signal transmission device shown in FIG. 2 in the following points. That is, resistance element R3 is coupled to current source differential terminals D + and D- through switching elements SW1a and SW1c provided at both ends thereof. The resistive element R4 has switching elements SW1b and SW1d connected in series at both ends thereof. That is, one end of the resistance element R4 is connected to the node S2 via the switching element SW1b, and the other end of the resistance element R4 is connected to the ground node via the switching element SW1d.

  These MOS transistors SW1a and SW1c are formed so that channel resistances (on-resistances) when conducting are equal, and switching elements SW1b and SW1d are formed so that channel resistances when conducting are equal.

  The resistance elements R1 to R4 are set so that the respective resistance values are the same as those in the first embodiment in consideration of the channel resistances (ON resistances) of the switching elements SW1a to SW1d. Is done.

  The other configuration of the signal transmission device shown in FIG. 4 is the same as that of the signal transmission device shown in FIG. 2, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  Switching elements SW1a to SW1d are each formed of an N-channel MOS transistor. The on-resistance (channel resistance when conducting) of a MOS transistor is determined by its gate-source voltage. In an N channel MOS transistor, a low potential node is a source node. Taking the switching element SW1a as an example, when a high level signal is output to the terminal D +, the source node of the switching element SW1a is a node connected to the resistance element R3. On the other hand, when a low level signal is output to the terminal D +, the source node of the switching element SW1a is a node connected to the terminal D +. Therefore, the gate-source voltage when the switching element WS1a is conductive differs, and the on-resistance varies accordingly.

  However, as shown in FIG. 4, terminals D + and D- output high level and low level signals by connecting N-channel MOS transistors constituting switching elements SW1a and SW1c to both ends of resistance element R3, respectively. When the time and the terminals D + and D− output low level and high level signals, respectively, the sum of the channel resistances (on resistances) of the N-channel MOS transistors constituting the switching elements SW1a and SW1c is constant. The differential potential VOD between the terminals D + and D− can always be maintained at a constant potential level regardless of the direction of current, that is, regardless of transmission data.

  Since the switching elements SW1a and SW1c are connected in series to both ends of the resistor element R3, the switching elements SW1b and SW1d are connected in series to the resistor element R4 at both ends of the resistor element R4 for current adjustment. The influence of the ON resistance of the switching elements SW1a and SW1b on the current flowing through the resistance element R3 is reflected on the current flowing through the resistance element R4. Even if the operating environment such as temperature fluctuates during operation, or even if the on-resistance of the switching elements SW1a and SW1c varies due to variations in parameters during the manufacturing process, fluctuations in the on-resistance of the switching elements SW1a and SW1c SW1b and Sw1d can be similarly generated, the resistance ratio of each current path can be accurately maintained, and a current corresponding to the current flowing through the resistance element R4 can be supplied to the resistance element R3.

  In the signal transmission device shown in FIG. 3, switching elements may be connected in series to both ends of each of the resistance elements R3, R6, R4, and R7.

  As described above, according to the fourth embodiment of the present invention, the switching element is connected in series to both ends of the reflected wave absorbing resistance element, or the current adjusting resistance element is correspondingly connected to both ends thereof. Since the switching elements are connected, a differential signal with a constant amplitude can be accurately generated regardless of the logic level of the output signal.

[Embodiment 5]
FIG. 5 shows a configuration of the signal transmission apparatus according to the fifth embodiment of the present invention. In the signal transmission device 1 shown in FIG. 5, a switching element SW1 and a resistance element R3 are connected in series between current source differential terminals D + and D−. The conduction / non-conduction of the switching element SW1 is controlled by a signal supplied from the control circuit 50 via the buffer circuit BFA.

  A terminating resistor R2 is disposed on the receiving unit (not shown in FIG. 5) side. At the time of signal transmission, a current source is separately provided for the drive circuit 30 in order to supply a current corresponding to the resistance ratio to the resistance elements R2 and R3.

  A current source for supplying a current to the resistance element R2 includes a differential amplifier AMP1 that compares the reference voltage VBGR from the reference voltage generation circuit BGR with the voltage VFB1 on the node S2a, and a node S1a according to an output signal of the differential amplifier AMP1. Operation of N channel MOS transistor TR10 for passing current between S2a and S2a, P channel MOS transistor TR11 connected between the power supply node and node S1a and having its gate connected to node S1a, and the power supply node and drive circuit 30 P channel MOS transistor TR12 connected between power supply node S3 and having its gate connected to node S1a is included.

  The resistance element R1 is connected to the node S2a outside the semiconductor value in which the signal transmission device 1 is formed. The size of MOS transistors TR11 and TR12 (ratio of channel width to channel length) is set to 1: k. Therefore, in this current source, the resistance value is set so that the current flowing through the resistance element R1 defines the current I2 flowing through the termination resistor R2. A current I2 / k flows through the resistance element R1, and a current I2 / k flows through the MOS transistor TR11 accordingly. Due to the current mirror operation, a current I2 flows through the MOS transistor TR12 and is supplied to the drive circuit 30. The operation of adjusting the voltage VFB1 to be equal to the reference voltage VBGR by feedback control of the differential amplifier AMP1 and the MOS transistor TR10 is the same as in the first embodiment, and the resistance of the reference voltage VBGR and the resistance element R1 A constant current determined by the value flows through the resistance element R1.

  As a current source for supplying a current I3 to the resistance element R3, a differential amplifier AMP2 that compares the voltage VFB2 on the node S2b with a reference voltage VBGR from the reference voltage generation circuit BGR, and a node S1b according to an output signal of the differential amplifier AMP2 N node MOS transistor TR15 for passing current between node S2b, P channel MOS transistor TR16 connected between the power supply node and node S1b and having its gate connected to node S1b, power supply node and drive circuit 30 P channel MOS transistors TR17 and TR18 connected in series with operating power supply node S3 are included.

  MOS transistor TR17 has its gate connected to node S1b, and MOS transistors TR16 and TR17 form a current mirror circuit with a mirror ratio k. Due to feedback control by the differential amplifier AMP2 and the MOS transistor TR15, a constant current determined by the reference voltage VBGR and the resistance value of the resistance element R4 flows to the MOS transistor TR16, and the MOS transistor TR17 is connected to the MOS transistor TR17 by the current mirror operation. A current k times the current flowing through TR16 flows.

  By setting the ratio of the resistance values of the resistance elements R1 to R4 to be R1: R4 = R2: R3 (considering the on-resistance of the switching element SW1), the resistance elements R2 and R3 when the switching element SW1 is turned on Can be supplied with currents (I2, I3) having a magnitude corresponding to the currents (I2 / k, I3 / k) flowing through the resistance elements R1 and R4.

  The output signal of control circuit 50 is applied to the gate of MOS transistor TR18 via inverter IVA. The control circuit 50 sets the MOS transistor TR18 and the switching element SW1 to a conductive state for a certain period according to the change of the input signal (data) IN.

  The configuration of drive circuit 30 is the same as the configuration of drive circuit 30 shown in the first to fifth embodiments, and current is supplied to current source differential terminals D + and D− according to the output signals of inverter IV and buffer circuit BF. Supply.

  During signal / data transmission, the current I3 supplied through the MOS transistor TR17 is supplied to the drive circuit 30 only during a period in which a reflected wave may occur due to impedance mismatch, and the resistance element R3 is connected to the current source differential terminal. Connect between D + and D-.

  When the signal / data waveform is stable, MOS transistor TR18 is set in a non-conductive state, and switching element SW1 is set in a non-conductive state. During this time, drive circuit 30 supplies current I2 supplied through MOS transistor TR12 to resistance element R2 through signal lines GLa and GLb of LVDS cable 5. By limiting the period during which the current I3 is supplied, current consumption can be reduced.

  FIG. 6 is a signal waveform diagram showing an operation at the time of signal / data transmission of the signal transmission apparatus shown in FIG. The operation of the signal transmission apparatus shown in FIG. 5 will be described below with reference to FIG.

  The control circuit 50 receives the signal / data IN and generates a one-shot pulse signal having a predetermined time width according to the change. When the output signal of drive circuit 30 (voltage level of terminal D +) rises, the output signal of inverter IVA becomes L level in accordance with the one-shot pulse signal from control circuit 50, MOS transistor TR18 becomes conductive, and from MOS transistor TR17. Current I3 is supplied to the operating power supply node S3 of the drive circuit 30. At this time, the output signal of the buffer BF becomes H level, the switching element SW1 becomes conductive, and the resistance element R3 is connected between the current source differential terminals D + and D−. As a result, the current source differential is obtained by connecting the resistance element R3 and absorbing the reflected wave during a period in which the reflected wave may be generated at the input unit of the receiving unit due to the impedance mismatch of the LVDS cable 5. The signal amplitudes of the terminals D + and D− can be set to a state corresponding to the output signal of the drive circuit 30, and the signal waveform at the input end of the receiving unit can be accurately raised accordingly.

  Similarly, when the output signal of the drive circuit 30 falls, a reflected wave in the opposite direction may be generated. Also at this time, the control circuit 50 detects the transition of the input signal IN and generates a one-shot pulse signal in response to the transition. Accordingly, the output signal of the buffer BFA is set to the H level and the output signal of the inverter IVA is set to the L level for a predetermined period, and the resistance element R3 is connected between the current source differential terminals D + and D− via the switching element SW1, The current I3 from the MOS transistor TR17 is supplied to the drive circuit 30 through the MOS transistor TR18. As a result, currents I3 and I2 are supplied to the resistance elements R3 and R2, respectively, and a voltage having the same amplitude as the differential voltage VOD of the current source differential terminals D + and D− can be generated at the receiving unit input unit. The generation of reflected waves can be reliably prevented.

  Since the reflected wave is not generated when the output signal of drive circuit 30 is stabilized, MOS transistor TR18 and switching element SW1 are set to a non-conductive state by control circuit 50. As a result, the MOS transistor TR17 is similarly rendered non-conductive, and the current driven by the MOS transistor TR17 can be reduced.

  The configuration of the control circuit 50 may be any circuit configuration that detects the transition of the input signal / data IN. For example, a delay circuit that delays the signal / data IN, an output of the delay circuit, and the signal / data IN The control circuit 50 can be configured by an EXOR gate receiving the above.

  In the configuration shown in FIG. 5 as well, switching elements may be connected in series to both ends of the resistance element R3. The resistance element R4 is directly connected to the node S2b. Therefore, the resistance value of the resistance element R4 is set in consideration of the on-resistance when the switching element SW1 is conductive. In this case, an N channel MOS transistor may be connected in series between resistance element R4 and node S2b, and the gate of the MOS transistor may be connected to the power supply node. In this case, the on-resistance of the MOS transistor which is always on can reflect the influence of the on-resistance on the current I3 when the switching element SW1 is conducted in the current flowing through the resistance element R4.

  As described above, according to the fifth embodiment of the present invention, when a transmission signal / data changes, a resistance element is connected between the current source differential terminals for a certain period and this reflected wave is absorbed by the drive circuit. A current to be supplied to the resistance element is supplied, and current consumption can be reduced while suppressing generation of reflected waves.

  The present invention is applicable to any interface that transmits a differential signal having a small amplitude and that is provided with a terminating resistor in the receiving unit.

It is a figure which shows the structure of the signal transmission apparatus according to Embodiment 1 of this invention. It is a figure which shows the structure of the signal transmission apparatus according to Embodiment 2 of this invention. It is a figure which shows the structure of the signal transmission apparatus according to Embodiment 3 of this invention. It is a figure which shows the structure of the signal transmission apparatus according to Embodiment 4 of this invention. It is a figure which shows the structure of the signal transmission apparatus according to Embodiment 5 of this invention. FIG. 6 is a signal waveform diagram illustrating an operation of the signal transmission device illustrated in FIG. 5.

Explanation of symbols

  1 signal transmission device, 20 current supply circuit, 30 drive circuit, 5 LVDS cable, R1-R7 resistance element, 40 control circuit, SW1a, SW1b, SW2a, SW2b, SW1c, SW1d, SW1 switching element, 42, 44, 50 control Circuit, TR1-TR7, TR10-TR18 MOS transistors.

Claims (10)

A signal transmission device that is formed on a semiconductor chip and drives a differential signal line pair in accordance with a given signal , the termination of a receiving-side device disposed outside the semiconductor chip between the differential signal line pair Resistors are combined,
A differential signal output node pair coupled to the differential signal line pair;
A first resistance element disposed on the semiconductor chip and coupled between the pair of differential signal output nodes;
A current supply circuit;
A drive stage that receives the current of the current supply circuit as an operating current and drives the differential signal output node pair according to the applied signal; and
Wherein said current supply circuit on the semiconductor chip are connected to current supplied externally adjustable external adjustment node, a second resistive element, wherein the current supply circuit to adjust the current supplied internally, the external An external adjustment resistor disposed outside the semiconductor chip is connected in parallel to the second resistance element, and a resistance ratio between the external adjustment resistor and the second resistance element is equal to the termination resistance. Ru is substantially equal to the resistance ratio of the first resistor element and the signal transmission device. Before SL current supply circuit, the supply current amount by the current flowing through said adjusting resistor and the second resistor element is determined,
2. The signal transmission device according to claim 1, wherein a current having a magnitude corresponding to a current flowing through the second resistance element flows through the first resistance element.   The signal transmission device according to claim 1, wherein the first resistance element and the second resistance element are formed of the same material. A first separation element for separating the first resistance element from the differential signal output node;
The signal transmission device according to claim 1, further comprising a second separation element for electrically separating the second resistance element from the adjustment node. The first separation element includes switching transistors connected in series with the first resistance element at both ends of the first resistance element, respectively.
5. The signal transmission device according to claim 4, wherein the second separation element includes switching transistors respectively connected in series with the second resistance element at both ends of the second resistance element. A third resistive element coupled between the differential signal output node pair in parallel with the first resistive element;
A fourth resistance element coupled to the external adjustment node in parallel with the second resistance element is further provided, and a ratio of resistance values of the first resistance element and the second resistance element is set to the third resistance element. The signal transmission device according to claim 1, wherein the signal transmission device is equal to a ratio of resistance values of the element and the fourth resistance element. A first separation element for separating the first resistance element from the differential signal output node;
A second separation element for separating the second resistance element from the differential signal output node;
A third separation element for separating the third resistance element from the adjustment node;
The signal transmission device according to claim 6, further comprising a fourth separation element for separating the fourth resistance element from the adjustment node. A signal transmission device integrated on a semiconductor chip,
A drive stage that drives the differential output node according to a given signal,
A first current source capable of adjusting a supply current amount from the outside of the semiconductor chip and supplying an operating current to the drive stage;
A second current source,
A first resistance element;
A second resistance element for adjusting a supply current of the second current source; and a drive for supplying a supply current from the second current source in parallel with the first current source in accordance with the given signal. A control circuit for supplying an operating current to the stage and connecting the first resistance element between the differential signal output nodes, wherein the second current source corresponds to a current flowing through the first resistance element; A current having a magnitude , and the first current source supplies a current having a magnitude corresponding to a current flowing through a termination resistor of a receiving-side device outside the semiconductor chip, and the termination resistor is configured to output the differential output. Ru is connected between the signal line pair connected to the node, the signal transmission apparatus.   The control circuit activates the second current source for a predetermined period in response to the transition of the applied signal, couples a current supply node to the drive stage, and sets the first resistance element for the predetermined period. The signal transmission device according to claim 8, wherein the signal transmission device is coupled between the differential output nodes. It said first and second current source separately provided, the supply current amount of the first current source is externally adjusted according to the impedance of the deployed terminating resistor to said receiving device, according Item 9. The signal transmission device according to Item 8.

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