JP4209792B2 - Semiconductor integrated circuit device and non-contact electronic device - Google Patents

Description

  The present invention uses a circuit inspection pad between a circuit inspection pad and an internal circuit in a cutting line before cutting the semiconductor wafer, and after cutting the semiconductor wafer, a cut end of a connection line with the circuit inspection pad. The present invention relates to a semiconductor integrated circuit device and a non-contact electronic device having a control circuit having a function of fixing or releasing the circuit.

  A so-called IC card in which a semiconductor integrated circuit device and an antenna are mounted in the card exchanges information between the reader / writer device and the semiconductor integrated circuit device, and the IC card holds the IC card. Many of the data holding functions for realizing various functions such as data transmission and data sending from a reader / writer are equipped with a non-volatile memory capable of holding data even when there is no power supply. For example, an EEPROM, which is a typical non-volatile memory, can erase or write data and retain data without a power supply by applying a high voltage to the memory element and changing the characteristics of the memory element. The data retention characteristics and the number of data rewrites of the memory element vary depending on a voltage (hereinafter simply referred to as “data write voltage”) used at the time of erasing or writing data. In order to improve the characteristics of the nonvolatile memory, it is necessary to adjust the voltage value of the data write voltage at the time of inspection before shipment.

  In addition, the semiconductor integrated circuit device mounted on the IC card receives a high-frequency signal supplied from the reader / writer device by the antenna mounted on the non-contact type IC card, and rectifies the voltage generated at both ends of the antenna. Smoothing and forming an internal voltage necessary for the operation of the internal circuit. The internal circuit operates by this internal voltage, and realizes the function as the IC card.

  In addition, there is a type in which an antenna coil is formed by a wiring layer formed on a semiconductor integrated circuit device to realize a function as an IC card. Thus, in the case of a semiconductor integrated circuit device having an antenna coil formed by a wiring layer, pads used before shipment cannot be arranged on the semiconductor integrated circuit device (see, for example, Patent Document 1).

On the other hand, the chip area of a semiconductor integrated circuit device is increasing with the higher functionality of the semiconductor integrated circuit device. For this reason, a pre-shipment inspection is provided by providing an inspection pad that is used only during a test (hereinafter, simply referred to as “pre-shipment inspection”) for determining whether a semiconductor integrated circuit device is good or defective before shipment. To improve efficiency. However, the use area of the pads on the semiconductor integrated circuit device is large, and there is a problem that the chip area increases. Therefore, by arranging inspection terminals that are used only during pre-shipment inspection on a cutting line for cutting after pre-shipment inspection, the efficiency of pre-shipment inspection is improved and the chip area is reduced. How to do is known. By using this technique, even when an antenna coil is provided on the semiconductor integrated circuit device, it is possible to improve the efficiency of inspection before shipment by arranging the inspection terminal on the cutting line (for example, , See Patent Document 2).
JP 2003-78023 A JP 2002-141383 A

  FIG. 1 shows the positional relationship between a semiconductor integrated circuit device, a cutting line, and a test pad.

  FIG. 1 shows a part of a semiconductor wafer, and a plurality of semiconductor integrated circuit devices C1 are dividedly arranged by cutting lines D1 to D3. After the pre-shipment inspection, the semiconductor integrated circuit device C1 is divided into individual semiconductor integrated circuit devices C1 by cutting along the cutting lines D1 to D3. For example, the inspection pad P1 is disposed on the cutting line D1, and the inspection pad P1 is connected to the semiconductor integrated circuit device C1 by the wiring A1.

  FIG. 2 shows a cross-sectional view of the XY portion when cut along the cutting line D1 of FIG. Here, the case where the silicon substrate on which the semiconductor integrated circuit device is formed is a P-type substrate is shown. The plurality of semiconductor integrated circuit devices C1 cut along the cutting line D1 are divided, and the inspection pad P1 in FIG. 1 is eliminated. However, the inspection pad P1 and the cutting waste K1 of the wiring A1 connecting the inspection pad P1 and the semiconductor integrated circuit device C1 adhere to the wall surface of the semiconductor integrated circuit device C1.

  The cut surface of the wiring A1 connecting the test pad P1 and the semiconductor integrated circuit device C1 by the cutting waste K1 such as the test pad P1, and the cut surface of the P-type substrate on which the semiconductor integrated circuit device C1 is formed. However, it is short-circuited.

  Usually, the P-type substrate is connected to the ground potential in the semiconductor integrated circuit device C1. However, when a potential other than the ground potential is supplied to the wiring A1, different potentials are short-circuited by the cutting waste K1, which may cause a malfunction of the circuit or an unnecessary current. Similarly, there may be a plurality of cut surfaces of the wiring A1, and the cut surfaces may be short-circuited.

  In other words, the wiring A1 connecting the inspection pad P1 and the semiconductor integrated circuit device C1 is short-circuited at different potentials by cutting dust generated when the semiconductor wafer is cut, and an unnecessary current of the semiconductor integrated circuit device C1 after the semiconductor wafer is cut. There was a problem of flowing.

  It is an object of the present invention to reduce the chip area by arranging inspection pads and wirings arranged on a cutting line on the cutting line and to generate a short circuit due to cutting waste generated when cutting a semiconductor wafer. Even so, it is an object of the present invention to provide a semiconductor integrated circuit device and a non-contact electronic device in which the divided semiconductor integrated circuit device does not malfunction or increase unnecessary current consumption.

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device that is divided and arranged on a semiconductor wafer by a plurality of cutting lines, and includes an inspection pad on the cutting line, the inspection pad being The control circuit is connected to an internal signal line of the semiconductor integrated circuit device through a control circuit provided in the semiconductor integrated circuit device, and the control circuit has the inspection pad before cutting the semiconductor wafer along the cutting line. And the signal line are short-circuited, and after the semiconductor wafer is cut along the cutting line, the function of opening the signal line and the cut end to which the inspection pad is connected is a MOS transistor, and the MOS transistor before and has a level shift circuit for changing a potential level of the signal for controlling the gate potential, and cut along the semiconductor wafer to the cutting line And it has a function of changing the state after disconnection.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, in the semiconductor integrated circuit device according to the present invention, it is possible to reduce the chip area by arranging the inspection pads and the wirings arranged on the cutting line on the cutting line, and at the time of cutting the semiconductor wafer. Even if a short circuit occurs due to cutting waste, an increase in current consumption of the divided semiconductor integrated circuit device can be prevented and normal operation can be performed.

  Hereinafter, a semiconductor integrated circuit device and a non-contact electronic device according to the present invention will be described with reference to the accompanying drawings.

  FIG. 3 shows a basic configuration of the first embodiment of the semiconductor integrated circuit device and the non-contact electronic device according to the present invention.

In FIG. 3, CA is a non-contact electronic device, C1 is a semiconductor integrated circuit device mounted on the non-contact electronic device, and L1 is an antenna coil mounted on the non-contact electronic device.
The semiconductor integrated circuit device C1 has a power supply circuit B1, an internal circuit B2, control circuits B3 to B6, and antenna terminals LA and LB for connecting the antenna L1.

  FIG. 4 shows a structure in which an antenna coil is formed on the semiconductor integrated circuit device shown in FIG. The antenna coil L1 is formed by a wiring layer formed on the semiconductor integrated circuit device C1, and is connected to the antenna terminals LA and LB.

  In FIG. 3, the antenna coil L1 that receives the electromagnetic wave from the reader / writer outputs a high-frequency AC signal to the antenna terminals LA and LB. The AC signal is partially modulated by an information signal (data). The power supply circuit B1 rectifies and smoothes the high-frequency signal input to the antenna terminal. The power supply circuit B1 may have a regulator function for controlling the output voltage of the power supply circuit B1 so as not to exceed a predetermined voltage level. The output voltage V1 of the power supply circuit B1 is supplied as an operation power supply voltage to the entire circuit B7 including the internal circuit B2 and the control circuits B3 to B6.

  The internal circuit B2 includes a transmission / reception unit B7, a signal processing unit B8, and a memory B9. The transmission / reception unit B7 demodulates the AC signal modulated by the information signal received by the antenna coil L1 provided in the non-contact electronic device, and supplies the obtained digital information signal to the signal processing unit B8. The digital signal generated by the signal processor B8 is received, and the AC signal received by the antenna coil L1 is modulated by the information signal. The reader / writer receives information from the signal processing unit B8 in response to the change due to the modulation. The memory B9 holds data in the process of signal processing executed by the signal processing unit B8, data owned by each non-contact electronic device CA, and the like.

  In FIG. 3, signal lines S1 to S4 connected to inspection pads P2 to P5 arranged on the cutting line of the semiconductor wafer are connected to the internal circuit B2 by the signal lines S5 to S8 via the control circuits B3 to B6. It is connected to the. The inspection pads P2 to P5 are used as terminals for inputting or outputting signals at the time of inspection before shipment. Since the inspection pads P2 to P5 disappear due to the semiconductor wafer cutting process, the inspection pads P2 to P5 are disposed on the cut semiconductor integrated circuit device C1. The cut ends T1 to T4 of the signal lines S1 to S4 are exposed on the cut surface E1. The control circuits B3 to B6 connect the signal lines S1 to S4 and the signal lines S5 to S8 before cutting the semiconductor wafer, particularly at the time of inspection before shipping, and after cutting the semiconductor wafer, connect the signal lines S1 to S4 to the silicon substrate. It has a function of fixing to the same potential as that of or a state of opening. Here, whether to apply the function of fixing the same potential as the silicon substrate or the function of opening the control circuit B3 to B6 can be selected by the function of the test pads P2 to P5.

  In FIG. 3, for example, after the semiconductor wafer is cut, the signal line S1 is shifted to an open state by the control circuit B3, and when the signal line S2 is fixed to the same potential as the silicon substrate by the control circuit B4, it is exposed to the cut surface E1. Even if the cut ends T1 and T2 are short-circuited by cutting waste and the signal line S1 has the same potential as the silicon substrate, the state of the signal line S5 connected to the internal circuit B2 does not change. There is no effect. Similarly, even if the cut ends T1 and T2 are short-circuited by the silicon substrate and the cutting waste, the state of the signal lines S5 and S6 connected to the internal circuit B3 does not change, and thus there is no influence on the internal circuit B1.

  As described above, by providing the control circuits B3 to B6 between the inspection pads P2 to P5 and the internal circuit B1, the mutual short circuit of the cut ends T1 to T4 due to the cutting waste generated when the semiconductor wafer is cut, or the cut end Even if a short circuit between T1 to T4 and the silicon substrate occurs, the internal circuit B2 is not affected, and after the semiconductor wafer is cut, the internal circuit B2 malfunctions and an unnecessary current increases at the cut end. There is no need to do it.

  FIG. 5 is a circuit diagram showing a specific embodiment of the semiconductor integrated circuit device and the non-contact electronic device of the present invention. In particular, an embodiment in which the inspection pad is mainly used as an output terminal of a logic signal is shown.

  The signal line S9 connected to the inspection pad P6 disposed on the cutting line of the semiconductor wafer is input to the internal circuit B11, and the signal line S9 is connected to the ground potential via the resistor R1. Here, since the silicon substrate forming the semiconductor integrated circuit device is a P-type substrate, the resistor R1 is connected to the ground potential.

  On the other hand, the signal line S10 connected to the inspection pad P7 disposed on the cutting line of the semiconductor wafer is connected to the internal circuit B11 by the signal line S11 via the control circuit B12. The control circuit B12 includes MOS transistors M1 to M4 and inverters G1 to G2, and when the signal line S9 is “L”, the MOS transistors M1 and M4 are “off”, so that the control circuit B12 is in an open state. When the signal line S9 is “H”, the MOS transistors M1 and M4 are “on”, so that the MOS transistors M1 and M4 operate as inverters, the signal line S10 is in the same state as the signal line S11, and the internal circuit B11. Is output to the inspection pad P7.

  As described above, when the test pad P7 is used as an output terminal of a logic signal, the signal line S10 is exposed to the cut surface E2 after cutting the semiconductor wafer by setting the signal line S10 to high impedance by the control circuit B11. Even if the cut ends T5 to T6 of S10 are short-circuited to the silicon substrate by the cutting waste, no unnecessary current flows between the signal lines S9 to S10 and the silicon substrate.

  Therefore, even when the semiconductor integrated circuit device has an antenna coil and rectifies and smoothes the voltage generated at both ends of the antenna coil to form an internal voltage necessary for the operation of the internal circuit, after cutting the semiconductor wafer, It is possible to prevent the communication range from being reduced due to unnecessary current consumption caused by cutting waste.

  FIG. 6 is a circuit diagram showing a specific embodiment of the semiconductor integrated circuit device and the non-contact electronic device of the present invention. In particular, an embodiment in which the inspection pad is mainly used as an output terminal of a logic signal is shown.

  The signal line S12 connected to the inspection pad P8 disposed on the cutting line of the semiconductor wafer is input to the internal circuit B13, and the signal line S12 is connected to the ground potential via the resistor R2. Here, since the silicon substrate forming the semiconductor integrated circuit device is a P-type substrate, the resistor R2 is connected to the ground potential.

  The signal line P13 connected to the inspection pad P9 arranged on the cutting line of the semiconductor wafer is connected to the internal circuit B13 by the signal line S14 via the control circuit B14. The control circuit B14 includes an inverter G3 and a NOR circuit G4. When the signal line S12 is “L”, the control circuit B14 outputs “L” to the signal line S13. Here, it goes without saying that "L" output to the signal line S13 is the same potential as the ground potential. When the signal line S12 is “H”, the NOR circuit G4 operates as an inverter, the signal line S13 is in the same state as the signal line S14, and the signal output from the internal circuit B13 is output to the inspection pad P9. Is done.

  As described above, when the test pad P9 is used as an output terminal of a logic signal, a signal having the same potential as that of the silicon substrate is output to the signal line S13 by the control circuit B14, thereby exposing the cut surface E3 after the semiconductor wafer is cut. Even if the cut ends T7 to T8 of the signal lines S12 to S13 are short-circuited to the silicon substrate by the cutting waste, unnecessary current does not flow between the signal lines S12 to S13 and the silicon substrate.

  Therefore, even when the semiconductor integrated circuit device has an antenna coil and rectifies and smoothes the voltage generated at both ends of the antenna coil to form an internal voltage necessary for the operation of the internal circuit, after cutting the semiconductor wafer, It is possible to prevent the communication range from being reduced due to unnecessary current consumption caused by cutting waste, and to reduce the number of transistors constituting the control circuit B14.

  FIG. 7 shows an example of outputting to a test pad for observing a data write voltage lower than the ground potential.

  The signal line S15 connected to the inspection pad P10 disposed on the cutting line of the semiconductor wafer is input to the internal circuit B15, and the signal line S15 is connected to the ground potential via the resistor R3. Here, since the silicon substrate forming the semiconductor integrated circuit device is a P-type substrate, the resistor R3 is connected to the ground potential.

  The signal line S19 connected to the inspection pad P11 disposed on the cutting line of the semiconductor wafer is connected to the internal circuit B15 by the signal line S17 via the control circuit B16. At this time, the signal line S17 is a signal line that outputs a data write voltage lower than the ground potential. The control circuit B16 includes a MOS transistor M5 that operates as a switch circuit and a level shift circuit B17. Since a voltage lower than the ground potential is output to the inspection pad P11, the MOS transistor M5 cannot be “off” even if the signal line S15 is “L”. Therefore, a level shift circuit B17 for controlling the gate potential of the MOS transistor M5 is provided, and the level shift circuit B17 is configured by MOS transistors M6 to M9 and an inverter G5.

  When the signal line S15 is “H”, the level shift circuit B17 outputs a signal having the same potential as the power supply voltage to the output signal S18. Accordingly, the MOS transistor M5 is turned on, and a signal having the same potential as that of the signal line S17 is output to the test pad P11. When the signal line S15 is “L”, the level shift circuit B17 outputs a signal having the same potential as the signal line S20 to the output signal S18. Therefore, the MOS transistor M5 is “off”, and the test pad P11 has a high impedance. As described above, the MOS transistor is controlled by the level shift circuit, so that the MOS transistor M5 can be controlled even when the signal line S17 is at a potential lower than the ground potential. A potential lower than the ground potential can be output to the pad.

  As described above, when the test pad P11 is used as a terminal for observing a data write voltage lower than the ground potential, the control circuit B16 outputs a signal having the same potential as that of the silicon substrate to the signal line S18. Even if the cut ends T9 to T10 of the signal lines S15 to S16 exposed on the cut surface E4 are short-circuited to the silicon substrate by the cutting waste after the cutting of, unnecessary current is generated between the signal lines S15 to S16 and the silicon substrate. Not flowing.

  It goes without saying that it is possible to output a potential higher than the power supply voltage by using the same means.

  FIG. 8 shows another embodiment in which the data write voltage lower than the ground potential is output to the test pad for observing.

  FIG. 8 is obtained by adding a MOS transistor M10 between the ground potential of the circuit shown in FIG. 7 and the signal line S16. The signal line S18 is input to the gate terminal of the MOS transistor M10. When the MOS transistor M5 is “off”, the MOS transistor M10 is “on”, and when the MOS transistor M5 is “on”, the MOS transistor M10 is “off”. “Yes.

  Thus, the control circuit B16 outputs a signal having the same potential as that of the silicon substrate to the signal line S18, so that the cut ends T9 to T10 of the signal lines S15 to S16 exposed on the cut surface E4 are cut after the semiconductor wafer is cut. Even if it is short-circuited with the silicon substrate due to dust, it is possible to prevent unnecessary current from flowing between the signal lines S15 to S16 and the silicon substrate, and to fix the cut end T10 of the signal line S16 to the ground potential. It becomes possible to do.

  Although the PMOS transistor M10 is used here to fix the signal line S16 to the ground potential, it goes without saying that a similar function can be realized by an NMOS transistor having a gate terminal connected to the drain terminal of the MOS transistor M7.

  The invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various design changes can be made without departing from the scope of the invention. Needless to say. For example, the antenna coil is not limited to the one formed by the wiring layer on the semiconductor integrated circuit device, and an antenna coil connected to the outside can also be used. The present invention can be widely used for semiconductor integrated circuit devices and contactless electronic devices.

FIG. 3 is a layout view showing a positional relationship between a semiconductor integrated circuit device, a cutting line, and a test pad. Sectional drawing after semiconductor wafer cutting. 1 is a basic configuration diagram showing an embodiment of a semiconductor integrated circuit device and a non-contact electronic device according to the present invention. FIG. 4 is a structural diagram in which the antenna coil of FIG. 3 is formed by a wiring layer on a semiconductor integrated circuit device. FIG. 4 is a circuit diagram showing a specific example when the test pad is used for outputting a logic signal in FIG. 3. FIG. 4 is a circuit diagram showing another specific example when the test pad is used for outputting a logic signal in FIG. 3. FIG. 4 is a circuit diagram showing a specific example when the test pad is used for outputting a potential lower than the ground potential in FIG. 3. FIG. 4 is a circuit diagram showing another specific example when the test pad in FIG. 3 is used for outputting a potential lower than the ground potential.

Explanation of symbols

A1 ... wiring,
B1 ... power supply circuit,
B2, B11, B13, B15... Internal circuit,
B3 to B6, B12, B14, B16... Control circuit,
B7 ... Entire circuit,
B8 ... Transmitter / receiver,
B9: Signal processing unit,
B10 ... Memory,
B17... Level shift circuit,
C1... Semiconductor integrated circuit device,
D1-D3 ... cutting line,
E1-E4 ... cut surface,
G1 to G3, G5... Inverter,
G4: NOR circuit,
K1 ... cutting waste,
M1 to M10 ... MOS transistors,
P1 to P11 ... inspection pads,
R1 to R3... Resistance
S1 to S18 ... signal lines,
T1 to T10 ... cutting end,
Z1-Z2 ... Silicon substrate

Claims (4)

A semiconductor integrated circuit device divided and arranged by a plurality of cutting lines provided on a semiconductor wafer,
An inspection pad is provided on the cutting line,
The inspection pad is connected to an internal signal line of the semiconductor integrated circuit device through a control circuit provided in the semiconductor integrated circuit device,
The control circuit includes:
Before cutting the semiconductor wafer along the cutting line, the inspection pad and the signal line are short-circuited, and after cutting the semiconductor wafer along the cutting line, the cutting end to which the inspection pad is connected, The function of opening the signal line is a MOS transistor,
A level shift circuit that changes the potential level of a signal that controls the gate potential of the MOS transistor,
A semiconductor integrated circuit device characterized by changing a state before and after cutting a semiconductor wafer along a cutting line.   The semiconductor integrated circuit device according to claim 1,
  The control circuit short-circuits the inspection pad and the signal line before cutting the semiconductor wafer along the cutting line, and the semiconductor integrated circuit device after cutting the semiconductor wafer along the cutting line. A semiconductor integrated circuit device which outputs a potential equivalent to a potential supplied to a silicon substrate to be formed.   A non-contact electronic device mounting a coil constituting an antenna and the semiconductor integrated circuit device according to claim 1,
  The contactless electronic device, wherein the coil is connected to an antenna connection terminal of the semiconductor integrated circuit.   The contactless electronic device according to claim 3,
  A non-contact electronic device, wherein a coil constituting the antenna is formed of a wiring layer on the semiconductor integrated circuit device according to claim 1.

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