JP4211014B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device.Made ofIn particular, a method of replacing an arbitrary portion of a polycrystalline silicon wiring layer with a metal having a low resistivity such as aluminum after completion of a process involving a high-temperature heat treatment process, and a semiconductor having a characteristic structure as a result apparatusMade ofIt relates to the manufacturing method.
[0002]
[Prior art]
  In recent years, design rules (lines / spaces) have become stricter with higher integration and larger capacity of semiconductor devices, and accordingly, wiring layers of semiconductor devices such as DRAM (Dynamic Random Access Memory). And the diameter of the via hole for forming the plug connecting the upper and lower wiring layers is becoming smaller.
[0003]
  As described above, there is a problem that when the width of the wiring layer is reduced, the resistance is increased, resulting in a delay in operation speed, and the aspect ratio (depth / diameter) is extremely increased as the via hole diameter is reduced. Therefore, even if a CVD method having better step coverage than a sputtering method is used, Al cannot be completely embedded in such a via hole, and a void is formed inside the via hole. As a result of the reduced cross-sectional area of the portion, there is a problem that the resistance is increased or the wire is disconnected in some cases.
[0004]
  In order to solve such a problem of fine via holes, a polysilicon-aluminum substrate (PAS) has been proposed (International Electron Devices Meeting 96, p. 946-948 if necessary). See), Figure3Will be described with reference to FIG.
[0005]
  Figure3(A) Reference
  First, after a SiO 2 film 202 having a thickness of 2.4 μm is deposited on the silicon substrate 201 by a CVD method, a via hole having a bottom diameter of 0.25 μm, that is, a contact hole 203 is formed by RIE (reactive ion etching). Then, a polycrystalline Si layer 204 that is much better than Al is deposited by low pressure chemical vapor deposition (LPCVD), and the inside of the contact hole 203 is buried.
[0006]
  Figure3(B) Reference
  Next, after using a CMP method (chemical mechanical polishing method) to polish until the surface of the SiO2 film 202 is exposed, a polycrystalline Si plug 205 is formed by a polycrystalline Si layer embedded in the contact hole 203. An Al layer 206 having a thickness of 0.5 μm is deposited by sputtering.
[0007]
  Figure3(C) Reference
  Next, by performing annealing at 500 ° C. in a nitrogen atmosphere, the polycrystalline Si plug 205 is replaced with Al by mutual diffusion of Si and Al, and then the surface of the SiO 2 film 202 is exposed, although not shown. The contact electrode composed of the Al-substitution plug 207 is formed by polishing up to 1.
  In this case, the Si content in the Al replacement plug 207 is about 0.4% even in the bottom portion, and is almost replaced with Al.
[0008]
  In the annealing step, a Ti layer having a thickness of 0.2 μm is deposited on the Al layer 206, so that the Ti layer functions as a Si absorption layer. It is thin, the annealing temperature can be lowered, and the annealing time can be shortened.
[0009]
  By using such a polysilicon-aluminum substitution method (PAS method), a via hole having a maximum aspect ratio of about 10 and a diameter of 0.1 μm or less can be filled with low-resistance Al, and future MPU (Microprocessor) Unit) and DRAM plugs (contact electrodes).
[0010]
  However, when such a polysilicon-aluminum replacement method is applied to an actual LSI manufacturing process, there is a relationship with other processes, and various problems arise due to the simple introduction of the above-described single process. Is expected.
[0011]
  For example, when applied to a source / drain contact electrode of an IGFET (Insulated Gate Field Effect Transistor), since the source / drain region is made of the same Si as the polycrystalline Si layer, the polycrystalline Si plug is made of Al. After the replacement, the source / drain regions are also replaced with Al.
[0012]
  Then, if Al enters the pn junction formed in the silicon substrate, the pn junction is destroyed due to an Al spike extending between the pn junctions. This is a fatal damage to the LSI. Become.
[0013]
  Therefore, when applying such a polysilicon-aluminum substitution method to an actual device, the present inventor has provided a stopper film or a barrier film serving as an Al stopper between the source / drain regions and the polycrystalline Si plug. I tried to install it.4Will be described with reference to FIG.
[0014]
  In general, the provision of a stopper film or a barrier film to prevent diffusion itself is a conventional method. However, in the case of the polysilicon-aluminum substitution method, it does not react with Al or reacts even at a high temperature. It was necessary to select a difficult material, and it was determined that TiN, WN, or SiC was appropriate as such a material.
[0015]
  However, since TiN, WN, or SiC has poor reactivity with Si and it is difficult to make electrical contact, there is a problem that the contact resistance with the source / drain region becomes very high. In addition, a film that easily reacts with Si, that is, a contact metal is formed thinly at the interface between the stopper film or the barrier film and the source / drain region.
[0016]
  Figure4(A) Reference
  First, an element isolation oxide film 212 is formed in a predetermined region of the p-type silicon substrate 211 by selective oxidation, and then the exposed surface of the p-type silicon substrate 211 surrounded by the element isolation oxide film 212 is thermally oxidized to form a gate oxide film 213. Next, after depositing a non-doped polycrystalline Si layer, impurities such as P (phosphorus) are ion-implanted, and then the entire surface is made of SiO which becomes the protective film 215 by CVD.₂ Film or Si_Three N_Four After the film is deposited, the gate electrode 214 is formed by etching into a predetermined pattern.
[0017]
  Next, impurities such as As or P are ion-implanted using the gate electrode 214 and the protective film 215 as a mask to form n-type source / drain regions 217, and then the entire surface is made of SiO by a CVD method.₂ A sidewall 216 is formed by depositing a film and performing anisotropic etching.
[0018]
  Next, Si is used as a stopper film during etching on the entire surface by CVD._Three N_Four After the film 218 is deposited, SiO 3 having different etching characteristics from the Si 3 N 4 film 218 is formed on the entire surface by CVD.₂ A film is deposited to form an interlayer insulating film 219, and then Si_Three N_Four After forming an opening in the interlayer insulating film 219 using the film 218 as an etching stopper layer, the Si exposed in the opening_Three N_Four The film 218 is selectively removed.
[0019]
  Next, a 20 nm thick Ti film 220 as a contact metal and a 10-100 nm thick TiN film 221 as a barrier metal are sequentially deposited by sputtering or CVD.
[0020]
  Next, after depositing a polycrystalline Si film using the LPCVD method, the polycrystalline Si plug 222 is formed by polishing by the CMP method until the TiN film 221 is exposed, and then a thickness of 2 μm is formed using the sputtering method. An Al layer 223 and a Ti layer 224 having a thickness of 200 nm are deposited.
[0021]
  Figure4(B) Reference
  Next, the polycrystalline Si plug 222 is replaced with Al by performing a heat treatment at a temperature of 400 to 660 ° C. for about 1 hour in a nitrogen atmosphere, and then the surface of the interlayer insulating film 219 is exposed again using the CMP method. The Al-substitution plug 225 is formed by polishing until.
[0022]
  It was found that the polysilicon-aluminum replacement method can be applied to an actual LSI manufacturing process by adopting such a structure, that is, a stopper film made of a contact metal and a barrier metal.
[0023]
  As the contact metal in this case, W, Co, Ni, Ta, or a silicide thereof can be used in addition to Ti, and silicide is already formed on the surface of the n-type source / drain region 217. In the case where the contact metal layer is formed, or when a base functioning as a contact metal is formed, the contact metal deposition step can be omitted.
[0024]
[Problems to be solved by the invention]
  However, in the application example described above, there is no problem when the annealing temperature is relatively low, such as 400 ° C. to 450 ° C., but when the heat treatment is performed at a higher temperature, for example, 450 ° C. to 850 ° C. Problems arise.
[0025]
  That is, when heat treatment for Al substitution is performed at such a high temperature, Ti of the contact metal itself reacts with Si in the source / drain region, and enters the pn junction to destroy the pn junction. This is because a case occurs.
[0026]
  Therefore, although there is no problem if such a contact plug formation process is the final process, a polycrystalline Si plug is provided through a stopper layer in the middle of the manufacturing process, and after a high temperature treatment process in the subsequent manufacturing process, If the silicon-aluminum substitution method is performed, an Al substitution plug can be formed, but the problem that Ti diffuses in the high temperature treatment process and destroys the pn junction, and the eutectic alloy of Ti and Si is caused by the diffusion of Ti. There is also a problem that impurities are abnormally segregated in this eutectic region and contact failure occurs, so that the application process is limited.
[0027]
  In addition, since the conventional polysilicon-aluminum replacement method only assumes replacement of the polycrystalline Si plug, the lower wiring layer constituting the conductive path of the LSI is higher than Al (specific resistance: 2.8 μΩ · cm). Doped polycrystalline Si with high resistance (specific resistance: 300 to 800 μΩ · cm), refractory metal (specific resistance of W: 6 μΩ · cm), or refractory metal silicide (specific resistance of W silicide: 70 μΩ · cm, Ti Since the high-temperature resistant material such as the specific resistance of silicide (15 μΩ · cm) remains, the merit of the polysilicon-aluminum substitution method cannot be fully utilized.
[0028]
  For example, in the case of a DRAM bit line, a storage electrode and a capacitor insulating film constituting a capacitor of a memory cell are formed above the bit line. In the current technology, this capacitor insulating film is formed at 600 ° C. Since it is very difficult to obtain high reliability by forming at a low temperature, high temperature heat treatment at 700 ° C. to 850 ° C. is required.
[0029]
  Since this process is after the formation of the bit line, Al having a melting point of 660 ° C. cannot be used for the bit line. However, if Al can be used for the bit line, the resistance of the bit line is simply lowered. In addition to being able to do this, it is allowed to make the bit line thin, so that the parasitic capacitance between adjacent bit lines can be reduced, and a high-speed and low-power consumption memory LSI can be manufactured. It becomes possible.
[0030]
  Further, since the resistance and parasitic capacitance of the bit line can be reduced, the number of cells connected to one bit line can be increased, so that the degree of integration of the memory can be increased. There is a long-awaited desire for Al in bit lines.
[0031]
  In the case of a normal self-aligned IGFET, ion implantation is performed using a gate electrode as a mask, and annealing for activation is performed to form a source / drain region. This annealing temperature is 800 ° C. Since it is about ˜1100 ° C., Al is not used as the gate electrode.
[0032]
  However, if Al can be used as the gate electrode, as in the case of the bit line, it can greatly contribute to speeding up and lowering power consumption of the LSI, and a high added value LSI can be manufactured. In addition, if Al can be used as the gate electrode of the memory, that is, the word line, the number of cells that can be connected to one word line can be increased, and the degree of integration of the memory can be increased. Become.
[0033]
  In the case of a self-aligned bipolar transistor, an external base region and an emitter region are formed by solid-phase diffusion of impurities from a base extraction electrode and an emitter electrode made of a doped polycrystalline Si layer. Therefore, Al cannot be used as a diffusion source / electrode because the heat treatment temperature for the heat treatment is 800 ° C. to 1100 ° C.
[0034]
  However, if the base extraction electrode and the emitter electrode can be replaced with Al, it is possible to significantly increase the speed and reduce the power consumption, which is very desirable.
[0035]
  Therefore, in order to reduce the resistance of such a wiring layer or electrode, even if the application of the polysilicon-aluminum replacement method is considered, the above-described bit line, gate electrode, or base lead electrode is not provided on the surface of the LSI. The bit line, the gate electrode, or the base lead electrode is formed of a polycrystalline Si layer and is formed on Al by the polysilicon-aluminum substitution method. Even if the replacement is attempted, the simple application of the polysilicon-aluminum replacement method causes a problem that the thick Al layer necessary for the replacement cannot be connected to the polycrystalline Si layer to be replaced.
[0036]
  Moreover, since the state-of-the-art LSI has a structure in which the source / drain electrodes are formed with respect to the word lines and the capacitor contacts are formed with self-alignment with respect to the bit lines, the upper portions of the word lines and bit lines are formed. It is indispensable to be covered with an insulating film, and it is not allowed to remove the insulating film in the subsequent process.
[0037]
  Therefore, the conventional polysilicon-aluminum replacement method in which Al replacement is performed by exposing the upper portion of the word line or the bit line and contacting with a thick replacement Al layer can be applied to the dense portion of the cell. Therefore, some ingenuity is necessary.
[0038]
  For example, when replacing a bit line with Al,
a.A structure in which the bit line itself is easily replaced with Al, and a structure of an introduction portion of Al replacement,
b.After replacing the bit line with Al, a stopper structure for preventing Al from entering further lower polycrystalline Si plugs and source / drain regions,
c.Stopper structure when the upper plug in contact with the lower plug that is not desired to be replaced with Al is replaced with Al,
It is necessary to devise such measures, and if these measures are taken separately, the work constant increases and the cost increases, so some contrivance to prevent an increase in the manufacturing process is also necessary.
[0039]
  In particular, in DRAM, competition among manufacturers is fierce, and cost reduction is very important. Even if a polysilicon-aluminum replacement method can be introduced to achieve high functionality, it is most important to reduce cost. This is a problem, and it is indispensable to prevent the cost of the Al replacement process itself and the accompanying stopper formation process.
[0040]
  In addition, when the polysilicon-aluminum substitution method is applied to the gate electrode, the gate insulating film is a very delicate thin insulating film, and the reliability of the gate electrode is easily lost due to the diffusion of a small metal. In the case of replacing Al, a device that does not impair the reliability of the gate insulating film is necessary.
[0041]
  In addition, when the polysilicon-aluminum substitution method is applied to the base extraction electrode and the emitter extraction electrode of the self-aligned bipolar transistor, these extraction electrodes also serve as impurity diffusion sources. It is necessary to devise an electrode structure so that it can play a role.
[0042]
  Furthermore, in order to increase the speed and power consumption of LSI, it is necessary to reduce the parasitic capacitance between wiring layers. However, in conventional LSI, the dielectric constant of the insulating film itself constituting the interlayer insulating film is lowered. Therefore, parasitic capacitance countermeasures were not sufficient.
[0043]
  Therefore, the present invention reduces the resistance of the plug and the wiring layer by applying the polysilicon-aluminum replacement method so that the manufacturing process does not increase so much and the device characteristics are not adversely affected, or An object is to reduce parasitic capacitance between wiring layers.
[0044]
[Means for Solving the Problems]
  Here, means for solving the problems in the present invention will be described with reference to FIG.
  (1) The present invention relates to a semiconductor device.In this manufacturing method, the gate electrode is formed from the upper layer side with a multilayer structure comprising a silicon layer, a conductor layer (38) serving as a stopper for aluminum as a replacement metal, and a silicon layer (36) doped with impurities. A step of forming a silicon plug in contact with the upper silicon layer, a step of providing an aluminum layer in contact with the silicon plug, and heat treatment in a nitrogen atmosphere so that the silicon plug is made of aluminum in the aluminum layer. And a metal replacement plug (39), and replacing only the upper silicon layer of the gate electrode with aluminum.
[0045]
  In this way, gate powerThe pole, Silicon layer / stopper(38)/ Doped silicon layer(36)By using the multi-layer structure, only the silicon layer can be replaced with metal, so that the gate insulating film can be obtained without changing Vth.(13)Without reducing the reliability of the gateThe poleThe specific resistance can be reduced.
DETAILED DESCRIPTION OF THE INVENTION
[0046]
  Here, first, with reference to FIG. 1, the process of the reference example 1 used as the premise of this invention is demonstrated.
  Figure1(A) Reference
  As before,3As described above, first, the element isolation oxide film 12 is formed by selective oxidation in a predetermined region of the p-type silicon substrate 11, and then the exposed surface of the p-type silicon substrate 11 surrounded by the element isolation oxide film 12 is thermally oxidized. Then, a gate oxide film 13 is formed, and then a non-doped polycrystalline Si layer is deposited. Then, P is ion-implanted to form a doped polycrystalline Si layer. SiO₂ After the film is deposited, the gate electrode 14 is formed by etching into a predetermined pattern.
[0047]
  Next, As is ion-implanted using the gate electrode 14 and the protective film 15 as a mask to form n-type source / drain regions 17, and then the entire surface is made of SiO by a CVD method.₂ A sidewall 16 is formed by depositing a film and performing anisotropic etching.
[0048]
  Next, a Si film having a thickness of 10 to 100 nm that serves as a stopper film during etching is formed on the entire surface by CVD._Three N_Four After the film 18 is deposited, Si is deposited on the entire surface by the CVD method._Three N_Four A SiO2 film having a thickness of 100 to 500 nm, which is different from the film 18 in etching characteristics, is deposited to form an interlayer insulating film 19, and then Si_Three N_Four After forming an opening in the interlayer insulating film 19 using the film 18 as an etching stopper layer, the Si exposed in the opening_Three N_Four By selectively removing the film 18, via holes reaching the n-type source / drain regions 17 are formed.
[0049]
  Next, after depositing a polycrystalline Si layer doped with impurities by LPCVD, polishing is performed by CMP until the first interlayer insulating film 19 is exposed, thereby forming a polycrystalline Si plug 20 having conductivity.
[0050]
  Next, a Ti film 21 having a thickness of 10 to 100 nm, for example, 20 nm, serving as a contact metal, and a TiN film 22 having a thickness of 10 to 200 nm, for example, 50 nm, serving as a barrier metal, are sequentially deposited by sputtering. Etching is performed so as to remain on the crystalline Si plug 20 to form a stopper pad for Al.
[0051]
  Next, again, a CVD method is used to deposit a SiO2 film having a thickness of 0.05 to 5.0 .mu.m, for example, 0.5 .mu.m on the entire surface to form the second interlayer insulating film 23, and then a via hole reaching the stopper pad is formed. Then, after depositing a non-doped polycrystalline Si layer again by LPCVD method, the polycrystalline Si plug 24 is formed by polishing by CMP method until the second interlayer insulating film 23 is exposed.
[0052]
  Next, an Al layer 25 having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer 26 having a thickness of 50 to 2000 nm, for example, 200 nm are deposited by sputtering.
[0053]
  Figure1(B) Reference
  Next, after the polycrystalline Si plug 24 is replaced with Al by performing heat treatment at 400 to 660 ° C., for example, 500 ° C. in a nitrogen atmosphere for 1.0 to 48 hours, for example, 6 hours, the CMP method is performed again. The Al replacement plug 27 is formed by polishing until the surface of the second interlayer insulating film 23 is exposed.
[0054]
  In this way, the present inventionReference example 1Since the stopper pad is provided between the polycrystalline Si plug 20 provided in the lower part and the polycrystalline Si plug 24 provided in the upper part, when the upper polycrystalline Si plug 24 is replaced with Al, Al It does not diffuse into the lower polycrystalline Si plug 20, and therefore, the pn junction constituting the n-type source / drain region 17 is not destroyed.
[0055]
  Further, even if a high temperature process of 450 ° C. or higher is performed in the heat treatment process accompanying the polysilicon-aluminum replacement process or other manufacturing processes, diffusion of Ti as a contact metal constituting the stopper pad occurs. The presence of the lower polycrystalline Si plug 20 increases the distance from the n-type source / drain region 17, so that no junction breakdown occurs.
[0056]
  For the same reason, Ti and Si in the n-type source / drain region 17 do not form a eutectic alloy, and abnormal segregation of impurities accompanying the eutectic alloy does not occur, resulting in contact failure. Thus, the specific resistance of the minute via hole can be reduced, and the reliability of the element can be improved.
[0057]
  Given the above,next,The steps of the first embodiment of the present invention will be described with reference to FIG.
  Figure2(B)2It is sectional drawing along the gate extraction wiring layer of (a).
  Figure2See (a) and (b)
  First, an element isolation oxide film 12 is formed in a predetermined region of the p-type silicon substrate 11 by selective oxidation, and then an exposed surface of the p-type silicon substrate 11 surrounded by the element isolation oxide film 12 is thermally oxidized to form a gate oxide film 13. Next, after depositing a non-doped polycrystalline Si layer having a thickness of 10 to 300 nm, for example, 50 nm, P is ion-implanted to form a doped polycrystalline Si layer 36.
  Note that a doped polycrystalline Si film may be formed from the beginning.
[0058]
  Next, a TiN film 37 having a thickness of 10 to 100 nm, for example, 20 nm, which becomes a contact metal, and a TiN film 38 having a thickness of 10 to 200 nm, for example, 50 nm, which becomes a barrier metal, are sequentially deposited by sputtering, and then LPCVD again. Is used to deposit a non-doped polycrystalline Si layer having a thickness of 10 to 1000 nm, for example, 150 nm.₂ After the film is deposited to 100 nm, the gate electrode and the gate lead-out wiring layer are formed by etching into a predetermined pattern.
[0059]
  Next, As is ion-implanted using the gate electrode and the protective film 15 as a mask to form n-type source / drain regions 17, and then the entire surface is made of SiO.₂ A sidewall 16 is formed by depositing a film and performing anisotropic etching.
[0060]
  Next, a Si film having a thickness of 10 to 100 nm that serves as a stopper film during etching is formed on the entire surface by CVD._Three N_Four After the film 18 is deposited, Si is deposited on the entire surface by the CVD method._Three N_Four A SiO2 film having a thickness of 100 to 500 nm, which is different from the film 18 in etching characteristics, is deposited to form an interlayer insulating film 19, and then Si_Three N_Four After forming an opening in the interlayer insulating film 19 using the film 18 as an etching stopper layer, the Si exposed in the opening_Three N_Four By selectively removing the film 18, via holes reaching the n-type source / drain regions 17 are formed.
[0061]
  Next, after depositing a polycrystalline Si layer doped with impurities by LPCVD, polishing is performed by CMP until the first interlayer insulating film 19 is exposed, thereby forming a polycrystalline Si plug 20 having conductivity.
[0062]
  Then, again, a CVD method is used to form a SiO.sub.2 layer having a thickness of 0.05 to 5.0 .mu.m, for example, 0.5 .mu.m.₂ After the film is deposited to form the second interlayer insulating film 23, a via hole reaching the gate lead-out wiring layer is provided, and then a non-doped polycrystalline Si layer is deposited again by LPCVD, and then the second interlayer insulating film is deposited. A polycrystalline Si plug is formed by polishing by CMP until the film 23 is exposed.
[0063]
  Next, after depositing an Al layer (not shown) having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer (not shown) having a thickness of 50 to 2000 nm, for example, 200 nm, by sputtering, In a nitrogen atmosphere, heat treatment is performed at 400 to 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours. After replacing the doped polycrystalline Si layer with Al, the Al replacement plug 39, the Al replacement wiring layer 40, and the Al replacement gate electrode 41 are again polished by CMP until the surface of the second interlayer insulating film 23 is exposed. Form.
[0064]
  In this way, the first of the present invention1In this embodiment, since the gate electrode and the gate lead-out wiring layer that could not use Al due to the high-temperature heat treatment accompanying the self-alignment process can be replaced with low specific resistance Al, the insulated gate type The operating speed of the semiconductor device can be increased.
[0065]
  In this case, the gate electrode has a multilayer structure of non-doped polycrystalline Si layer / stopper / doped polycrystalline Si layer 36, and Al diffusion is blocked by the stopper, so Al substitution is non-doped polycrystalline. Since only the Si layer and the doped polycrystalline Si layer 36 are left as they are, Vth does not fluctuate, and the gate oxide film 13 and the channel region 42 are not damaged, so that reliability is not impaired. The resistance of the gate electrode and the gate lead-out wiring layer can be reduced.
[0066]
  As described above, the present inventionThe fruitAlthough the embodiments have been described, the present invention can be modified in various ways, for example, a replacement Al layer(25)Ti layer provided on top(26)Is not always necessary.
[0067]
  Also, aboveThe fruitIn the present embodiment, the source / drain region having a single structure is used for the sake of simplicity of explanation, but an LDD (Lightly Doped Drain) structure may be adopted, and in that case, the gate electrode After forming the LDD region by ion implantation using the protective film as a mask, the source / drain regions may be formed by ion implantation using the sidewall as a mask.
[0068]
  The barrier metal is not limited to TiN, and any conductive film that can prevent Al diffusion can be used. For example, TaN, WN, SiC, or the like can be used.
[0069]
  In addition, the present inventionThe fruitIn the description of the embodiment, the region to be replaced is made of polycrystalline silicon, but is not limited to polycrystalline silicon, and may be microcrystalline silicon or amorphous silicon. Silicon may be used.
[0070]
  In addition, the present inventionThe fruitIn the description of the embodiment, a conductor film other than polycrystalline silicon is deposited by a sputtering method. However, the present invention is not limited to the sputtering method, and a CVD method or a vapor deposition method may be used.
[0071]
  In addition, the present inventionThe fruitIn the description of the embodiment, n-channel type IGFEAt TAs described, p-channel IGFETIt goes without saying that also applies.
[0072]
【The invention's effect】
  According to the present invention, since the high-temperature treatment step is involved in the subsequent steps, the wiring layer and the electrode where the Al cannot be used are replaced with Al by using a polysilicon-aluminum substitution method after the high-temperature treatment step is finished. Since the resistance is reduced, the operating speed of various semiconductor devices can be greatly increased, and it contributes to the reduction of power consumption.
[Brief description of the drawings]
[Figure 1]It is explanatory drawing of the process of the reference example 1 used as the premise of this invention.
FIG. 2 is an explanatory diagram of the first embodiment of the present invention.
[Fig. 3]It is explanatory drawing of the conventional PAS process.
[Fig. 4]It is explanatory drawing of the example of application of the conventional PAS technique.
[Explanation of symbols]
  11 p-type silicon substrate
  12 Device isolation oxide film
  13 Gate oxide film
  14 Gate electrode
  15 Protective film
  16 sidewall
  17 n-type source / drain regions
  18 Si_Three N_Four film
  19 First interlayer insulating film
  20 Polycrystalline Si plug
  21 Ti film
  22 TiN film
  23 Second interlayer insulating film
  24 Polycrystalline Si plug
  25 Al layer
  26 Ti layer
  27 Al replacement plug
  36 doped polycrystalline Si layer
  37 Ti film
  38 TiN film
  39 Al replacement plug
  40 Al replacement wiring layer
  41 Al substitution gate electrode
  42 channel region
  201 silicon substrate
  202 SiO₂ film
  203 Contact hole
  204 Polycrystalline Si layer
  205 Polycrystalline Si plug
  206 Al layer
  207 Al replacement plug
  211 p-type silicon substrate
  212 Device isolation oxide film
  213 Gate oxide film
  214 Gate electrode
  215 Protective film
  216 sidewall
  217 n-type source / drain regions
  218 Si_Three N_Four film
  219 Interlayer insulation film
  220 Ti film
  221 TiN film
  222 Polycrystalline Si plug
  223 Al layer
  224 Ti layer
  225 Al replacement plug

Claims (1)

A step of forming a gate electrode with a multilayer structure comprising a silicon layer from the upper layer side, a conductor layer serving as a stopper for aluminum as a replacement metal, and a silicon layer doped with impurities, and silicon in contact with the upper silicon layer A step of forming a plug, a step of providing an aluminum layer in contact with the silicon plug, and a heat treatment in a nitrogen atmosphere to replace the silicon plug with aluminum in the aluminum layer to form a metal replacement plug. A method of manufacturing a semiconductor device, comprising: replacing only the upper silicon layer of the gate electrode with aluminum.

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