JP4211035B2 - Semiconductor device having temperature control function - Google Patents

Description

  The present invention relates to a semiconductor device having a package in which a Peltier element is incorporated, has a temperature control function, and is suitable for a low temperature test.

  In general, in a semiconductor device, a low-temperature test is performed in advance in order to guarantee its low-temperature operation. At that time, cooling with a refrigerant such as liquid nitrogen, or a refrigerant and a compressor Is used for cooling.

In that case, it is necessary to take measures to prevent dew condensation on the test apparatus, and it takes 1-2 hours as a time for cooling the entire inside of the test chamber and a time for returning to normal temperature after the test.

  In order to cool the semiconductor device, in addition to the means using the refrigerant or the like, heat generation due to circuit operation is suppressed using a Peltier element (for example, Patent Document 1, Patent Document 2, and Patent Document 3). , See Patent Document 4).

  The means disclosed in Patent Documents 1 to 4 employ a method of cooling by joining a Peltier element or a Peltier module to a semiconductor device.

  In order to perform cooling with high efficiency, a Peltier element is also formed in an IC chip by using a manufacturing process technology of a semiconductor device. For example, Patent Document 5 discloses an IC chip periphery outside a semiconductor circuit region. Patent Document 6 describes that the upper surface of a semiconductor circuit region is directly cooled by a Peltier element, and Patent Document 7 describes that a Peltier element is scattered in an IC chip. It is described that the elements constituting the semiconductor circuit are cooled.

  As described above, in the mounting structure of the semiconductor device using the Peltier element as a temperature application means such as cooling, the structure including the Peltier element is sealed, the heat sink that is in contact with one surface of the Peltier element, the radiator, the heat A structure in which heat radiating means such as a pipe is attached to an upper surface or a side surface of a sealing resin of a semiconductor device is known.

Incidentally, the invention disclosed in Patent Document 5 relates to a structure in which the entire semiconductor device including the Peltier element is integrally sealed, and the invention disclosed in Patent Document 7 includes a heat sink and a fan in the package. It relates to a structure in which heat dissipating means is installed.
JP 2001-230354 A JP-A-4-212442 Japanese Patent Laid-Open No. 4-142071 JP-A-5-243437 JP-A-5-152614 JP-A-7-221351 Japanese Patent Laid-Open No. 11-135692 Published by Yoshio Inuishi et al., “Semiconductor Properties I”, Asakura Shoten, page 223

  In the conventional technologies listed in the background section, the mounting structure or mounting method of a semiconductor device incorporating a Peltier element is addressed with a focus on cooling the semiconductor device that is operating with the Peltier element. Therefore, it is difficult to say that it is suitable for testing a semiconductor device, for example, using a test handler.

  In the present invention, it is intended to provide a semiconductor device having a package in which a good result can be obtained when a semiconductor device having a temperature control function in which a Peltier element is incorporated is subjected to a temperature test by a test handler.

  In general, in order to perform a temperature test of a semiconductor device incorporating a Peltier element, it is necessary to keep the temperature of the IC chip constant, and it is essential to efficiently dissipate the heat generated by the Peltier element.

  In a test handler used for testing a semiconductor device, the upper surface of the semiconductor device is pressed with a match plate (product name: Advantest) to contact the terminal of the semiconductor device to apply a signal to the socket board. Are in conductive contact.

  The match plate is usually made of an aluminum alloy, and its area is 50 to 100 times that of a semiconductor device. If the match plate can directly contact the heat dissipation surface of the Peltier element, it can act as a huge heat sink. Therefore, the heat generated by the Peltier element can be efficiently dissipated.

  However, in the semiconductor device mounting structure or mounting method as seen in the prior art, there are irregularities on the surface, and it is difficult to bring the match plate into contact with the heat dissipation surface of the Peltier element.

  Therefore, in the semiconductor device according to the present invention, since the upper surface of the sealing resin of the package and the Peltier element heat dissipation surface are in the same flat surface in the mounted state, the pusher of the match plate is placed on the Peltier element heat dissipation surface. (Product name of parts manufactured by Advantest) can be directly contacted.

  Normally, in a semiconductor device that performs cooling using the Peltier effect, it is essential to attach a radiator, so for example, it is not possible to apply pressure to the semiconductor device with fins mounted thereon, and therefore, This type of semiconductor device could not be tested using a test handler.

  In the semiconductor device having the temperature control function according to the present invention, even if a load is applied to the semiconductor device by the match plate of the test handler, most of the load is supported by the surface of the sealing resin, and the heat dissipation surface of the Peltier element Therefore, an excessive load is not applied to the IC, and therefore, the IC pressing mechanism (pusher) of the test handler and the Peltier element heat radiation surface can be in good contact with each other. This is equivalent to mounting a large area radiator on the heat dissipation surface of the Peltier element, so that the heat in the Peltier element can be dissipated well, and a semiconductor device having a Peltier element can be used as a test handler. This makes it possible to perform testing at the same time and simultaneously measure a large number of semiconductor devices.

  In addition, since it is possible to test a semiconductor device having a Peltier element with a test handler, a fan is attached to the test chamber of the test handler so that the air is blown into the chamber while maintaining the room temperature state, and flows to the Peltier element. It is possible to realize a temperature change from a high temperature to a low temperature simply by reversing the direction of the current. Therefore, when performing a temperature test of a semiconductor device with a test handler, the ambient temperature in the test chamber is changed, and the semiconductor device There is no need to provide a heater for applying a temperature to the chamber or use a refrigerant, and no airtightness maintenance mechanism or dew condensation prevention mechanism in the test chamber is required.

  Furthermore, if the semiconductor device having the temperature control function according to the present invention is configured to share the power supply of the semiconductor device and the power supply of the Peltier element at the time of mounting, a rapid increase in chip temperature during operation is suppressed, If each is an independent power supply, more stable cooling is possible, and it becomes possible to cool and heat the IC chip with a certain temperature difference by connecting the signal from the environmental temperature sensor device to the power inversion circuit. Since the environmental temperature and the chip temperature are associated with each other, a stable operation can be performed.

  In a semiconductor device incorporating a Peltier element for temperature control and its mounting method, the heat sinking surface of the Peltier element and the upper surface of the package are aligned so that the handler match plate can be used as a radiator. In addition, by providing an inverting circuit in the Peltier device power supply to control the direction of the current, the temperature test can be performed without using a refrigerant or a compressor.

  FIG. 1 is a cutaway side view illustrating a principal part of a semiconductor device having a temperature control function according to the present invention. In the figure, 1 is a silicon wafer chip, 2 is a pad, 3 is an insulating film, 4 is an insulating film, 5 Is a heat absorption side metal film, 6 is an insulation film, 7 is a Peltier element layer, 8 is an insulation film, 9 is a heat dissipation side metal film, 10, 10n, 10p are Peltier element electrode lead wires, 11 is an insulation film, 12 is a Peltier element Power supply pads 13 are device signal pads.

  FIG. 2 is a main part cutting slope view illustrating a semiconductor device having a temperature control function of the present invention. The same symbols as those used in FIG. 1 represent the same parts or have the same meaning.

  FIG. 2 is a view of the semiconductor device shown in FIG. 1 as viewed obliquely from the upper left, and the left and right sides of FIG. In the figure, 14 is a power inverting circuit, 15 is a mounting substrate, 16 is a pad on the mounting substrate side, 17 is a bonding wire, and 50 is a semiconductor device having a temperature control function.

  In FIG. 1 and FIG. 2, necessary devices such as transistors and diodes are formed on a silicon wafer chip 1, and the surface thereof is covered with an insulating film 3 except for pads 2 for applying power and signals, and The surface is flattened, and a Peltier structure represented as a Peltier element layer 7 in FIG. 1 is formed thereon.

  3 is a cut-away side view of the principal part specifically showing the Peltier structure, FIG. 4 is a top view of the principal part of the Peltier structure seen in FIG. 3, and FIG. 5 is a principal view of the Peltier structure seen in FIGS. It is a partial bottom view, and the same symbols as those used in FIGS. 1 and 2 represent the same portions or have the same meaning.

  In each figure, 21 indicates an n-type semiconductor, 22 indicates a p-type semiconductor, 23 indicates a heat absorption surface side electrode, and 24 indicates a heat dissipation surface side electrode.

  In order to produce this Peltier structure, the heat absorption side metal film 5 and the insulation film 6 are formed in this order on the insulation film 3 covering the silicon wafer chip 1, and the heat absorption surface side electrode 23 is formed on the insulation film 6. An n-type semiconductor 21 and a p-type semiconductor 22 are formed at both ends of each endothermic surface-side electrode 23, and the n-type semiconductor 21 and the p-type semiconductor 22, and the p-type semiconductor 22 and the n-type semiconductor 21 are joined in pairs. The side electrodes 24 are formed, and the heat radiating side metal film 9 is formed on each heat radiating surface side electrode 24 through the insulating film 8 so that the upper surface is flattened.

  Further, from the Peltier structure, electrode lead-out wirings 10n and 10p made of a metal film are drawn out from the n-channel side and p-channel side electrodes and connected to the Peltier element power supply pad 12 or the device signal pad 13.

  When the electrode lead-out wirings 10n and 10p are connected to the Peltier element power supply pad 12, a power inversion circuit 14 is provided in the middle so that the direction of the current to the Peltier structure can be reversed.

  The semiconductor device 50 having the temperature control function described above is fixed to the mounting substrate 15 using an insulating adhesive, and the Peltier element power supply pads 12 and the device signal pads 13 are bonded to the pads 16 on the mounting substrate 15 side by bonding wires 17. Connect with.

  The pads 16 on the mounting substrate 15 are electrically connected to the outside by solder balls 15A (see FIG. 6) fixed to the back surface side of the mounting substrate 15 via the pattern wiring in the mounting substrate 15. Yes.

  6 is a cutaway side view of the main part showing the semiconductor device mounted and sealed on the mounting board, and FIG. 7 is a top view of the main part showing the semiconductor device shown in FIG. The same symbols as used in the above description represent the same parts or have the same meaning.

  In the figure, reference numeral 25 denotes a resin mold formed from the periphery including the pads 12 and 13 formed in the semiconductor device and a part of the bonding wire 17 to the exposed surface of the mounting substrate 15. A groove 26 is formed so that the resin mold 25 is not in contact with the heat dissipation side metal film 9 so as to be aligned with the heat dissipation side metal film 9 which is the surface of the Peltier element layer 7.

  6 and 7, in the semiconductor device according to the present invention, the heat dissipation side metal film 9 of the Peltier element is exposed, and the heat absorption side of the Peltier element and the silicon wafer chip 1 are sealed with a resin mold 25. Since there is no contact with the heat radiating side, the influence of the heat radiated from the heat radiating side metal film 9 is reduced.

  Further, since the heat dissipation side metal film 9 of the Peltier element and the upper surface of the resin mold 25 are aligned, when the upper surface of the semiconductor device is pressed by the match plate of the test handler when performing the function test, The pusher and the heat-dissipation side metal film 9 are in good contact with each other, and the match plate functions as a large-area heat radiator. Therefore, the heat generated by the Peltier element can be sufficiently dissipated by sending room temperature wind.

  Furthermore, the semiconductor device is provided with a power inversion circuit 14 between the Peltier element electrode lead wires 10n and 10p and the Peltier element power supply, and can easily be inverted between the heat absorption side and the heat dissipation side by switching the direction of the supply current. Therefore, the semiconductor device can be applied from a low temperature to a high temperature.

  FIG. 8 is a principal circuit diagram showing an example of a power supply inverting circuit. The same symbols as those used in FIGS. 1 to 7 represent the same parts or have the same meaning. In the figure, reference numeral 27 denotes a control terminal to which a signal of "H" level or "L" level is input. If the input of the control terminal 27 is "H" level, the Peltier element electrode lead-out wiring 10n is (-). If the Peltier element electrode lead wire 10p is (+) and the input of the control terminal 27 is at "L" level, the Peltier element electrode lead wire 10n is (+) and the Peltier element electrode lead wire 10p is (-).

The amount of heat generation or endotherm W per unit time of the Peltier element is
W = IIi (1)
II: Peltier coefficient i: Expressed by a flowing current. According to Non-Patent Document 1, the Peltier coefficient II is about 0.8 J / C in a wide temperature range of 400K or less by combining p-type silicon and n-type silicon.

The temperature change ΔT due to the Peltier effect is expressed by the following formula (2) using the energy change ΔW on the pn coupling surface where heat absorption and heat dissipation are generated and the thermal conductance G _th .
ΔT = ΔW / G _th (2)

For example, when the thermal conductance G _th is 1 mW / K, in order to set the temperature on the heat absorption side to −50 ° C., if the temperature on the heat dissipation side is 25 ° C., a temperature difference of 75 ° C. results. In addition, from equation (2), a current of about 93 mA may be passed through the Peltier element.

  Since the above calculation is for the case where the Peltier element itself does not generate heat, it is necessary to increase the current flowing through the Peltier element in accordance with the amount of heat in order to keep the temperature on the heat absorption side constant. Current control can be performed by a power supply inverting circuit as shown.

  FIG. 9 is a cutaway explanatory view showing a part of a test handler for explaining a case of testing a semiconductor device of the present invention. In FIG. 9, 51 is a test chamber, 52 is an air inlet fan, 53 Is an air delivery fan, 54 is a match plate, 55 is a pusher, 56 is a Peltier element integrated semiconductor device, 57 is a contact, 58 is a socket board, 59 is a measurement jig, 60 is a test head, 61 is a temperature detection circuit, Reference numeral 62 denotes a current control circuit, and 63 denotes a power supply unit (power supply for supplying a Peltier element).

  The test handler is a device that automatically performs the mounting from the mounting of the semiconductor device to the test jig to the payout after the test. FIG. 9 shows a simplified test chamber portion in the test handler.

  Although only one pusher 55 is shown in FIG. 9, actually, a large number of pushers 55 are arranged and attached to a large-area match plate 54, and a large number of semiconductor devices are handled in a lump. be able to.

  In the semiconductor device mounting portion in the test handler, a large number of semiconductor devices set on the JEDEC standard IC tray are arranged on the measurement tray. Incidentally, about 4 to 64 semiconductor devices can be simultaneously mounted on the measurement tray.

  The measurement tray on which the semiconductor devices are arranged is transported into the test chamber 51 and mounted on the measurement jig 59, the semiconductor device 56 and the socket board 58 are associated with each other, and the semiconductor device 56 is moved by the pusher 55 descending. The signal terminal of the semiconductor device 56 contacts the contact 57 that is pushed down and attached to the socket board 58. At this time, a signal is sent from the test handler to the test head, and the test is started.

  The test chamber 51 is provided with an air inlet fan 52 and an air outlet fan 53, and the heat transmitted to the match plate 54 is effectively transmitted by sending air from outside into the test chamber 51 and sending it out. It is possible to maintain a constant temperature equivalent to the room temperature by being diffused, and therefore it is possible to prevent a change with time in the endothermic effect when a current is passed through the Peltier element.

  In this case, when the chip temperature of the semiconductor device is set to, for example, −30 ° C., if the room temperature is 25 ° C., the Peltier element supply current is controlled so that a temperature difference of 55 ° C. is obtained. The detection of the chip temperature can be easily realized by using an appropriate means such as a forward characteristic of a diode configured at an input / output terminal of the semiconductor device.

  When performing a high temperature test, the power supply inversion circuit described with reference to FIG. 8 may be used to reverse the direction of the current. For example, when the chip temperature is set to 85 ° C., the temperature is 50 ° C. compared to 25 ° C. What is necessary is just to control a Peltier device supply current so that a difference may be obtained.

  If the power supply terminal that supplies current to the Peltier element, the ground terminal, and the control terminal of the inverting circuit are made independent, the power supply of the semiconductor device can be made using the wiring of the mounting board 15 according to the actual use and purpose of use. It is possible to select to use the power source of the Peltier element in common or independently.

  Further, the control terminal 27 in the power inverter circuit can be cooled or heated by setting the “L” level or “H” level according to the environmental temperature at the time of actual operation. If the environment temperature sensor device is installed and the signal from the sensor is sent to the power inversion circuit, the semiconductor device can be operated more stably with respect to the environment temperature. Can be made.

It is a principal part cutting side view which illustrates the semiconductor device which has the temperature control function of this invention. It is a principal part cutting slope figure which illustrates the semiconductor device which has the temperature control function of this invention. It is a principal part cutting side view showing a Peltier structure concretely. It is a principal part top view of the Peltier structure seen in FIG. It is a principal part bottom view of the Peltier structure seen in FIG.3 and FIG.4. It is a principal part cutting side view showing the semiconductor device mounted in the mounting substrate and sealed. FIG. 7 is a main part top view showing the semiconductor device seen in FIG. 6. It is a principal part circuit diagram showing an example of a power supply inversion circuit. It is principal part cutting explanatory drawing showing a part of test handler for demonstrating the case where the semiconductor device of this invention is tested.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon wafer chip 2 Pad 3 Insulating film 4 Insulating film 5 Endothermic metal film 6 Insulating film 7 Peltier element layer 8 Insulating film 9 Heat radiating side metal film 10, 10n, 10p Peltier element electrode lead-out wiring 11 Insulating film 12 For Peltier element power supply Pad 13 Device Signal Pad 14 Power Inversion Circuit 15 Mounting Board 15A Solder Ball 16 Mounting Board Side Pad 17 Bonding Wire 50 Semiconductor Device Having Temperature Control Function

Claims (3)

A semiconductor device in which a Peltier element module that exposes a heat-dissipating metal film is formed on a wafer chip in which the device is incorporated;
A mounting substrate on which the semiconductor device is mounted;
A resin mold that covers a part of the surface of the semiconductor device from the exposed surface of the mounting substrate and has a height aligned with the upper surface of the heat dissipation side metal film ;
The semiconductor device having a temperature control function, wherein the resin mold seals pads and wirings and maintains a required gap between the exposed heat-dissipation-side metal film . Power inverting circuit inserted between the Peltier element power supply and the Peltier element module
The semiconductor device having a temperature control function according to claim 1, comprising: Peltier element module wiring and power or signal pads are formed on a wafer chip in a semiconductor device.
The semiconductor device having a temperature control function according to claim 1 or claim 2, wherein the feature to.

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