JP4222525B2 - Semiconductor device, method for manufacturing the same, and reflective liquid crystal display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, a manufacturing method thereof, and a reflective liquid crystal display device, and more particularly, a semiconductor device suitable for directly using another component or device such as a liquid crystal on the surface of a chip, a manufacturing method thereof, and The present invention also relates to a reflective liquid crystal display device using the semiconductor device.
[0002]
[Prior art]
In general, a semiconductor device such as an LSI has a chip including various elements formed on a semiconductor substrate such as silicon (Si), and multilayer wiring formed on the substrate for operating these elements. This multilayer wiring is usually formed by laminating an Al-based material such as an Al-Si alloy on an interlayer insulating film such as a silicon oxide film deposited on a substrate by CVD (Chemical Vapor Deposition) or the like to form a metal film. The metal film is formed into a predetermined pattern by repeating the process of forming a wiring and further depositing another interlayer insulating film thereon as necessary.
[0003]
On the other hand, when driving a reflective liquid crystal or the like on a semiconductor chip, such as a Si chip-based liquid crystal, an interlayer insulating film or a passivation film that is an uppermost insulating film is formed into a mirror-like surface with extremely high flatness. There was a demand to make it as thin as possible.
[0004]
With ordinary interlayer film planarization, such as SOG (Spin On Glass) coating and etch back, it is possible to smooth the wiring step to such an extent that wiring on the upper layer becomes easy. It cannot be in a close and extremely flat state. There is a CMP (Chemical Mechanical Polishing) method as a method of making the flatness extremely high, and a case is considered in which this technique is applied to a conventional multilayer wiring insulating film and the surface thereof is flattened.
[0005]
FIG. 20 shows a wiring 2 having a thickness T1 formed on the flat insulating film 1 and a flat insulating film 3 having a thickness T2 formed thereon. In order to form by the CMP method, an insulating material is first deposited to a thickness of at least T3 (= T1 + T2) indicated by a two-dot chain line, and then a thickness exceeding T2 (T3−T2) is polished. There is a need. That is, in order to planarize the insulating film by the CMP method, it is necessary to deposit an insulating material having a film thickness of twice or more the step T1 corresponding to the wiring 2 and to polish the step or more.
[0006]
On the other hand, the polishing by the CMP method has a large variation, and a variation of 10% or more of the polishing amount (thickness) can occur. Therefore, the polishing amount should be as small as possible for planarization.
[0007]
[Problems to be solved by the invention]
However, when an Al-based material is used for the wiring layer, in order to function as an electrode or wiring, it is necessary to increase the thickness to, for example, 0.5 μm or more, and accordingly, the polishing amount is also required to be 0.5 μm or more. Thus, when the wiring 2 is formed of an Al-based material, the amount of polishing becomes thick, so that there is a problem in forming a mirror-like flat surface in consideration of variations in polishing.
[0008]
In addition, as described above, when the thin insulating film 3 is formed on the wiring 2 by the CMP method, the Al-based wiring material that is usually used is relatively soft. However, there is a drawback that the thickness tends to be non-uniform, and it is difficult to completely flatten in this respect.
[0009]
Therefore, it is extremely difficult to form an interlayer insulating film or a passivation film having a thin and completely flat mirror-like flat surface on a wiring formed of an Al-based material having a thickness of 0.5 μm or more as in the conventional case. There was a problem that it was difficult.
[0010]
Further, in recent semiconductor chips, a silicon nitride (hereinafter referred to as p-SiN) film deposited mainly by plasma CVD (Chemical Vapor Deposition) is formed on the uppermost layer as a chip protective film in order to prevent wiring corrosion. Used.
[0011]
FIG. 21 schematically shows an enlarged cross section of the main part of an example of such a semiconductor chip. That is, this semiconductor chip includes a first interlayer insulating film 14 and a second interlayer insulating film on a semiconductor substrate 10 made of silicon (Si) in which a source / drain and the like constituting a so-called MOS transistor are formed via a LOCOS 12. 16 and the third interlayer insulating film 18 are sequentially stacked. A first wiring layer 22 connected to the lower gate electrode 20 through a contact hole is formed on the first interlayer insulating film 14, and a second wiring layer 24 is formed on the second interlayer insulating film 16. However, a bonding pad 26 made of the exposed second wiring layer 24 is formed in the opening of the uppermost third interlayer insulating film 18. In this semiconductor chip, the third interlayer insulating film 18 as the uppermost layer is a chip protective film.
[0012]
By the way, depending on the use of the semiconductor chip, in addition to the connection by the normal bonding performed through the bonding pad 26, other parts and devices are directly mounted on the chip, for example, Si chip-based liquid crystal. The case where it connects with has come out.
[0013]
However, as described above, when another component or device is directly attached to the chip and electrically connected thereto, a chip protective film is formed on the uppermost wiring layer as in the semiconductor chip shown in FIG. There was also a problem that it could not be formed.
[0014]
The present invention has been made to solve the above-mentioned conventional problems, and it is a first object of the present invention to provide a semiconductor device having a chip suitable for mounting a liquid crystal on the surface and a manufacturing method thereof.
[0015]
The second object of the present invention is to form an insulating film having a mirror-like flat surface that is thin and has a very flat surface on the uppermost wiring layer.
[0016]
The third object of the present invention is to sufficiently protect the inside of the chip so that other components and devices can be directly attached to the chip surface.
[0017]
It is a fourth object of the present invention to provide a reflective liquid crystal display device formed integrally with a chip.
[0018]
[Means for Solving the Problems]
  A first invention of the present application is a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate.In,Laminated on the lower wiring layer and the lower wiring layer;The uppermost interlayer insulating film having a flat upper surface is laminated on the flat surface of the uppermost interlayer insulating film.,The uppermost wiring layer is formed of a metal having a hardness higher than that of an Al-based material and has a thickness of 0.5 μm or less, and a mirror having a mirror-like flat surface laminated on the uppermost wiring layer.TsuWith the passivation filmA bonding pad having an opening in the passivation film and the uppermost interlayer insulating film to expose the lower wiring layerBy adopting a configuration in which is formed, the first and second problems are solved.
[0019]
That is, on the flat surface of the uppermost interlayer insulating film, by forming a thin uppermost wiring layer having a predetermined pattern with, for example, a titanium-based material having sufficient hardness compared to an Al-based material that is usually used as a wiring material. The insulating material deposited thereon can be polished to a sufficiently thin and mirror-like flat surface. Here, Ti, Cr, Co, Ni, Mo, W, Pt, or a silicide thereof, or a composite film of these and TIN formed on the Ti, Cr, Co, Ni, Mo, W, Pt, or the like has a sufficient hardness as compared with the Al-based material. Can be used.
[0020]
  The first invention is a method of manufacturing a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate.Forming a lower wiring layer on the substrate; and on the lower wiring layerA step of flattening the deposited insulating material to form an uppermost interlayer insulating film; and on a flat surface of the uppermost interlayer insulating film., Formed of a metal having a hardness higher than that of an Al-based material and having a thickness of 0.5 μm or lessForming the uppermost wiring layer of a predetermined pattern and the entire substrate on the uppermost wiring layer;By depositing an insulating film and polishing it by CMPForming a top insulating film having a mirror-like flat surface;Opening the uppermost insulating film and the uppermost interlayer insulating film to form a bonding pad in which the lower wiring layer is exposed;Thus, the semiconductor chip can be reliably manufactured.
[0021]
  The second invention of the present application is also a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate.A lower wiring layer and a chip protective film made of a silicon nitride film or a silicon oxide nitride film provided on the lower wiringTop interlayer insulating filmAnd compared to the Al-Si alloy provided on the uppermost interlayer insulating filmCorrosion resistant materialConsist ofTop wiring layerAnd a bonding pad that opens the uppermost interlayer insulating film and exposes the lower wiring layer.Thus, the first and third problems are solved.
[0022]
  For the uppermost wiring layer, a material that is more resistant to corrosion than Al-Si alloy or the like that is usually used as a wiring material is used, and in order to protect the inside of the chip, the uppermost interlayer insulating film directly below it has chip protection. By having it, the reliability of the chip is ensured and the uppermost wiring layer can be used in a substantially bare state, and other parts and devices can be directly attached to the chip for electrical connection. It becomes.Here, the chip protection means that the chip is protected from being affected by various external factors that adversely affect the semiconductor element. The required characteristics are as follows: 1) There are no pinholes, cracks or micro-defects in the protective film itself, 2) Moisture permeation that induces corrosion of wiring, especially Al-based wiring can be prevented, and 3) Semiconductors It is possible to prevent permeation of alkali ions, particularly Na + ions, which deteriorate the characteristics of transistors and the like formed at the substrate interface. As the protective film having such characteristics, a silicon nitride film, a silicon oxide nitride film, or the like formed by a plasma CVD method is used.
[0023]
  The third invention of the present application is further directed to a reflective liquid crystal display device,Laminated on the lower wiring layer and the lower wiring layer;An uppermost interlayer insulating film having a flat upper surface, and laminated on the flat surface of the uppermost interlayer insulating film;AlThe uppermost wiring layer of a predetermined pattern having a thickness of 0.5 μm or less and a mirror-like flat surface laminated on the uppermost wiring layer is formed of a metal having a hardness higher than that of the system material.TsuWith the passivation filmA bonding pad having an opening in the passivation film and the uppermost interlayer insulating film to expose the lower wiring layerA chip havingProvided on the lower wiring layer and the lower wiring layer,The upper surface is formed flat, andMade of silicon nitride film or silicon oxide nitride filmThe uppermost interlayer insulating film having chip protection, and laminated on the flat surface of the uppermost interlayer insulating film,Compared to Al-Si alloyAn uppermost wiring layer made of a material having corrosion-resistant characteristics;A bonding pad that opens the uppermost interlayer insulating film and exposes the lower wiring layer;The fourth problem is solved by providing a chip having a liquid crystal and a reflective liquid crystal unit disposed on the chip and driven by the chip.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
In a preferred embodiment of the first invention, the uppermost insulating film that is thin and has a mirror-like flat surface is a passivation film. In order to reduce the step of the uppermost wiring layer that is the base, (1) the uppermost interlayer insulating film is formed. (2) The uppermost wiring layer thereon is not made of an Al-based material, and a metal having a hardness higher than that of the Al-based material is formed as a thin film having a thickness of 0.5 μm or less.
[0025]
Further, when performing CMP to form a passivation film, first, a first insulating film having a sufficiently lower polishing rate than that of the second insulating film to be polished is deposited, and the second insulating film is formed on the Al insulating film. The film is deposited about twice as thick as the thin conductive film made of a film having a hardness higher than that of the system material, and the second insulating film is polished by CMP using the first insulating film having a low polishing rate as a stopper.
[0026]
In addition, when the above CMP is performed, a minute defect enters the surface to be polished. Therefore, in order to ensure the insulation of the passivation film, a thin insulating film is further deposited thereon. Further, when the passivation film is formed in this way, since the uppermost wiring layer cannot be die-bonded, the lower wiring layer is drawn out to form a bonding pad.
[0027]
Hereinafter, a more specific embodiment of the first invention applied to the case of four-layer wiring will be described in detail with reference to the drawings. Note that the present invention is characterized by the laminated structure of the chip included in the semiconductor device, and therefore the description will focus on the wiring process related thereto. Here, a MOS type semiconductor device is taken as an example, but this is not always necessary.
[0028]
1 to 8 are partial cross-sectional views for explaining a semiconductor chip manufacturing method according to the first embodiment of the first invention. In FIG. 1, a first interlayer insulating film 114, a second interlayer insulating film 116, and a third interlayer are formed on a semiconductor substrate 110 made of, for example, Si, in which elements and the like constituting an element are formed via a LOCOS 112. An insulating film 118 is sequentially stacked, and on the first interlayer insulating film 114, a lower gate electrode 120, a first wiring layer 122 through a via hole, and a second interlayer insulating film 116 are formed. Similarly, the second wiring layers 124 are shown in a stacked state. Here, the process up to the step of laminating the third interlayer insulating film 118 is shown.
[0029]
Specifically, the first interlayer insulating film 114 is composed of two layers (not shown) of NSG (Non-doped Silicate Glass) and BPSG (Boron Phosphorous Silicate Glass) on the second, second, and second layers. The three interlayer insulating films 116 and 118 are both silicon oxide films (hereinafter also referred to as p-TEOS) laminated by plasma CVD using TEOS (Tetra Ethyl Ortho Silicate) as a raw material. The gate electrode 120 is made of polysilicon (p-Si), and the first and second wiring layers 122 and 124 are made of an Al-Si alloy that is an Al-based material (but not limited to this). Next, as shown in FIG. 2, for example, Al—Si is deposited as a third layer metal on the third interlayer insulating film 118, and this third layer metal is patterned by an appropriate method to form a third layer. A wiring layer 126 is formed. Note that the third wiring layer 126 has a film thickness sufficient for bonding, for example, 0.5 μm, in order to use a part of the third wiring layer 126 as the bonding pad 126A. The state shown in FIG. 2 can be manufactured according to a conventional method.
[0030]
Next, a fourth interlayer insulating film (uppermost interlayer insulating film) 128 shown in FIG. 3 is formed. This may be formed by any method. For example, p-TEOS is deposited in the state of FIG. 2 by 1.4 μm (not shown), and this thick silicon oxide is 0.7 μm by CMP. Polish to the thickness indicated by the broken line in FIG. Next, an insulating film 128A made of p-TEOS is further deposited by 0.2 μm thereon, and the fourth interlayer insulating film 128 having a flat surface is formed by covering minute defects by CMP. Thereafter, via holes 130 are formed by a conventional method to obtain the state shown in FIG.
[0031]
At this time, a via hole is not formed in the fourth interlayer insulating film 128 in the region (right side in the figure) to be the bonding pad 126A of the third wiring layer 126. However, in some cases, a via hole may be formed in the region of the bonding pad 126A. However, in this case, a step in a large region is not formed because it is undesirable for planarization of a passivation film by CMP performed later. .
[0032]
Next, as the fourth wiring layer (uppermost wiring layer), 0.03 μm of Ti is deposited as a material having a hardness higher than that of the Al-based material, and subsequently 0.1 μm of TiN is deposited thereon and patterned by an appropriate method. As shown in FIG. 4, a fourth wiring layer 132 electrically connected to the third wiring layer 126 is formed. At this time, since the TiN / Ti film is not suitable for bonding, the TiN / Ti film in the bonding pad portion is removed by etching.
[0033]
Next, a passivation film is formed as a thin uppermost insulating film having a mirror-like flat surface. For this purpose, first, a silicon nitride film (hereinafter referred to as p-SiN) formed by plasma CVD is deposited as a first insulating film by 0.3 μm, and subsequently, p-TEOS is deposited as a second insulating film 136 by about 0.4 μm. Deposited to the state of FIG.
[0034]
Next, the p-TEOS is polished by, for example, 0.5 μm by CMP to fill the concave portion of the first insulating film 134 with the p-TEOS as shown in FIG. 6 and above the fourth wiring layer 132. The second insulating film 136 is substantially absent from the flat portion. In this step, the p-SiN of the first insulating film 134 has a polishing rate by CMP of less than half that of p-TEOS. Therefore, the first insulating film 134 can function as a stopper during polishing. This function makes it possible to stably form a uniform flat surface with a film thickness of approximately 0.3 μm mainly composed of p-SiN by CMP.
[0035]
Thereafter, as shown in FIG. 7, 0.2 μm of p-SiN is deposited as the third insulating film 138 to cover and protect the micro defects generated by the CMP, thereby completing the passivation film 140.
[0036]
Through the above-described steps, a thin passivation film 140 of about 0.5 μm that is substantially made of only p-SiN and has a mirror-like flat surface that is completely flattened can be formed. Since the relative dielectric constant of the silicon oxide film is about 3.9 and the relative dielectric constant of the silicon nitride film is about 7.5, the oxide film thickness is converted to about 0.5 μm × 3.9 / 7.5 = 0.26 μm. This corresponds to forming a thin passivation film.
[0037]
Next, as shown in FIG. 8, an insulating film on the bonding pad 126A is opened. This is because the third insulating film 138 is p-SiN, the second interlayer insulating film 136 is p-TEOS, the first insulating film 134 is p-SiN, and the fourth interlayer insulating film 128 is p-TEOS. It can form by etching in this order. In the second etching of p-TEOS, since the first insulating film 134 in the bonding pad portion is slightly depressed at the time of deposition, there is a possibility that p-TEOS may remain in that portion even after CMP. Is going. FIG. 8 also shows the meaning of the shading used to represent the cross section.
[0038]
As described above in detail, according to the first embodiment, since the material having a higher hardness than the Al-based material is used as the uppermost wiring layer, the wiring layer is not easily deformed during CMP. The passivation film 140 having the flatness can be stably formed. Accordingly, when a capacitor having, for example, the fourth wiring layer 132 as one electrode is formed on the passivation film 140, the distance between both electrodes can be made narrow and uniform in the surface direction. An accurate capacitor can be configured. Further, when the mirror-like flat surface of the passivation film 140 is used as a light reflecting surface, complete regular reflection can be performed.
[0039]
In the first embodiment, the TiN / Ti film is used as the uppermost wiring layer. However, the present invention is not limited to this, and Ti, Cr, Co, Ni, Mo, W, Pt, silicides thereof, and these and the top thereof are used. A composite film formed with TiN can be used.
[0040]
The specific dimensions are not limited to those described above, the thickness of the passivation film 140 is 0.6 μm or less, the first insulating film 134 for forming the thickness is 0.4 μm or less, and the second insulating film 136. The preferred range is 0.2 to 0.5 μm, and the third insulating film 138 is preferably 0.1 to 0.3 μm.
[0041]
The fourth wiring layer 132 made of TiN / Ti preferably has a total thickness of 0.1 to 0.2 μm, in which case TiN is preferably 0.07 to 0.15 μm and Ti is preferably 0.02 to 0.05 μm. .
[0042]
The thickness of the passivation film 140 is preferably 0.3 μm or less in terms of the oxide film thickness based on the dielectric constant.
[0043]
Although the first invention has been specifically described above, the first invention is not limited to that shown in the first embodiment, and various modifications can be made without departing from the scope of the invention.
[0044]
For example, in the first embodiment, the first invention has been described with respect to the passivation film, but an interlayer insulating film may also be used. In this case, an accurate capacitive element can be formed by placing an electrode on the interlayer insulating film.
[0045]
Next, an embodiment of the second invention will be described in detail.
[0046]
9 to 18 are cross-sectional views of relevant parts showing the characteristics of the process of manufacturing the semiconductor chip of the second embodiment according to the second invention in the order of the processes. Hereinafter, it demonstrates sequentially according to these figures.
[0047]
As shown in FIG. 9, a MOS transistor is formed on a semiconductor substrate 210 made of silicon (Si) by a normal process. This process is substantially the same as that of the conventional semiconductor chip shown in FIG. 21, in which a LOCOS 212 is laminated on the semiconductor substrate 210, and polysilicon (p) is formed on the gate oxide film between the source and drain. A gate electrode 214 made of -Si) is formed.
[0048]
Next, as shown in FIG. 10, as the first interlayer insulating film 216, for example, NSG (Non Silicate Glass) of 1000 to 2000 mm, and 4,000 to 8000 mm of BPSG (Boron Phosphorous Silicate Glass) indicated by broken lines are deposited, In order to alleviate the surface step, for example, after annealing at 900 to 950 ° C. for 20 to 60 minutes, a contact hole 216A is opened in the first interlayer insulating film 216.
[0049]
Next, as shown in FIG. 11, a first wiring layer 218 is deposited on the first interlayer insulating film 216 by, for example, an Al—Si alloy layer having a thickness of 0.4 to 1.0 μm by a sputtering method. It forms by patterning by the method.
[0050]
Subsequently, a second interlayer insulating film is formed. For this purpose, first, as shown in FIG. 12, a silicon oxide film (hereinafter referred to as a p-TEOS film) 220 deposited by plasma CVD using TEOS (Tetra Ethyl Ortho Silicate) as a raw material is about 1.0-2. It is formed with a thickness of 0.0 μm. Then, the surface of the p-TEOS film 220 is polished by about 0.5 to 1.0 μm by CMP (Chemical Mechanical Polishing) to flatten the surface (however, the state immediately after the planarization) Is omitted). The surface of the p-TEOS film 220 is planarized in order to ensure contact by flattening the surface when another device or the like is bonded onto the completed chip and electrically connected. ing.
[0051]
Thereafter, p-SiN having a thickness of about 0.2 to 0.8 μm is deposited as the chip protection film 221 on the planarized p-TEOS film 220, thereby forming the p-TEOS film 220 and the p-TEOS film 220 as shown in FIG. A second interlayer insulating film (uppermost interlayer insulating film) 222 having a two-layer structure composed of the chip protective film 221 is formed. The p-SiN deposited here is a material widely used as a chip protective film in a normal semiconductor.
[0052]
Thus, also in this embodiment, the chip protection film 221 is formed of p-SiN, and the inside of the chip inside the chip protection film 221 is protected. That is, by stacking the protective film 221, chip protection is imparted to the second interlayer insulating film.
[0053]
Next, as shown in FIG. 14, a via hole 224 that penetrates the second interlayer insulating film 222 and reaches the first wiring layer 218 is opened at a predetermined position.
[0054]
Thereafter, as shown in FIG. 15, a second wiring layer (uppermost wiring layer) 226 is formed. This is because about 0.02 to 0.1 μm of Ti (titanium) is formed inside the via hole 224 together with the entire surface of the second interlayer insulating film 222, and subsequently about 0.05 to 0.20 μm of TiN ( Titanium nitride) is deposited to form a TiN / Ti two-layer conductive film, and the conductive film is then patterned by a known method.
[0055]
In the present embodiment, the second wiring layer 226 is left exposed. The reason why the conductive film made of TiN / Ti is used as a wiring material to be exposed on the chip surface is that it is superior in corrosion resistance compared to Al-Si alloy or the like.
[0056]
FIG. 15 shows a state in which the second wiring layer 226 is formed. By doing so, conduction between the second wiring layer 226 and the first wiring layer 218 is achieved. In the case of a normal chip, an insulating film serving as a protective film such as p-SiN is formed on the second wiring layer 226 which is the uppermost wiring layer. In this embodiment, such a protective film is formed. Does not form.
[0057]
As described above in detail, in this embodiment, the second wiring layer 226 made of a material having excellent corrosion resistance is formed as the uppermost wiring layer, and the second interlayer insulating film 222 immediately below the second wiring layer 226 has chip protection. Therefore, the inside of the chip can be surely protected, and corrosion can be prevented even when the second wiring layer 226 is exposed, so that the reliability of the semiconductor device can be ensured and other components and devices can be directly mounted on the chip. And can be electrically connected. As described above, as an apparatus (component) that is directly attached to a chip, for example, a liquid crystal that is attached via a dielectric reflection film using the second wiring layer 226 as an electrode can be cited.
[0058]
Therefore, according to the present embodiment, it is possible to provide a highly reliable semiconductor device having excellent corrosion resistance as well as being able to electrically connect other components and devices directly on the chip.
[0059]
In the second embodiment, the material used as the uppermost wiring layer is a two-layer film of Ti and TiN formed thereon, but the present invention is not limited to this, and other materials can be used. it can.
[0060]
Corrosion is roughly divided into dry corrosion (mainly oxidation) and corrosion by aqueous solution. The ease of oxidation of the metal is based on the free energy at the time of forming the oxide, and the easier the oxidation is, the more negative the free energy. Ti, Cr, Co, Ni, Mo, Ag, W, Pt, Au, etc. are raised as a metal whose value is larger than Al and hardly oxidizes. Corrosion due to an aqueous solution is caused by elution of metal atoms as ions. When two metals are placed in the electrolyte and electrically connected, the metal on the anode side ionizes and moves to the cathode side, and electrons generated by ionization on the anode side flow to the cathode side through external connections, reducing hydrogen ions. To produce OH- ions. The work required to transfer electrons from the anode to the cathode is a change in free energy ΔG accompanying this reaction, ΔG is proportional to the standard electrode potential E, and the more anodic the metal is, the more likely it is to corrode. Examples of metals that have an ionization tendency and a value of E that is smaller than Al and less likely to corrode include Ti, Cr, Co, Ni, Mo, Ag, W, Pt, and Au. Therefore, these metals can be used as a material resistant to corrosion in the second embodiment.
[0061]
Here, in the second embodiment, unlike the first embodiment, the CMP process is not used after the uppermost wiring layer is formed. Therefore, there is no problem even if a soft metal such as Ag or Au is used. In addition, since TiN and W are materials that are extremely resistant to corrosion, not only the metal but also, for example, at least the upper surface of the wiring including Al-based material can be used that is covered with TiN or W. .
[0062]
Next, a third embodiment according to the second invention will be described.
[0063]
FIG. 16 is a partial cross-sectional view showing one of the steps of manufacturing the semiconductor chip of the third embodiment. The state of this cross-sectional view is further oxidized on the second wiring layer 226 of the second embodiment. This is a step of laminating a normal insulating film 228 made of silicon by a known method.
[0064]
After the above process, the insulating film 228 is etched back to a height substantially the same as that of the second wiring layer by a known method, and the level difference generated as a result of patterning of the second wiring layer 226 is also reduced. By flattening with 228A, the semiconductor chip of the third embodiment having the cross-sectional shape shown in FIG. 17 is obtained.
[0065]
In the present embodiment, basically, the insulating film 228A does not exist on the second wiring layer 226 except for the portion above the via hole 224. However, in this case as long as it can be electrically connected to another device or the like, there is no problem even if some insulating film remains on the second wiring layer 226.
[0066]
FIG. 18 is a partial cross-sectional view showing the main configuration of the semiconductor chip according to the fourth embodiment of the second invention. In this chip, a bonding pad 230 is added to the chip of the second embodiment shown in FIG. It has a configuration. FIG. 18 also shows the meaning of the shaded area used to represent the cross-sectional view.
[0067]
In the present embodiment, as in the second embodiment, it is assumed that electrical signals are exchanged with the outside by exposing the top wiring layer of the chip and directly directly connecting to other external devices. However, in addition to this, wire bonding similar to that of a normal chip can be performed. However, since bonding is difficult with TiN / Ti constituting the second wiring layer 226 which is the uppermost wiring layer, when forming the lower first wiring layer, a metal layer of the bonding pad portion is formed at the same time. In addition, a bonding pad 230 is formed by opening the second interlayer insulating film 222 thereabove.
[0068]
Although the second invention has been specifically described above, the second invention is not limited to that shown in the second to fourth embodiments, and various modifications can be made without departing from the scope of the invention.
[0069]
For example, in the above-described embodiment, the case where the p-TEOS film 220 constituting the second interlayer insulating film 222 is planarized by the CMP method is described. However, the present invention is not limited to this, and the polishing may not necessarily be performed. .
[0070]
In addition, the case where the surface of the second interlayer insulating film 222 is covered with the chip protective film 221 in order to provide the chip protective property is shown. You may make it form in.
[0071]
Next, a fifth embodiment according to the third invention will be described in detail.
[0072]
FIG. 19 is a cross-sectional view showing the configuration of the reflective liquid crystal display device of the fifth embodiment.
[0073]
In this embodiment, for example, a P + buried region 312 and an N + buried region 314 are formed on a semiconductor substrate 310 of P type silicon, for example, by buried epitaxial, and a P well 316 and an N well 318 are formed thereon, respectively. Has been. The P well 316 and the N well 318 are separated by a LOCOS 320, for example. By forming the source region 322, the drain region 324, and the gate electrode 326 on each of the wells 316 and 318, high breakdown voltage transistors are formed in a matrix.
[0074]
A first wiring layer 332 made of, for example, an aluminum (Al) -based material is formed on the first interlayer insulating film 330 covering the transistor portion. On the second interlayer insulating film 334 covering the first wiring layer 332, for example, a second wiring layer 336 made of an Al-based material is formed. On the third interlayer insulating film 338 covering the second wiring layer 336, for example, a third wiring layer 340 made of an Al-based material is formed. The surface of the fourth interlayer insulating film (uppermost interlayer insulating film) 342 covering the third wiring layer 340 is polished and planarized by the CMP method according to the first invention, and the chip protection is provided by the second invention. A fourth wiring layer (uppermost wiring layer) 344 made of, for example, a TiN / Ti material is formed thereon according to the second invention. The fourth wiring layer 344 is a liquid crystal pixel electrode layer disposed on the chip, on which a chip protective film (the uppermost insulating film of the first invention) 346 can be formed. Further, since TiN is a material resistant to corrosion as in the embodiment of the second invention, it is not necessary to form a chip protective film. Further, after forming the uppermost wiring layer 344 as in the third embodiment, an insulating film such as silicon oxide is deposited, and the insulating film is removed to a height substantially the same as the uppermost wiring layer. The chip surface may be planarized by forming the insulating film.
[0075]
A liquid crystal driving chip 348 is formed from the semiconductor substrate 310 to the chip protective film 346 (or to the fourth wiring layer 344 when the chip protective film is not formed). 350 is arranged. Specifically, the liquid crystal part 350 is formed on the protective film (or the fourth wiring layer 344) of the mirror-finished chip 348, and is a dielectric with a flat reflecting surface for reflecting incident light. A reflective film 352, a transparent electrode 354 disposed on the reflective film 352, a liquid crystal 356 sealed between the dielectric reflective film 352 and the transparent electrode 354, and a transparent electrode device 354. The liquid crystal protection glass 358 is used. Here, the dielectric reflecting film 352 is made of, for example, titanium oxide formed by electron beam evaporation. Titanium oxide has a high refractive index and is suitable for use as a light reflection film, but is a porous film and has poor insulation and does not function as a chip protection film.
[0076]
In this liquid crystal display device, when the S-polarized incident light incident in the direction of arrow A from the glass surface is reflected again by the planarized dielectric reflecting film 352 to the surface direction, the intensity of the reflected light of S + P polarized light is increased. In addition, by changing the driving state of the transistors formed in a matrix for each pixel in the chip 348, the arrangement state of the liquid crystal is changed so as to form an image.
[0077]
Since the configuration and operation other than the chip 348 in which the first and second inventions are employed are the same as those of a known Si chip-based liquid crystal, detailed description thereof is omitted.
[0078]
In the present embodiment, the first and second inventions are applied to the reflective liquid crystal display device, but the application target of the first and second inventions is not limited to this.
[0079]
【The invention's effect】
According to the first invention, it is possible to provide a semiconductor chip in which an insulating film having a mirror-like flat surface that is thin and has an extremely flat surface is formed on the uppermost wiring layer.
[0080]
Further, according to the second invention, it is possible to provide a semiconductor chip excellent in corrosion resistance in which other components and devices can be electrically connected directly to the chip and the inside of the chip is sufficiently protected. it can.
[0081]
Furthermore, according to the third invention, a reflective liquid crystal display device formed integrally with a chip can be provided.
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional view showing a process of forming up to a third interlayer insulating film in a first embodiment of the present invention.
FIG. 2 is a partial cross-sectional view showing a process of forming a third wiring in the first embodiment.
FIG. 3 is a partial cross-sectional view showing a process of forming a fourth (uppermost) interlayer insulating film, planarizing the surface, and forming a via hole in the first embodiment;
FIG. 4 is a partial cross-sectional view showing a process of forming a fourth (uppermost) wiring layer in the first embodiment.
FIG. 5 is a partial cross-sectional view showing a process of forming first and second insulating films in the first embodiment.
FIG. 6 is a partial cross-sectional view showing a process of polishing a second insulating film in the first embodiment.
FIG. 7 is a partial cross-sectional view showing a process of forming a third insulating film in the first embodiment.
FIG. 8 is a partial cross-sectional view showing a process of forming a window for the bonding pad portion in the first embodiment.
FIG. 9 is a partial cross-sectional view showing a process of forming a MOS transistor in the second embodiment of the present invention.
FIG. 10 is a partial cross-sectional view showing a process of forming a first interlayer insulating film in the second embodiment.
FIG. 11 is a partial cross-sectional view showing a process of forming a first wiring layer in the second embodiment.
FIG. 12 is a partial cross-sectional view showing a step of depositing a p-TEOS film for forming a second interlayer insulating film in the second embodiment.
FIG. 13 is a partial cross-sectional view showing a step of forming a chip protective film on the flat surface of the second interlayer insulating film in the second embodiment.
FIG. 14 is a partial cross-sectional view showing a process of forming a via hole in a second interlayer insulating film in the second embodiment.
FIG. 15 is a partial cross-sectional view showing a main part of a semiconductor chip according to a second embodiment.
FIG. 16 is a partial sectional view showing one manufacturing process in the third embodiment of the present invention.
FIG. 17 is a partial cross-sectional view showing a main part of a semiconductor device according to a third embodiment.
FIG. 18 is a partial sectional view showing the main part of a semiconductor device according to a fourth embodiment of the invention.
FIG. 19 is a partial sectional view showing an essential part of a reflective liquid crystal display device according to a fifth embodiment of the invention.
FIG. 20 is a partial cross-sectional view for explaining a problem of the conventional method
FIG. 21 is a partial cross-sectional view showing a main part of a conventional semiconductor device.
[Explanation of symbols]
110, 210, 310 ... Semiconductor substrate
112, 212, 320 ... LOCOS
114, 216, 330 ... first interlayer insulating film
116, 334 ... second interlayer insulating film
118, 338 ... Third interlayer insulating film
120, 214, 326 ... gate electrodes
122, 218, 332 ... first wiring layer
124, 226, 336 ... second wiring layer
126, 340 ... third wiring layer
126A, 230 ... Bonding pads
128, 222, 342 ... uppermost interlayer insulating film
130, 224 ... via hole
132, 226, 344 ... uppermost wiring layer
134: first insulating film
136: Second insulating film
138 ... Third insulating film
140 ... Passivation film (uppermost insulating film)
220 ... P-TEOS film
221, 346... Chip protective film
228 ... Insulating film
348 ... chip
350 ... Liquid crystal part
354 ... Liquid crystal

Claims (14)

In a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate,
A lower wiring layer;
An uppermost interlayer insulating film laminated on the lower wiring layer and having a flat upper surface;
Laminated on a flat surface of the uppermost interlayer insulating film, formed of a metal having a hardness higher than that of an Al- based material, and having an uppermost wiring layer having a predetermined pattern with a thickness of 0.5 μm or less;
Stacked on the outermost on the wiring layer, and path Tsu Shibeshon film having a mirror-like flat surface,
A bonding pad that opens the passivation film and the uppermost interlayer insulating film to expose the lower wiring layer;
A semiconductor device characterized in that is formed. The uppermost wiring layer is formed of Ti, Cr, Cu, Ni, Mo, W, Pt, or a silicide thereof, or a composite film of these and TiN formed thereon. The semiconductor device according to claim 1. 2. The semiconductor device according to claim 1, wherein the uppermost wiring layer is formed of a TiN / Ti film in which TiN is deposited on Ti. A lower wiring layer;
An uppermost interlayer insulating film laminated on the lower wiring layer and having a flat upper surface;
Laminated on a flat surface of the uppermost interlayer insulating film, formed of a metal having a hardness higher than that of an Al- based material, and having an uppermost wiring layer having a predetermined pattern with a thickness of 0.5 μm or less;
Stacked on the outermost on the wiring layer, and path Tsu Shibeshon film having a mirror-like flat surface,
A chip having a bonding pad that opens the passivation film and the uppermost interlayer insulating film and exposes the lower wiring layer ;
A reflective liquid crystal unit disposed on the chip and driven by the chip;
A reflective liquid crystal display device comprising: The uppermost wiring layer is formed of Ti, Cr, Cu, Ni, Mo, W, Pt, or a silicide thereof, or a composite film of these and TiN formed thereon. The reflective liquid crystal display device according to claim 4, wherein: In a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate,
A lower wiring layer;
Provided on the lower layer wiring, and the uppermost interlayer insulating film including a chip protection film made of a silicon nitride film or a silicon oxynitride film,
Provided on the uppermost insulating layer, and the uppermost wiring layer made of a material resistant to corrosion compared to the Al-Si alloy,
A bonding pad that opens the uppermost interlayer insulating film and exposes the lower wiring layer;
Wherein a has a. 7. The semiconductor device according to claim 6, wherein the uppermost wiring layer is made of any one of Ti, Cr, Co, Ni, Mo, Ag, W, Pt, Au, and TiN. 7. The semiconductor device according to claim 6, wherein an upper surface of the uppermost wiring layer is covered with TiN or W. 9. The semiconductor device according to claim 6, wherein the uppermost wiring layer is used as an electrode and is electrically connected to another component or device directly attached on the chip. A lower wiring layer;
An uppermost interlayer insulating film provided on the lower wiring layer, having a flat upper surface and having a chip protection property made of a silicon nitride film or a silicon oxide nitride film ;
An uppermost wiring layer made of a material laminated on a flat surface of the uppermost interlayer insulating film and made of a material having resistance to corrosion compared to an Al-Si alloy ;
A chip having a bonding pad that opens the uppermost interlayer insulating film and exposes the lower wiring layer ; and
A reflective liquid crystal unit disposed on the chip and driven by the chip;
A reflective liquid crystal display device comprising: 11. The reflective liquid crystal display device according to claim 10, wherein the uppermost wiring layer is made of any one of Ti, Cr, Co, Ni, Mo, Ag, W, Pt, Au, and TiN. 11. The reflective liquid crystal display device according to claim 10, wherein the upper surface of the uppermost wiring layer is covered with TiN or W. In a method of manufacturing a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate,
Forming a lower wiring layer on the substrate;
Flattening the insulating material deposited on the lower wiring layer to form an uppermost interlayer insulating film;
Forming the uppermost wiring layer having a predetermined pattern on the flat surface of the uppermost interlayer insulating film, which is made of a metal having a hardness higher than that of an Al-based material and having a thickness of 0.5 μm or less ;
A step of forming an uppermost insulating film having a mirror-like flat surface by depositing an insulating film over the entire substrate on the uppermost wiring layer and polishing by a CMP method ;
Opening the uppermost insulating film and the uppermost interlayer insulating film to form a bonding pad in which the lower wiring layer is exposed; and
A method for manufacturing a semiconductor device, comprising: The uppermost wiring layer is formed of any one of Ti, Cr, Cu, Ni, Mo, W, Pt, a silicide thereof, or a composite film of these and TiN formed thereon. A method of manufacturing a semiconductor device according to claim 13.

Images