JP4233551B2 - Timing control apparatus and timing control method - Google Patents

Description

  The present invention relates to a timing control device and a timing control method, and more particularly to a timing control device and a timing control method including a first oscillation element and a second oscillation element.

  For example, Patent Document 1 is known as a method for correcting the oscillation frequency of the CPU. Conventionally, crystal oscillators, ceramic oscillators, CR oscillators, and the like have been used as oscillation elements. In general, in a digital camera, a crystal oscillator is used for the operating frequency of an IPP (Image Pre Processor) which is a digital signal processing unit, so that the accuracy is considerably high. On the other hand, for the operating frequency of the CPU, an inexpensive ceramic oscillator is often used because of its cost and short rise time of oscillation. When performing processing such as shooting, the CPU often takes the timing of each control starting from the IPP vertical synchronization signal (vd). In this case, the timing is interrupted by interrupting the vertical synchronization signal (vd). The timer in the CPU is started from the point of detection, and the processing is performed on the control target after the lapse of a specified time.

Japanese Patent Laid-Open No. 5-75445

  However, as described above, since an expensive crystal oscillator is used on the IPP side, the error of the oscillation frequency is reduced. On the other hand, an inexpensive ceramic oscillator is used on the CPU side. The error becomes larger and the time accuracy becomes worse. Therefore, there is a problem that an error occurs when the CPU determines the control start timing of the control target with reference to the vertical synchronization signal (vd) input from the IPP.

  The present invention has been made in view of the above, and a timing control device and a timing control method that prevent an error in the start timing when a control start timing of a control target is determined using a plurality of oscillation elements. The purpose is to provide.

  In order to solve the above-described problems and achieve the object, the present invention provides a first oscillation element, a second oscillation element, and a first cycle having a predetermined period based on the oscillation frequency of the first oscillation element. First signal generating means for outputting one signal, period measuring means for measuring the period of the first signal by counting based on the oscillation frequency of the second oscillation element, and oscillation of the second oscillation element Based on a control timing determining means for determining a control timing based on the frequency, a theoretical value when the period of the first signal is measured at the oscillation frequency of the second oscillating element, and a count value obtained by the period measuring means. Correction means for correcting the control timing determined by the control timing determination means.

  According to a preferred aspect of the present invention, it is desirable that the correction by the correction means is performed within an error range of the second oscillation element.

  Further, according to a preferred aspect of the present invention, it is desirable that the period measuring unit measures the period of the first signal a plurality of times, and uses the average value of the plurality of times as a period count value.

  According to a preferred aspect of the present invention, it is desirable that at least one of the first oscillation element and the second oscillation element oscillates a reference frequency of a central processing unit that controls the apparatus.

  In order to solve the above-described problems and achieve the object of the present invention, the present invention includes a first signal generation step of outputting a first signal having a predetermined period based on the oscillation frequency of the first oscillation element. , A period measuring step for measuring the period of the first signal by counting based on the oscillation frequency of the second oscillation element, and a control timing determination for determining a control timing based on the oscillation frequency of the second oscillation element A control timing determined by the control timing determination step based on a theoretical value obtained when measuring the cycle of the first signal at the oscillation frequency of the second oscillation element and the count value obtained by the cycle measurement step. And a correction step for correcting.

  The present invention includes a first oscillating element, a second oscillating element, first signal generating means for outputting a first signal having a predetermined period based on an oscillating frequency of the first oscillating element, Period measuring means for measuring the period of one signal by counting based on the oscillation frequency of the second oscillating element; control timing determining means for determining control timing based on the oscillation frequency of the second oscillating element; The control timing determined by the control timing determination means is corrected based on the theoretical value when the period of the first signal is measured at the oscillation frequency of the second oscillation element and the count value by the period measurement means. When the control start timing of the control target is determined on the basis of the vertical synchronization signal, the control target is controlled at the start timing with less error. It becomes possible.

  Hereinafter, a digital camera to which a timing control apparatus and a timing control method according to the present invention are applied will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. In addition, constituent elements in the following embodiments include those that can be easily assumed by those skilled in the art or that are substantially the same.

  FIG. 1 is a configuration diagram of a digital camera according to the present embodiment. In the figure, reference numeral 100 denotes a digital camera. The digital camera 100 includes a lens system 101, a mechanical mechanism 102 including an aperture / filter unit, a CCD 103, a CDS circuit 104, a variable gain amplifier (AGC amplifier) 105, an A / A D converter 106, IPP 107, DCT 108, coder 109, MCC 110, DRAM 111, PC card interface 112, CPU 121, display unit 122, operation unit 123, SG (control signal generation) unit 126, strobe device 127, battery 128, DC-DC A converter 129, an EEPROM 130, a focus driver 131, a pulse motor 132, a zoom driver 133, a pulse motor 134, and a motor driver 135 are provided. A detachable PC card 150 is connected via the PC card interface 112.

  The lens unit includes a mechanical mechanism 102 including a lens 101 system, an aperture / filter unit, and the like. A mechanical shutter of the mechanical mechanism 102 performs simultaneous exposure of two fields. The lens system 101 is composed of, for example, a varifocal lens, and includes a focus lens system 101a and a zoom lens system 101b.

  The focus driver 131 drives the pulse motor 132 according to the control signal supplied from the CPU 121 to move the focus lens system 101a in the optical axis direction. The zoom driver 133 drives the pulse motor 132 according to the control signal supplied from the CPU 121 to move the zoom lens system 101b in the optical axis direction. Further, the motor driver 135 drives the mechanical mechanism 102 in accordance with a control signal supplied from the CPU 121, and sets, for example, an aperture value of the aperture.

  A CCD (charge coupled device) 103 converts an image input via the lens unit into an electrical signal (analog image data). A CDS (correlated double sampling) circuit 104 is a circuit for reducing noise in the CCD type image pickup device.

  In addition, the AGC amplifier 105 corrects the level of the signal that has been correlated and sampled by the CDS circuit 104. The gain of the AGC amplifier 105 is set by the CPU 121 when setting data (control voltage) is set in the AGC amplifier 105 via a D / A converter built in the CPU 121. Further, the A / D converter 106 converts analog image data from the CCD 103 input via the AGC amplifier 105 into digital image data. That is, the output signal of the CCD 103 is converted into a digital signal through the CDS circuit 104 and the AGC amplifier 105 and by the A / D converter 106 at an optimum sampling frequency (for example, an integer multiple of the subcarrier frequency of the NTSC signal). Is done.

  Further, an IPP (Image Pre-Processor) 107, a DCT (Discrete Cosine Transform) 108, and a coder (Huffman Encoder / Decoder) 109, which are digital signal processing units, are digital image data input from the A / D converter 106. Various processing, correction, and data processing for image compression / decompression are performed separately for color differences (Cb, Cr) and luminance (Y). The IPP 107 also outputs timing signals such as a vertical synchronization signal (vd) and a horizontal synchronization signal (Hd) to the CPU 121. Note that an IPP (Image Pre-Processor) 107 uses the oscillation frequency of a crystal oscillator as an internal clock (operation frequency).

  Further, an MCC (Memory Card Controller) 110 temporarily stores the compressed image and records it on the PC card 150 or reads it from the PC card 150 via the PC card interface 112.

  The CPU 121 uses the RAM as a work area according to a program stored in the ROM, and controls all operations inside the digital camera according to an instruction from the operation unit 123 or an external operation instruction such as a remote controller (not shown). Specifically, the CPU 121 controls an imaging operation, strobe light emission operation, automatic exposure (AE) operation, automatic white balance (AWB) adjustment operation, AF operation, and the like. Note that the oscillation frequency of the ceramic oscillator is used as the internal clock (operation frequency) of the CPU 121.

  Camera power is input from a battery 128, such as NiCd, nickel metal hydride, or a lithium battery, to the DC-DC converter 129 and supplied into the digital camera.

  The display unit 122 is realized by an LCD, LED, EL, or the like, and displays captured digital image data, decompressed recorded image data, and the like. The operation unit 123 includes buttons for performing function selection, shooting instruction, and other various settings from the outside. In the EEPROM 130, adjustment data and the like used when the CPU 121 controls the operation of the digital camera are written. The strobe device 127 emits strobe light based on a control signal output from the CPU 121.

  The above-described digital camera 100 (CPU 121) includes a recording mode in which image data obtained by imaging a subject is recorded on the PC card 150, a display mode in which image data recorded on the PC card 150 is displayed, and captured image data. Is provided directly on the display unit 122.

  Next, the operation performed by the CPU 121 for determining the start timing of the control of the control target with reference to the vertical synchronization signal (vd) input from the IPP 107 will be described with reference to the strobe emission synchronization control as an example. FIG. 2 is a flowchart for explaining the process of measuring the period of the vertical synchronization signal (vd) executed by the CPU 121. FIG. 3 is a flowchart for explaining the calculation processing of the strobe light emission timing executed by the CPU 121.

  On the IPP 107 side, since an expensive crystal oscillator is used, the error of the oscillation frequency is reduced. On the other hand, since an inexpensive ceramic oscillator is used on the CPU 121 side, the error of the oscillation frequency is increased and the time accuracy is increased. Becomes worse. For this reason, an error occurs when the CPU 121 determines the start timing of control of the control target based on the vertical synchronization signal (vd) input from the IPP 107. Therefore, in the present embodiment, the CPU 121 measures the period of the vertical synchronization signal input from the IPP 107 based on the internal operating frequency (the oscillation frequency of the ceramic resonator), and uses the vertical synchronization signal (vd) as a reference. When the strobe light emission timing is determined, the strobe light emission timing is corrected based on the measured period of the vertical synchronization signal.

With reference to FIG. 2, the measurement process of the period of the vertical synchronizing signal (vd) executed by the CPU 121 will be described. First, variables used in the figure will be described.
tcnt1: Count value of timer (free run) in CPU vd_time: Period (vd time) of vertical synchronizing signal (vd) measured in units of timer count in CPU
vd_time1: variable for storing the count value of the timer for vd time measurement

In FIG. 2, when the CPU 121 is interrupted by the IPP 107 by vdHEAD (frame vertical synchronization signal) or vd (vertical synchronization signal), the CPU 121 sets the internal timer according to the internal operating frequency (the oscillation frequency of the ceramic resonator). The vd time (the period of the vertical synchronizing signal) is measured using (Step S100). Specifically, the measurement of the vd time is performed by calculation of itu1_tmp = tcnt1, vd_time = itu1_tmp−vd_time1, and vd_time1 = itu1_tmp. The measurement of the vd time is performed a plurality of times. Then, an average value of the vd times measured a plurality of times is calculated (step S101).

  Next, with reference to FIG. 3, a calculation process of the strobe light emission timing executed by the CPU 121 will be described. Table 1 below shows the standard value of the value of vd_time in the count unit of the timer. The contents shown in Table 1 below are converted into data and stored in the ROM.

  In FIG. 3, first, the CPU 121 determines NTSC / PAL (TV / LCD) (steps S200 and S204). Specifically, the measured vd_time is compared with each value in Table 1 above to determine which vd time is close to detect NTSC or PAL (TV / LCD).

  If the result of the above determination (steps S200 and S204) is NTSC, a vd time limit calculation is performed (step S201). Specifically, the range of the oscillation accuracy error (for example, ± 0.5%) of the ceramic oscillator having the values in Table 1 as vd_time is set as a limit range, and vd_time is set as a value within this range.

  Subsequently, the CPU 121 obtains a time from vd to strobe light emission, that is, a standard strobe light emission timing time (sy_start_time) from the shutter speed (step S201). Then, the standard strobe emission timing time (sy_start_time) is corrected and calculated with the measured vd time (vd_time) (step S203). Specifically, the correction strobe light emission timing time is calculated by calculating sy_start_time (correction strobe light emission timing time) = sy_start_time * vd_time (vd time) / 0x77da. Here, 0x77da is a vd time value measured by the CPU 121 with the oscillation accuracy (for example, ± 0%) of a standard ceramic oscillator. Further, the standard strobe light emission time is a value for a standard ceramic oscillator.

  The CPU 121 sets sy_start_time in the timer, starts the timer, and causes the flash device 127 to emit flash when the timer ends.

  On the other hand, if the result of the determination (steps S200 and S204) is PAL (TV), the CPU 121 performs a vd time limit calculation (step S205). Specifically, the range of the oscillation accuracy error (for example, ± 0.5%) of the ceramic oscillator having the values in Table 1 as vd_time is set as a limit range, and vd_time is set as a value within this range.

  Subsequently, the CPU 121 obtains a time from vd to strobe light emission, that is, a standard strobe light emission timing time (sy_start_time) from the shutter speed (step S206). Then, the standard strobe emission timing time (sy_start_time) is corrected and calculated with the measured vd time (vd_time) (step S207). Specifically, the corrected strobe light emission timing time is calculated by the following calculation: sy_start_time (corrected strobe light emission timing time) = sy_start_time * vd_time (vd time) / 0x8fd2. Here, 0x8fd2 is the vd time value of PAL (TV) measured by the CPU 121 with the oscillation accuracy (for example, ± 0%) of a standard ceramic oscillator. Then, the CPU 121 sets sy_start_time for the timer, starts the timer, and causes the strobe device 127 to emit light when the timer ends.

  If the result of the determination (steps S200 and S204) is PAL (LCD), the CPU 121 performs a vd time limit calculation (step S208). Specifically, the range of the oscillation accuracy error (for example, ± 0.5%) of the ceramic oscillator having the values in Table 1 as vd_time is set as a limit range, and vd_time is set as a value within this range.

  Subsequently, the CPU 121 obtains a time from vd to strobe light emission, that is, a standard strobe light emission timing time (sy_start_time) from the shutter speed (step S209). Then, the standard strobe emission timing time (sy_start_time) is corrected and calculated with the measured vd time (vd_time) (step S207). Specifically, the corrected strobe light emission timing time is calculated by the following calculation: sy_start_time (corrected strobe light emission timing time) = sy_start_time * vd_time (vd time) / 0x63d2. Here, 0x63d2 is the vd time value of the PAL (CCD) measured by the CPU 121 with the oscillation accuracy (for example, ± 0%) of a standard ceramic oscillator. Then, the CPU 121 sets sy_start_time for the timer, starts the timer, and causes the strobe device 127 to emit light when the timer ends.

  4A and 4B are timing charts showing strobe light emission timings. FIG. 4A shows the timing when the shutter speed is 1/250 seconds, and FIG. 4B shows the timing when the shutter speed is 1/8000 seconds. In the figure, (a) is a vertical synchronization signal (vd), (b) is a strobe light emission timing (sy), (c) is a charge accumulation reset (sub) of the strobe device 127, and (d) is an image capture (ch1). Indicates.

  As shown in FIG. 5A, the flash synchronization is good when the shutter speed is 1/250 seconds. On the other hand, as shown in FIG. 5B, when the shutter speed is 1/8000 sec, the strobe tuning is NG, and the strobe is emitted after ch1 (image capture) in sub (charge accumulation reset). . As the shutter speed increases, the length of time that the strobe light is emitted becomes a problem. It is desirable that the flash light emission is completed at the shutter speed = exposure time. Further, since it is desirable to start the flash emission after the last sub output as much as possible, the emission timing accuracy equal to or higher than the shutter speed is required.

  As described above, in the present embodiment, the CPU 121 measures the period (vd time) of the vertical synchronization signal input from the IPP 107 based on the internal operating frequency, and determines the vertical synchronization signal (vd). When the strobe light emission timing is determined based on the reference, the strobe light emission timing is corrected based on the measured period (vd time) of the vertical synchronization signal. For example, the IPP 107 uses a crystal oscillator. Even when the CPU 121 uses a ceramic oscillator, it is possible to prevent the occurrence of an error in the strobe light emission timing, and it is possible to perform strobe tuning even at the time of high-speed shutter. That is, according to the present embodiment, the accuracy of the oscillator of the CPU 121 can be corrected in software.

  In the present embodiment, since a limiter is provided in the measured period (vd time) of the vertical synchronizing signal, it is possible to cope with an erroneous measurement of the period (vd time) of the vertical synchronizing signal. It becomes. In addition, the ceramic oscillator used in the CPU 121 has an error of about ± 1% even if the oscillation frequency accuracy is poor. Therefore, the correction range may be ± 1%, and the error is more than that. This is because there is a high possibility of erroneous measurement of the period (vd time) of the vertical synchronization signal.

  In the present embodiment, the period (vd time) of the vertical synchronization signal is measured a plurality of times, and the average value of the plurality of times is set as the measurement value of the period (vd time) of the vertical synchronization signal. The influence of measurement error can be reduced.

  In this embodiment, after determining whether the vertical synchronization signal input from the IPP 107 is the NTSC system or the PAL system, it is determined whether the time of the measured vertical synchronization signal is within the limiter. As a result, the period (vd time) of the time vertical synchronization signal can be accurately detected.

  In the above-described embodiment, the crystal oscillator is used in the IPP 107 and the ceramic oscillator is used in the CPU 121. However, the oscillator is not limited to this, and the signal input side has an internal operating frequency. All are applicable when the accuracy of the oscillating oscillator is poor. Further, the present invention is not limited to the case of correcting the difference due to the accuracy of the oscillator, but can be applied to the case of correcting a difference in environmental accuracy, for example, a difference in accuracy in temperature and voltage characteristics.

  In the present embodiment, the case where the vertical synchronization signal (vd) of the IPP 107 is used has been described. However, the present invention can be applied not only to the vertical synchronization signal (vd) but also to other operating frequency signals.

  The timing control device and timing control method according to the present invention can be widely used when correcting the control timing, and is useful for various devices such as a digital camera.

It is a block diagram of the digital camera which concerns on this Embodiment. It is a flowchart for demonstrating the measurement process of the period of the vertical synchronizing signal (vd) performed by CPU. It is a flowchart for demonstrating the calculation process of the flash light emission timing performed by CPU. It is a timing chart which shows strobe light emission timing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Digital camera 101 Lens system 101a Focus lens system 101b Zoom lens system 102 Mechanical mechanism including autofocus 103 CCD (charge coupled device)
104 CDS (Correlated Double Sampling) Circuit 105 Variable Gain Amplifier (AGC Amplifier)
106 A / D converter 107 IPP (Image Pre-Processor)
108 DCT (Discrete Course Transform)
109 Coder (Huffman Encoder / Decoder)
110 MCC (Memory Card Controller)
111 RAM (internal memory)
112 PC card interface 121 CPU
122 Display Unit 123 Operation Unit 126 SG Unit 127 Strobe 128 Battery 129 DC-DC Converter 130 EEPROM
131 Focus Driver 132 Pulse Motor 133 Zoom Driver 134 Pulse Motor 135 Motor Driver 150 PC Card

Claims (5)

A first oscillation element;
A second oscillation element;
First signal generating means for outputting a first signal having a predetermined period based on the oscillation frequency of the first oscillation element;
Period measuring means for measuring the period of the first signal by counting based on the oscillation frequency of the second oscillation element;
Control timing determining means for determining a control timing based on the oscillation frequency of the second oscillation element;
Correction for correcting the control timing determined by the control timing determination means based on the theoretical value when the period of the first signal is measured at the oscillation frequency of the second oscillation element and the count value by the period measurement means Means,
A timing control device comprising:   The timing control apparatus according to claim 1, wherein the correction by the correction unit is performed within an error range of the second oscillation element.   2. The timing control device according to claim 1, wherein the period measuring unit measures the period of the first signal a plurality of times, and uses the average value of the plurality of times as a count value of the period.   2. The timing control apparatus according to claim 1, wherein at least one of the first oscillation element and the second oscillation element oscillates a reference frequency of a central processing unit that controls the apparatus. A first signal generation step of outputting a first signal having a predetermined period based on the oscillation frequency of the first oscillation element;
A period measuring step of measuring the period of the first signal by counting based on the oscillation frequency of the second oscillation element;
A control timing determination step for determining a control timing based on the oscillation frequency of the second oscillation element;
Correction for correcting the control timing determined by the control timing determination step based on the theoretical value when the cycle of the first signal is measured at the oscillation frequency of the second oscillation element and the count value obtained by the cycle measurement step Process,
Including a timing control method.

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