JP4237008B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device. Furthermore, it is preferably effective as a method for manufacturing a semiconductor device in which metal wiring is formed on a porous low dielectric constant insulating film.
[0002]
[Prior art]
In recent years, with high integration and miniaturization of semiconductor devices, it is particularly necessary to reduce RC delay. For this reason, it is considered that a material having a low specific resistivity is used as the wiring material and a low dielectric constant (low-k) insulating film having a low dielectric constant is used as the insulating film material.
[0003]
As a low dielectric constant (Low-k) insulating film, an insulating film having a relative dielectric constant k <3.0 is being researched. Examples of such a low dielectric constant insulating film include poly-siloxane, HSQ (hydrogen-silsesquioxane), poly-methyl-siloxane, and MSQ (methyl silsesquioxane). Among them, in recent years, poly-methyl-siloxane, MSQ, etc., which are highly resistant to heat treatment and processing, are widely used.
[0004]
In addition, the use of a low dielectric constant porous film having a relative dielectric constant <2.5 is also being studied. The low dielectric constant porous film has pores of several to several tens of squares in the low dielectric constant film as described above.
[0005]
On the other hand, with the miniaturization of semiconductor devices, there is an increasing demand for miniaturization of metal wiring. For this reason, there is a similar demand for miniaturization of via holes or contact holes formed in insulating films for forming metal wiring. Is growing. In addition, when a fine hole is formed in the insulating film, a technique for performing a heat treatment after forming the insulating film hole, such as thermosetting, is also proposed, for example, to suppress generation of Pois vias, which adversely affects the subsequent wiring process. (For example, refer to Patent Document 1).
[0006]
[Patent Document 1]
JP-A-2002-83809 [0007]
[Problems to be solved by the invention]
However, the low dielectric constant porous film has low mechanical strength because it has pores in the film. For this reason, the damage in the process of forming the opening and the wiring process is large, and in particular, the damage due to the plasma process and the chemical process in the process such as etching and ashing which are diversified with miniaturization is large. If the porous film having a low dielectric constant is damaged, it causes a problem of RC delay due to an increase in wiring capacitance and an increase in leakage current.
[0008]
Accordingly, the present invention provides a method for manufacturing a semiconductor device that solves the above-described problems, recovers damage of a low dielectric constant porous film, and suppresses an increase in wiring capacitance and an increase in leakage current. .
[0009]
[Means for Solving the Problems]
Therefore, the manufacturing method of the semiconductor device in this invention is as follows:
Forming a first diffusion barrier film on the lower substrate, and forming a low dielectric constant porous film on the first diffusion barrier film;
A mask forming step of forming a mask having a predetermined pattern formed on the low dielectric constant porous film;
Forming a first opening reaching the first diffusion prevention film in the low dielectric constant porous film through the mask;
Forming a second opening connected to the first opening in the first diffusion preventing film after forming the first opening;
Forming a copper-containing wiring in the first opening and the second opening,
A first heat treatment step of performing a heat treatment at 250 ° C. to 350 ° C. after the step of forming the first opening and before the step of forming the second opening ;
A second heat treatment step of performing a heat treatment at 250 ° C. to 350 ° C. after the step of forming the second opening and before the step of forming the copper-containing wiring;
Is provided.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is omitted or simplified.
[0015]
Embodiment 1 FIG.
FIG. 1 is a schematic sectional view for illustrating a semiconductor device 100 according to the first embodiment of the present invention. FIG. 2 is a graph comparing the in-plane distribution of wiring capacitance between the semiconductor device 100 according to the first embodiment of the present invention and the conventional semiconductor device.
[0016]
As shown in FIG. 1, in a semiconductor device 100, an STI (Shallow Trench Isolation) 4 is formed on a Si substrate 2. A diffusion layer 6 is formed in the active region separated by the STI 4 of the Si substrate 2. A gate insulating film 8 is formed on the portion of the Si substrate 2 sandwiched between the diffusion layers 6, and a gate electrode 10 is formed on the gate insulating film 8. A side wall 12 is formed on the side wall of the gate electrode 10.
[0017]
An insulating film 20 is formed on the Si substrate 2 so as to embed the gate insulating film 8, the gate electrode 10, and the sidewalls 12. The insulating film 20 is formed on the diffusion layer 6 from the surface thereof. Up to this point, the tungsten plug 22 formed through the insulating film 20 is formed.
[0018]
An SiC film 30 having a thickness of about 50 nm is formed on the insulating film 20, and a low dielectric constant porous film 32 is formed on the SiC film 30. Here, the relative dielectric constant k of the low dielectric constant porous film 32 is k = 2.2, and the film thickness is about 200 nm. Further, an SiO ₂ cap film 34 is formed on the low dielectric constant porous film 32. The film thickness of the SiO ₂ cap film is about 100 nm.
[0019]
A hole 36 is formed so as to penetrate the SiC film 30, the low dielectric constant porous film 32, and the SiO ₂ cap film 34 thus laminated to reach the surface of the insulating film 20. Further, a contact hole 38 that connects to the hole 36 and penetrates the insulating film 20 to reach the diffusion layer 6 is formed. The minimum space of the holes 36 and 38 is both about 0.16 um.
[0020]
A TaN film 40 and a Ta film 42 are formed in this order along the inner walls of the holes 36 and 38. The film thicknesses are about 10 nm and about 15 nm, respectively. Further, Cu 44 is embedded on the Ta film 42 inside the holes 36 and 38. Thus, the Cu wiring, and the contact plugs for connecting the expansion goldenrod 6 is constructed. On the SiO ₂ cap film 34, a SiC film having a thickness of 50 nm is formed as a diffusion preventing film.
[0021]
The semiconductor device 100 configured as described above is similar to the structure of a conventional semiconductor device. However, as shown in FIG. 2, the wiring capacity of the semiconductor device 100 according to the first embodiment is about 7% to 10% smaller than the wiring capacity of the conventional semiconductor device. This is because the low dielectric constant porous film 32 used in the semiconductor device 100 has recovered to some extent damage received when forming the holes 36 and contact holes 38 of the semiconductor device 100 and embedding Cu 44. Because there is.
[0022]
Specifically, dry etching is used to open the hole 36 in the low dielectric constant porous film 32. This dry etching is performed in a plasma atmosphere. Further, when the contact hole 38 is formed in the insulating film 20, dry etching is performed in a plasma atmosphere, and a chemical solution is used for removing the residue after the etching. At this time, the low dielectric constant porous film 32 is damaged by plasma treatment or chemical treatment. Further, when a Ta film or the like is formed in the hole 36 and the contact hole 38, a sputtering method is used. However, the low dielectric constant porous film 32 is damaged by the plasma treatment before sputtering and the sputtering. Further, when the SiC film 50 is formed, the low dielectric constant porous film 32 is damaged because the treatment is performed in the plasma atmosphere. In the first embodiment, as described above, the damage given to the low dielectric constant porous film 32 in each processing step is appropriately recovered by performing a heat treatment at about 250 ° C. to 350 ° C. Therefore, the low dielectric constant porous film 32 of the semiconductor device 100 according to the first embodiment is less damaged than the conventional low dielectric constant porous film.
[0023]
FIG. 3 is a flowchart for illustrating the method for manufacturing semiconductor device 100 in the first embodiment of the present invention. 4 to 9 are schematic cross-sectional views for explaining states in each manufacturing process of the semiconductor device 100 of the present invention.
Hereinafter, the method for manufacturing the semiconductor device 100 according to the first embodiment of the present invention will be described in detail with reference to FIGS.
[0024]
First, as shown in FIG. 4, the SiC film 30 is formed on the insulating film 20 on which the tungsten plug 22 connected to the diffusion layer 6 of the Si substrate 2 is formed (step S102). The thickness of the SiC film deposited here is about 50 nm. Next, the low dielectric constant porous film 32 is formed on the SiC film 30 (step S104). The low dielectric constant porous film 32 is formed by an SOD (Spin-on Dielectrics) method. The low dielectric constant porous film 32 used here has a relative dielectric constant k = 2.2, and the thickness of the deposited low dielectric constant porous film is 200 nm.
[0025]
Next, the SiO ₂ cap film 34 is formed on the low dielectric constant porous film 32 (step S106). The SiO ₂ cap film 34 is used as a cap film for CMP, and is formed so as to have a film thickness of 100 nm here. Further, the SiC film 50 is formed on the SiO ₂ cap film 34 (step S108). The SiC film 50 is used as a hard mask, and is formed so as to have a film thickness of 50 nm here. Here, the SiO ₂ cap film 34 and the SiC film 50 are respectively formed by a CVD (Chemical Vapor Deposition) method.
[0026]
Next, as shown in FIG. 5, a hard mask is formed using the SiC film 50 as a material film. Here, first, a resist mask 52 is formed on the SiC film 50 (step S110). In this case, a resist mask is formed by applying a resist on the SiC film 50 and performing exposure and development processes in the same manner as in a normal process. Next, using the resist mask 52 as a mask, the SiC film 50 is etched by dry etching and processed into a hard mask (step S112). Thereafter, the resist mask 52 is removed by ashing using O ₂ gas and chemical cleaning (step S114). Note that dry etching and ashing performed when the hard mask is formed are performed in a plasma atmosphere, and then chemical cleaning is performed. In this plasma processing and chemical cleaning, the low dielectric constant porous film 32 is in a state of being somewhat damaged.
[0027]
Next, as shown in FIG. 6, the SiO ₂ cap film 34 and the low dielectric constant porous film 32 are etched (step S116). Here, etching is sequentially performed by dry etching using the SiC film 50 as a hard mask. In this way, holes 36 are formed in the SiO ₂ cap film 34 and the low dielectric constant porous film 32. Note that, also in the dry etching here, since the plasma treatment is performed, the low dielectric constant porous film 32 is further damaged.
[0028]
Next, annealing for damage recovery is performed (step S118). Here, heat treatment at 250 ° C. to 350 ° C. is performed for about 30 minutes in a N ₂ atmosphere by furnace annealing. As a result, F taken in the low dielectric constant porous film 32 during etching can be removed, and damage received by the low dielectric constant porous film 32 can be recovered.
[0029]
Next, as shown in FIG. 7, a contact hole 38 is formed in the insulating film 20 (step S120). Here, the insulating film 20 is etched, and then chemical cleaning is performed to remove the residue. At this time, the SiC films 50 and 30 exposed on the SiO ₂ cap film 34 and the bottom of the hole 36 are also removed. At this time, the low dielectric constant porous film 32 becomes damaged again by plasma treatment or chemical treatment.
[0030]
Thereafter, annealing for damage recovery is performed again (step S122). Here, heat treatment at 250 ° C. to 350 ° C. is performed for about 30 minutes in a N ₂ / H ₂ mixed gas atmosphere by furnace annealing. As a result, F taken in the low dielectric constant porous film 32 during etching of the contact hole 38 can be removed, and damage received by the low dielectric constant porous film 32 can be recovered.
[0031]
Next, as shown in FIGS. 8 and 9, Cu wiring is formed.
Here, as shown in FIG. 8, first, after pre-cleaning with H ₂ / He plasma (step S124), a TaN film 40 is formed on the inner wall of the hole 36 and the contact hole 38 to a thickness of 10 nm. (Step S126), and a Ta film 42 is formed thereon with a thickness of 15 nm (Step S128). Further, a Cu seed film 54 is formed with a film thickness of 65 nm on the Ta film 42 (step S130). Here, the TaN film 40, the Ta film 42, and the Cu seed film 54 are each formed by sputtering.
[0032]
Thereafter, as shown in FIG. 9, Cu 44 is embedded in the hole 36 and the contact hole 38 (step S132). At this time, the electroplating method is used with the Cu seed film 54 as a seed film. Next, furnace annealing at 350 ° C. is performed (step S134), and then CMP is performed (step S136). As a result, Cu, TaN, and Ta deposited on the surface of the SiC film 50 are removed, and the Cu 44, Ta film 42, and TaN film 40 remain only in the hole 36 and the contact hole 38, and Cu in the holes 36 and 38. A wiring is formed.
[0033]
Next, the SiC film 46 is formed (step S138). The SiC film 46 is a diffusion preventing film, and is formed here by CVD so that the film thickness becomes 50 nm.
[0034]
Thereafter, in order to recover the damage received by the porous insulation by the H ₂ / He plasma treatment before sputtering, a heat treatment at about 250 ° C. to 350 ° C. is performed for 30 minutes by furnace annealing (step S140). In this way, the semiconductor device 100 as shown in FIG. 1 can be obtained. When the semiconductor device 100 obtained here was inspected, the wiring capacity was recovered by 7% to 10%, and the leakage current was improved by about one digit.
[0035]
Thereafter, similarly, annealing is performed as necessary, and necessary via formation, metal wiring formation, and the like are performed while recovering damage received by the low dielectric constant porous film 32 in plasma treatment or chemical treatment. A wiring layer is formed.
[0036]
As described above, according to the first embodiment, etching and ashing in the plasma atmosphere when forming the hole 36 and the contact hole 38, chemical treatment, etc., and in the plasma atmosphere when forming the Cu wiring are performed. In the pre-cleaning, the damage to the low dielectric constant porous film 32 is recovered by annealing at about 250 to 350 ° C. each time. Thereby, F or the like taken into the low dielectric constant porous film 32 during etching can be removed. Thereby, in the semiconductor device 100, an increase in wiring capacitance and an increase in leakage current can be suppressed.
[0037]
Here, a relatively low temperature heat treatment of about 250 ° C. to 350 ° C. is applied. For this reason, even if heat treatment is performed after the Cu wiring is formed, Cu aggregation and the like can be suppressed, so that a highly reliable semiconductor device can be obtained.
[0038]
Further, in the first embodiment, the case where annealing for damage recovery is performed after the formation of the hole 36, after the formation of the contact hole 38, and after the Cu 44 is filled has been described. In this way, by recovering damage each time, damage recovery can be achieved more reliably. However, in the present invention, the annealing may be performed selectively once or when necessary. For example, even with a single annealing, a certain amount of damage recovery effect can be obtained. Further, the timing for performing the annealing for recovering each damage is not limited to that described in the first embodiment. For example, in the first embodiment, the case where the damage recovery in the pre-cleaning is performed after the SiC film 46 is formed has been described. However, this annealing is finally performed after the pre-cleaning and before the formation of the pad and the passivation. If it is.
[0039]
In the first embodiment, the case where the damage recovery annealing is performed in an N ₂ gas atmosphere or a mixed gas of N ₂ and H ₂ has been described. However, in the present invention, the heat treatment is not limited to the case where the heat treatment is performed in these gases. For example, it may be performed in the atmosphere, an atmosphere of H ₂ gas, or Ar gas.
[0040]
Moreover, in Embodiment 1, the case where Cu wiring was formed in the low dielectric constant porous film 32 by the dual damascene method was demonstrated. However, the present invention is not limited to this, and when a low dielectric constant porous film is used, damage to the low dielectric constant porous film such as etching, ashing, etc. in a plasma atmosphere, chemical treatment, etc. The present invention can be applied to various cases in which the process of giving is performed.
[0041]
In the present invention, the low dielectric constant porous film 32 means a low dielectric constant film having pores of several to several tens of thousands in the film.
Examples of the low dielectric constant film include poly-siloxane, HSQ (hydrogen-silsesquioxane), poly-methyl-siloxane, and MSQ (methyl silsesquioxane), but the present invention is not necessarily limited thereto.
In the present invention, the thickness of each film, the material of the film, the formation method thereof, and the like are not limited to those described in the first embodiment.
[0042]
Embodiment 2. FIG.
FIG. 10 is a flow diagram for illustrating the method for manufacturing a semiconductor device in the second embodiment of the present invention. FIG. 11 is a schematic cross-sectional view for explaining a state in the manufacturing process of the semiconductor device according to the second embodiment.
The semiconductor device described in the second embodiment is similar in structure to the semiconductor device 100 described in the first embodiment.
[0043]
Further, the manufacturing method of the semiconductor device in the second embodiment is similar to the manufacturing method described in the first embodiment. However, in the first embodiment, the low dielectric constant porous film 32 is etched using the SiC film 50 as a hard mask, whereas in the second embodiment, the low dielectric constant porous film 32 is formed using the resist mask 52. Etching 32 is performed.
Hereinafter, the manufacturing method of the semiconductor device according to the second embodiment will be described in detail with reference to FIGS.
[0044]
First, as in steps S102 to S110 of the first embodiment, the SiC film 30, the low dielectric constant porous film 32, the SiO ₂ cap film 34, and the SiC film 50 are formed on the insulating film 20 on which the tungsten plug 22 is formed. Then, the resist mask 52 is formed as shown in FIG. 11 (steps S202 to S210).
[0045]
Next, in the second embodiment, the SiC film 50, the SiO ₂ cap film 34, and the low dielectric constant porous film 32 are etched by dry etching using the resist mask 52 as a mask (step S212).
[0046]
Next, the resist mask 52 is removed (step S214). Here, the resist mask 52 is peeled off by ashing using a mixed gas of H ₂ / He and chemical cleaning. Here, in the first embodiment, after etching using the SiC film 50 as a hard mask, the resist is peeled off, and then the low dielectric constant porous film 32 and the like are etched. In this state, the low dielectric constant porous film 32 is damaged.
[0047]
Next, similarly to step S116 of the first embodiment, annealing at 250 ° C. to 350 ° C. is performed for 30 minutes in an N ₂ atmosphere to recover the damage of the low dielectric constant porous film 32 (step S216).
Subsequent processes are performed in the same manner as steps S118 to S140 of the first embodiment, whereby a semiconductor device similar to the semiconductor device 100 as shown in FIG. 1 can be obtained. When the semiconductor device obtained here was inspected, the wiring capacity was recovered by about 10%, and the leakage current was improved by about one digit.
[0048]
As described above, even with the second embodiment, it is possible to recover the damage of the low dielectric constant porous film 32 and obtain a semiconductor device in which the increase in wiring capacitance and leakage current is suppressed.
[0049]
In the first embodiment, the low dielectric constant porous film 32 is covered with the SiO ₂ cap film 34 and is not exposed on the surface at the time of ashing at the time of resist peeling. Relatively small. However, in the second embodiment, the resist is peeled after the holes 36 are opened by etching. For this reason, the low dielectric constant porous film 32 is exposed on the inner wall of the hole 36 during ashing. Therefore, at the time of ashing, the low dielectric constant porous film 32 is in direct contact with the ashing gas at the inner wall portion of the hole 36, and thus is more easily damaged. However, here, by using H ₂ / He, a certain amount of damage can be suppressed as compared with normal ashing, and the damage is greatly recovered by subsequent annealing.
Since other parts are the same as those of the first embodiment, the description thereof is omitted.
[0050]
For example, the low dielectric constant porous film forming process of the present invention is performed by executing steps S104 and S204 of the first and second embodiments, and the mask formation is performed by executing steps S110 to S112 and S210. A process is performed and an etching process is performed by performing step S116, S212.
[0051]
Further, for example, in the first embodiment, by executing steps S108, S110, S112, and S114, a hard mask material film forming step, a resist mask forming step, a hard mask etching step, and a resist mask removing step are executed, respectively. The In the second embodiment, the resist mask removing process of the present invention is executed by executing step S212.
[0052]
Further, for example, in the first and second embodiments, the first opening forming step of the present invention is executed by executing steps S116 and S212, and the second opening forming is executed by executing steps S120 and S218. A process and a residue removal process are performed.
[0053]
Also, for example, in the first and second embodiments, the metal wiring forming process of the present invention is executed by executing S124 to S134 and S222 to S232, and the diffusion preventing film is executed by executing steps S138 and S236. A forming step is performed.
[0054]
Further, for example, in the first and second embodiments, the heat treatment process of the present invention is performed by executing S118, S122, S140, S216, S220, and S238.
[0055]
In the present invention, for example, the hard mask material film corresponds to the SiC film 50 in the first embodiment, the first opening corresponds to the hole 36 in the first and second embodiments, and the second A contact hole 38 corresponds to the opening.
[0056]
【The invention's effect】
As described above, according to the present invention, after performing plasma processing such as etching or ashing or chemical processing, annealing is performed by applying a heat treatment at about 250 ° C. to 350 ° C. Therefore, the damage which the low dielectric constant porous film received in the plasma treatment or the chemical treatment can be recovered to some extent. Thereby, it is possible to obtain a semiconductor device in which increases in wiring capacitance and leakage current are suppressed.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view for illustrating a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a graph comparing the in-plane distribution of wiring capacitance between the semiconductor device according to the first embodiment of the present invention and a conventional semiconductor device.
FIG. 3 is a flowchart for illustrating the method for manufacturing the semiconductor device in the first embodiment of the present invention.
FIG. 4 is a schematic cross sectional view for illustrating a state in the manufacturing process of the semiconductor device in the first embodiment of the present invention.
FIG. 5 is a schematic cross sectional view for illustrating a state in the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
6 is a schematic cross sectional view for illustrating a state in the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG.
FIG. 7 is a schematic cross sectional view for illustrating the state in the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
FIG. 8 is a schematic cross sectional view for illustrating a state in the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
FIG. 9 is a schematic cross sectional view for illustrating the state in the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
FIG. 10 is a flowchart for illustrating the method for manufacturing the semiconductor device in the second embodiment of the present invention.
FIG. 11 is a schematic cross sectional view for illustrating a state in the manufacturing process of the semiconductor device in the second embodiment of the present invention.
[Explanation of symbols]
100 Semiconductor device 2 Si substrate 4 STI
6 Diffusion layer 8 Gate insulating film 10 Gate electrode 12 Side wall 20 Insulating film 22 Tungsten plug 30 SiC film 32 Low dielectric constant porous film 34 SiO ₂ cap film 36 Hole 38 Contact hole 40 TaN film 42 Ta film 44 Cu
46 SiC film

Claims (7)

Forming a first diffusion barrier film on the lower substrate, and forming a low dielectric constant porous film on the first diffusion barrier film;
A mask forming step of forming a mask having a predetermined pattern formed on the low dielectric constant porous film;
Forming a first opening reaching the first diffusion prevention film in the low dielectric constant porous film through the mask;
Forming a second opening connected to the first opening in the first diffusion preventing film after forming the first opening;
Forming a copper-containing wiring in the first opening and the second opening,
A first heat treatment step of performing a heat treatment at 250 ° C. to 350 ° C. after the step of forming the first opening and before the step of forming the second opening ;
And a second heat treatment step of performing a heat treatment at 250 ° C. to 350 ° C. after the step of forming the second opening and before the step of forming the copper-containing wiring. A method for manufacturing a semiconductor device. The mask forming step includes
A hard mask material film forming step of forming a hard mask material film on the low dielectric constant porous film;
A resist mask forming step of forming a resist mask having a predetermined pattern formed on the hard mask material film;
Using the resist mask as a mask, a hard mask etching step for etching the hard mask material film,
A resist mask removing step for removing the resist mask;
The method of manufacturing a semiconductor device according to claim 1, comprising: The mask is a resist mask;
The method for manufacturing the semiconductor device further includes:
After the step of forming the first opening and before the first heat treatment step,
The method for manufacturing a semiconductor device according to claim 1, further comprising a resist mask removing step of removing the resist mask. The resist mask removing step, and H _2, by ashing in an atmosphere of plasma gas using a mixed gas of He, The semiconductor device according to claim 3, characterized in that the removal of the resist mask Manufacturing method. 5. The method of manufacturing a semiconductor device according to claim 1, further comprising a third heat treatment step of performing a heat treatment at 250 ° C. to 350 ° C. after the step of forming the copper-containing wiring. Further comprising forming a second diffusion barrier film on at least the copper-containing wiring,
The method of manufacturing a semiconductor device according to claim 5, wherein the third heat treatment step is performed after the step of forming the second diffusion barrier film. The heat treatment step is N ₂ And H ₂ Mixed gas or in the atmosphere or N ₂ Gas or H ₂ 7. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed in an atmosphere of gas or Ar gas.

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