JP4237229B2 - In-vehicle engine controller - Google Patents

Description

  The present invention relates to an in-vehicle engine control device to which an immobilizer for performing authentication verification of a start key of an in-vehicle engine is connected, and particularly relates to a novel improved technique for improving the authentication verification accuracy of a start key with an inexpensive configuration. Is.

  Conventionally, the personal identification number provided on the start key is wirelessly transmitted to the immobilizer via the transponder provided on the start key, and collated with the correct personal identification number stored in the immobilizer or in-vehicle engine control device. Systems that prevent engine start by an unauthorized start key have been widely put into practical use.

  As a conventional vehicle-mounted engine control device, a known immobilizer and an authentication method using an immobilizer can be given (for example, see Patent Document 1). According to the authentication control method described in Patent Document 1, when the unique information (password) of the start key is wirelessly transmitted to the immobilizer via the transponder, the immobilizer performs an authentication match determination, and A start permission signal is provided, and in particular, the authentication accuracy is improved by encrypting the password using a random number based on the previous engine start time information.

  Other conventional devices include a system having a macro cell in an integrated microprocessor and a macro cell control method in the integrated microprocessor (see, for example, Patent Document 2). Patent Document 2 discloses a technique related to a counter / timer macro cell applicable to an in-vehicle engine control device.

JP 2001-012123 (FIG. 1, abstract) Japanese Patent Laid-Open No. 09-259102 (FIG. 1, abstract)

  In the conventional vehicle engine control device, for example, in the technology described in Patent Document 1, although the authentication accuracy is improved by using the encryption technology together, the wireless signal transmitted and received between the immobilizer and the transponder is referred to. However, there is a problem that the accuracy of authentication verification for the start key cannot be improved with an inexpensive configuration.

  Further, in the technique described in Patent Document 2, although an operation mode setting unit for applying the counter / timer to various uses is disclosed, the specific use of the counter / timer module is not mentioned. There is still a problem that the authentication verification accuracy for the start key cannot be improved with an inexpensive configuration.

  The present invention relates to an in-vehicle engine capable of improving authentication verification accuracy with respect to a start key with an inexpensive configuration when used in combination with drive control means for engine drive equipment comprising at least one of a fuel injection solenoid valve and an ignition coil. The object is to obtain a control device.

The in-vehicle engine control apparatus according to the present invention is
For driving an engine that is connected to various sensors including a crank angle sensor for detecting the operating state of an in-vehicle engine, powered by an in-vehicle battery, and comprising at least one of a fuel injection solenoid valve and an ignition coil according to the operating state Drive control means for controlling the device;
A program memory storing a control program to be an authentication verification means for the engine start key, and a microprocessor cooperating with the program memory;
An in-vehicle engine control device connected to an immobilizer for reading out a personal identification number of the start key with a radio signal via a transponder provided in the start key,
The microprocessor cooperates with a plurality of timer circuit units and timer output units,
The program memory includes a control program serving as an operation time setting unit and a timer output switching unit for the timer circuit unit,
The timer circuit unit generates a comparison coincidence output when the time counter that counts the clock signal for timing, the set value register, and the current count value of the time counter reaches the target set value stored in the set value register. Consists of a comparison circuit that drives the timer output unit,
The timer output unit generates a logic output corresponding to a predetermined ON time and OFF time that are variably set in the set value register by the microprocessor.
The operation time setting means transfers and stores ON time data and OFF time data corresponding to the ON time and OFF time, or ON / OFF total time data and ON time data or OFF time data to the set value register, At the start of timing, the current count value is reset,
The authentication verification means reads the start key code number via the immobilizer with a radio signal having a frequency and amplitude corresponding to the period and duty of the pulse width modulation signal transmitted from the microprocessor, and the read code number is Authenticate whether or not it matches the correct password stored in the program memory or immobilizer in advance.
The pulse width modulation signal is generated by a timer circuit unit, an operation time setting unit, and a timer output unit, and is composed of a continuous pulse signal having a predetermined OFF time and ON time,
The timer output switching means generates a timer output switching command signal when the authentication determination is a coincidence determination, and switches and uses the timer circuit unit used for generating the pulse width modulation signal as a drive control timer. ,
The drive control timer includes a timer circuit unit, an operation time setting unit, and a timer output unit. The timer circuit unit starts operating in synchronization with the detection signal of the crank angle sensor and corresponds to the set OFF time. After the set time elapses, the first comparison match output is generated, and after the second set time corresponding to the set ON time elapses, the next comparison match output is generated, and the timer output unit has generated the first match output. Timer output is generated during the period until the next comparison match output occurs,
The engine driving device is driven by the timer output from the timer output unit,
One of the plurality of timer circuit units is selectively used in the authentication verification unit and the drive control unit, and to the drive control unit until a coincidence determination is obtained as a result of the authentication verification by the authentication verification unit. Is not switched, and output generation of the drive control means is prohibited.

According to the present invention, the pulse width modulation signal is used to perform authentication verification of the start key, and the pulse width modulation signal is generated also as a timer circuit unit for performing engine ignition control or fuel injection control. The engine drive control output is not generated until the authentication verification is completed. Therefore, it is possible to generate a pulse width modulation signal at a low cost without increasing the number of timer circuit portions used in combination with the microprocessor, and to perform advanced authentication verification.
Moreover, until the authentication verification is normally completed, unnecessary discharge of the vehicle-mounted battery to the engine driving device can be suppressed, and the starting characteristics at low voltage / cold temperature can be improved.

Embodiment 1 FIG.
Hereinafter, an in-vehicle engine control apparatus 100A according to Embodiment 1 of the present invention will be described with reference to the circuit block diagram of FIG.
In FIG. 1, an in-vehicle battery 101 is connected to an in-vehicle engine control device 100A through an output contact 102a of a power relay (described later with reference to FIG. 6), and a power switch 103a and a start switch 103b are connected. The in-vehicle sensor group 105 and the electric load group 106 are connected.

  As shown in FIG. 6 (described later), the power switch 103a and the start switch 103b open and close in association with the rotational position of the start key 103 of the engine (not shown), and the power switch 103a The key 103 is closed from the first rotation position to the third rotation position, and the start switch 103 b is closed at the third rotation position of the start key 103.

  The starter key 103 is integrated with a transponder 104a for transmitting a personal identification number added to the starter key 103. The transponder 104a is connected to an immobilizer 104b built in the key switch body 104. Wireless communication with. The immobilizer 104b is connected to the in-vehicle engine control apparatus 100A via the data communication line 12A, reads the password number added to the start key 103, and inputs it to the microprocessor 110 in the in-vehicle engine control apparatus 100A.

  The in-vehicle sensor group 105 includes a crank angle sensor 105a, and an operating state of the engine such as a shift stage selection switch of a transmission (not shown), an exhaust gas sensor, an accelerator position sensor, a throttle position sensor, an air flow sensor, an exhaust gas sensor, and a water temperature sensor. Including various sensors for monitoring.

  The electric load group 106 includes an unillustrated intake throttle valve opening motor, a fuel injection solenoid valve for selecting a transmission gear stage, an exhaust circulation valve drive motor, an exhaust gas sensor temperature control electric heater, and the like. Includes various electrical loads related to engine drive control. Of the electric load group 106, the fuel injection solenoid valve (injector INJ) or the ignition coil (ignition coil IGC) is shown as an engine driving device 161A.

  The engine driving device 161A is driven via the amplification output circuit 160 by the in-vehicle engine control device 100A. Here, the engine driving device 161A includes four engine driving devices 161a to 161d corresponding to ignition coils or fuel injection solenoid valves for a four-cylinder four-cycle engine. Each engine driving device 161a to 161d circulates in the order of 161a → 161b → 161c → 161d → 161a →..., And the engine rotates twice during this time.

  The microprocessor 110 constituting the main part of the in-vehicle engine control apparatus 100A includes a RAM memory 111 for arithmetic processing, a program memory 112A (for example, a non-volatile flash memory), and timer circuit units 300ac, 300bd, and 300rv. . The in-vehicle sensor group 105 is connected to the microprocessor 110 via the input interface 125, and the electric load group 106 is connected via the output interface 126. Further, detection signals of analog sensors included in the in-vehicle sensor group 105 are input to the microprocessor 110 via a multi-channel AD converter (not shown).

  The program memory 112A in the microprocessor 110 stores input / output control programs related to the in-vehicle sensor group 105 and the electric load group 106, and supplies a drive control command to the engine drive device 161A by the drive control timers TIM1 and TIM2. And a control program for storing data.

  The cylinder selection gate circuits 116a to 116d connected to the microprocessor 110 are composed of AND elements of three input terminals inserted in the input part of the amplification output circuit 160 for driving the engine driving devices 161a to 161d. A timer output switching command signal INHB is input to the first input terminal of each AND element.

  The output signal of the drive control timer TIM1 is input to the second input terminals of the cylinder selection gate circuits 116a and 116c, and the drive control is applied to the second input terminals of the cylinder selection gate circuits 116b and 116d. The output signal of the timer TIM2 is input. Further, the cylinder selection gate signals OP1 to OP4 from the microprocessor 110 are individually input to the third input terminals of the cylinder selection gate circuits 116a to 116d, respectively.

  The timer output switching command signal INHB generated by the microprocessor 110 has a logic level “H” when the authentication verification result of the start key 103 is valid, and validates the drive command for the engine driving device 161A. .

  As will be described later with reference to FIG. 2, the output signals of the drive control timers TIM1 and TIM2 have a first set time (variable set OFF time) after the operation of the detection signal of the crank angle sensor 105a from the L level to the H level. After the elapse of time, the logic level becomes “H” to drive the engine driving device 161A, and after the variable second set time elapses, the logic level returns to “L” to stop the driving of the engine driving device 161A. .

  The cylinder selection gate signals OP1 to OP4 sequentially select the cylinders for which the fuel injection control and the ignition control are performed, and the logic level becomes “H” during the period in which the engine driving devices 161a to 161d of each cylinder are operating. Become. Further, at least every time the crank angle sensor 105a operates (L → H), the cylinder selection gate signal OP1 and the cylinder selection gate signal OP3 are alternately logically inverted, and the cylinder selection gate signal OP2 and the cylinder selection gate are inverted. The signal OP4 is logically inverted alternately. Therefore, the logic levels of the cylinder selection gate signals OP1 and OP3 are not simultaneously “H”, and similarly, the logic levels of the cylinder selection gate signals OP2 and OP4 are not simultaneously “H”.

  A constant voltage power supply circuit 120 in the in-vehicle engine control apparatus 100A is supplied with power from an in-vehicle battery 101 serving as an external power supply via an output contact 102a of a power supply relay, and a control power supply voltage Vcc (for example, a stabilized power supply voltage Vb) DC5V) to supply control power to the microprocessor 110.

  The synchronization clock signal CLK generated by the microprocessor 110 includes a driver circuit 141a in the in-vehicle engine control apparatus 100A, a synchronization signal transmission line 11 including external wiring that connects the in-vehicle engine control apparatus 100A and the key switch body 104, The signal is supplied to the immobilizer 104b in the key switch body 104 via the receiver circuit 141b in the key switch body 104.

  Communication data DATA between the microprocessor 110 and the immobilizer 104b is composed of a driver circuit 142a in the in-vehicle engine control device 100A, and external wiring connecting the in-vehicle engine control device 100A and the key switch body 104 from the microprocessor 110. The data is transmitted to the immobilizer 104b via the data communication line 12A and the receiver circuit 142b in the key switch body 104. Further, the communication data DATA is transmitted from the immobilizer 104b to the microprocessor 110 via the driver circuit 143b in the key switch body 104, the data communication line 12A, and the receiver circuit 143a in the in-vehicle engine control device 100A. .

  The authentication gate circuit 144 connected to the microprocessor 110 includes a logical product element having the output information of the drive control timer TIM1 and the inverted logical signal of the timer output switching command signal INHB as input information. The output signal is supplied to the immobilizer 104b via the driver circuit 145a, the PWM signal transmission line 13, and the receiver circuit 145b in the key switch body 104.

  As will be described later, the drive control timer TIM1 in the microprocessor 110 generates the pulse width modulation signal PWM and supplies it to the immobilizer 104b until the validity of the start key 103 is authenticated. Thereby, the immobilizer 104b has a frequency that is inversely proportional to the period of the pulse width modulation signal PWM and an amplitude that is proportional to the duty of the pulse width modulation signal PWM (the ratio between the time and the period when the logic level is “H”). A radio signal is generated, and radio communication is performed with the transponder 104 a provided in the start key 103.

  During the period in which the drive control timer TIM1 (also used as the authentication control timer) is generating the pulse width modulation signal PWM, the logic level of the timer output switching command signal INHB becomes “L” and passes through the authentication gate circuit 144. Then, the pulse width modulation signal PWM is transmitted to the immobilizer 104b. However, at this time, the cylinder selection gate circuits 116a and 116c are stopped by the timer output switching command signal INHB, so that the pulse width modulation signal PWM is not supplied to the engine driving devices 161a and 161c. .

  If the output of the drive control timer TIM2 is stopped during the period when the logic level of the timer output switching command signal INHB is “L”, the timer output switching command signal INHB is used as the cylinder selection gate circuit. The interlock circuit 119 (see the broken line) introduced into 116b and 116d is unnecessary. However, if the interlock circuit 119 is connected to the cylinder selection gate circuits 116b and 116d, the output of the cylinder selection gate circuits 116b and 116d is also stopped by the timer output switching command signal INHB. The output generation of the drive control timer TIM2 can be stopped reliably.

  The timer circuit units 300ac and 300bd in the microprocessor 110 are configured by counter circuits (CNT1 and CNT2) for generating drive control timers TIM1 and TIM2. Similarly, the timer circuit unit 300rv functions as a means for detecting the engine rotation speed Ne, and includes a counter circuit (CNT0) for measuring the operation interval (H-level pulse generation interval) of the crank angle sensor 105a. . Details of the timer circuit units 300ac, 300bd, and 300rv will be described later with reference to FIG.

Next, output characteristics of the drive control timers TIM1 and TIM2 in FIG. 1 will be described with reference to the timing chart of FIG.
In FIG. 2, for the horizontal axis (crank angle position of the engine rotation shaft), (A) a detection signal of the crank angle sensor 105a, (B) an output signal of a fuel injection drive control timer TIM1, (C) fuel injection The operation sequence of the output signal of the drive control timer TIM2 of (1), (D) the output signal of the ignition drive control timer TIM1, and (E) the output signal of the ignition drive control timer TIM2 is shown.

  In FIG. 2A, the detection signal of the crank angle sensor 105a is generated when the crank angle sensor 105a operates only once (L → H) in the engine rotation cycle T0 (1 rotation: 360 degrees). The piston position can be determined. However, in practice, the rotation angle is determined by the elapsed time from the latest operation of the crank angle sensor 105a instead of the rotation angle. The rotation cycle T0 (the operation cycle of the crank angle sensor 105a) is measured every time as a value inversely proportional to the engine rotation speed Ne, and the rotation cycle T0 measured last time is handled as a time corresponding to the current crank angle 360 degrees.

  FIGS. 2B and 2C show the first and third fuel injection solenoid valves INJ1 when the engine driving devices 161a to 161d are the fuel injection solenoid valves INJ1 to INJ4. , Output characteristics of the drive control timer TIM1 for driving INJ3 and the drive control timer TIM2 for driving the second and fourth fuel injection solenoid valves INJ2 and INJ4 in the fuel injection order.

  In FIG. 2B, a time T11 corresponding to the elapsed time from the latest operation of the crank angle sensor 105a corresponds to the valve opening timing of the fuel injection solenoid valves INJ1 and INJ3, and the time corresponding to the subsequent elapsed time. T12 corresponds to a valve opening period until the closing timing of the fuel injection solenoid valves INJ1 and INJ3. The fuel injection solenoid valves INJ1 and INJ3 are divided by cylinder selection gate signals OP1 and OP3, and the fuel injection solenoid valve INJ1 and the fuel injection solenoid valve INJ3 operate alternately.

  Similarly, in FIG. 2C, a time T21 corresponding to the elapsed time from the latest operation of the crank angle sensor 105a corresponds to the valve opening timing of the fuel injection solenoid valves INJ2 and INJ4, and the elapsed time subsequent thereto. The corresponding time T22 corresponds to the valve opening period until the closing timing of the fuel injection solenoid valves INJ2, INJ4. The fuel injection solenoid valves INJ2 and INJ4 are classified by the cylinder selection gate signals OP2 and OP4, and the fuel injection solenoid valve INJ2 and the fuel injection solenoid valve INJ4 operate alternately.

  2D and 2E show that when the engine driving devices 161a to 161d are gasoline engine ignition coils IGC1 to IGC4, the first and third ignition coils IGC1 and IGC3 are driven. Output characteristics of the drive control timer TIM1 that drives the ignition coils IGC2 and IGC4 having the second and fourth ignition orders are shown.

  In FIG. 2D, a time T13 corresponding to the elapsed time from the latest operation of the crank angle sensor 105a corresponds to the excitation start timing of the ignition coils IGC1 and IGC3, and a time T14 corresponding to the subsequent elapsed time is This corresponds to the excitation period until the excitation cutoff timing (ignition timing) of the ignition coils IGC1 and IGC3. The sections of the ignition coils IGC1 and IGC3 are discriminated by the cylinder selection gate signals OP1 and OP3, and the ignition coil IGC1 and the ignition coil IGC3 operate alternately.

  Similarly, in FIG. 2E, a time T23 corresponding to the elapsed time from the latest operation of the crank angle sensor 105a corresponds to the excitation start timing of the ignition coils IGC2 and IGC4, and the time corresponding to the subsequent elapsed time. T24 corresponds to an excitation period until the excitation cutoff timing (ignition timing) of the ignition coils IGC2 and IGC4. The sections of the ignition coils IGC2 and IGC4 are discriminated by the cylinder selection gate signals OP2 and OP4, and the ignition coil IGC2 and the ignition coil IGC4 operate alternately.

Next, the timer circuit units 300ac, 300bd, 300rv in FIG. 1 and the timer output unit 304n in the microprocessor 110 will be described with reference to the block diagram of FIG.
In FIG. 3, the timer circuit unit 300n representatively shows timer circuit units 300ac, 300bd, and 300rv, and the timer output unit 304n representatively shows timer output units 304ac, 304bd, and 304rv.

The timer circuit unit 300n includes a time counter 301 to which a clock signal 113 for time measurement is input, a set value register 302 in which a time target value is set by the microprocessor 110, a value of the current value register of the time counter 301, and a set value register And a comparison circuit 303 for comparing values 302.
In FIG. 3, the timer circuit unit 300n is provided outside the integrated circuit element constituting the microprocessor 110, and the timer output unit 304n is provided inside the integrated circuit element constituting the microprocessor 110. Both may be configured to be installed inside or outside the microprocessor 110, and FIG. 1 shows an example in which both are configured in the microprocessor 110.

  The time counter 301 in the timer circuit unit 300n has a current value register for outputting the current count value. The counting current value of the current value register increases with time as the time counter 301 counts the clock signal 113 for time counting. Note that the clock signal 113 for time measurement is a pulse train signal of a fixed time obtained by dividing a reference clock signal (not shown) supplied to the microprocessor 110.

  The detection signal from the crank angle sensor 105a and the comparison coincidence output CMP from the comparison circuit 303 are input to the interrupt input terminal of the microprocessor 110. The current count value of the time counter 301 is read into the microprocessor 110 via the read input terminal RD. When the logic level is “H”, the reset signal RST generated by the microprocessor 110 resets the current count value of the time counter 301 to zero and supplies the time counter signal to the time counter 301 (time signal). Stop input.

  The set value register 302 in the timer circuit unit 300n is composed of a memory, and a time measurement target value is written by a set output SET from the microprocessor 110. The comparison circuit 303 compares the current count value in the current value register in the time counter 301 with the target time value in the set value register 302, and supplies a comparison match output CMP to the microprocessor 110 if they match.

  The timer output unit 304n in the microprocessor 110 is constituted by a RAM memory 111 (see FIG. 1), and has an alternating inversion flag in which the logic level is alternately inverted every time the comparison match output CMP is input. The inversion control operation of the alternating inversion flag is executed by flag inversion means 522 (described later with reference to FIG. 5) stored in the program memory 112A.

  As will be described later with reference to FIGS. 4 and 5, the timer circuit unit 300n is used as a drive control timer, used as an authentication control timer for generating a pulse width modulation signal PWM, and measures an engine rotation period T0. Used to do.

  Hereinafter, as a first example of the timer circuit unit 300n, referring to FIGS. 1 to 3, the timer circuit unit 300rv (counter circuit CNT0) in FIG. 1 is used to measure the engine rotation period T0. A control operation of the microprocessor 110 will be described.

  The microprocessor 110 first generates a reset output RST to reset the current count value of the time counter 301, and when the detection signal of the crank angle sensor 105a operates from L level to H level, The current count value of the time counter 301 is read via the read input terminal RD. Immediately thereafter, the reset output RST is instantaneously generated again to repeat the process of resetting the current count value. As a result, a value proportional to the operation interval time (engine rotation period T0) of the crank angle sensor 105a is obtained as a read value from the read input terminal RD.

  Next, as a second example of the timer circuit unit 300n, the control operation of the microprocessor 110 when generating the pulse width modulation signal PWM using the timer circuit unit 300ac (counter circuit CNT1) in FIG. 1 will be described. .

  First, the microprocessor 110 resets the timer output unit 304ac (304n) to set the logic output of the drive control timer TIM1 (TIMn) to “L”. Subsequently, the set OFF time (the first set time in which the logic output level of the drive control timer TIM1 is “L”) is written in the set value register 302 in the timer circuit unit 300ac by the set output SET. Further, the count current value of the time counter 301 is instantaneously reset by the reset signal RST, and the time counting operation of the time counter 301 is started.

  Thereafter, when the current count value of the time counter 301 increases and reaches the set OFF time stored in the set value register 302, the comparison circuit 303 outputs the first comparison match output CMP to the interrupt input terminal of the microprocessor 110. To enter.

  When the comparison coincidence output CMP is generated, the microprocessor 110 inverts the logic output of the timer output unit 304ac composed of the alternating inversion flag to “H”. Subsequently, the setting ON time (second setting time when the logic level is “H”) is written in the setting value register 302 by the setting output SET. Further, the current count value of the time counter 301 is instantaneously reset by the reset signal RST, and the time measuring operation is started again.

  Thereafter, when the count current value of the time counter 301 increases and reaches the set ON time stored in the set value register 302, the comparison circuit 303 generates the next comparison match output CMP, and the microprocessor 110 The logic output of the timer output unit 304ac composed of the alternating inversion flag is inverted to “L” again. Thereafter, the same operation is repeated.

  The above operation is typically described for the case where the pulse width modulation signal is generated using the timer circuit unit 300ac (counter circuit CNT1) and the timer output unit 304ac (drive control timer TIM1) for odd-numbered cylinders. It is also possible to generate a pulse width modulation signal using the timer circuit unit 300bd (counter circuit CNT2) and the timer output unit 304bd (drive control timer TIM2) for even-numbered cylinders.

  Next, as a third example of the timer circuit unit 300n, control of the microprocessor 110 when generating a drive control signal for the engine driving device 161A using the timer circuit unit 300ac (counter circuit CNT1) in FIG. The operation will be described.

  The microprocessor 110 first resets the timer output unit 304ac to set the logic output to “L”, and sets the set OFF time (the first set time in which the logic level is “L”) in the set value register 302 by the set output SET. ) And the reset signal RST is continuously generated to stop counting the clock signal 113 for timekeeping, and keep the current count value of the time counter 301 in the reset state.

  Thereafter, when the logic level of the detection signal of the crank angle sensor 105a becomes “H” with the engine rotation, the microprocessor 110 stops generating the reset signal RST and counts the clock signal 113 for clocking by the clock counter 301. Let it begin.

  As a result, when the current count value of the time counter 301 matches the set OFF time of the set value register 302, the first comparison match output CMP from the comparison circuit 303 is input to the interrupt input terminal of the microprocessor 110, The processor 110 inverts the logic output of the timer output unit 300ac to the “H” level. In addition, the set ON time (second set time in which the logic level is “H”) is written to the set value register 302 by the set output SET, and the current count value of the time counter 301 is instantaneously received by the reset signal RST. Reset to start timing operation.

  Thereafter, when the count current value of the time counter 301 increases and reaches the set ON time stored in the set value register 302, the comparison circuit 303 generates the next comparison match output CMP. In response to the comparison match output CMP, the microprocessor 110 restores and inverts the logic output of the timer output unit 304ac to “L”. In addition, the setting output SET is used to write the setting OFF time (the first setting time in which the logic level is “L”) to the setting value register 302, and the reset signal RST is continuously generated, so that the clock signal 113 for clocking is used. Is stopped, and the current count value of the time counter 301 is maintained in the reset state. Thereafter, it waits for the next detection signal of the crank angle sensor 105a to arrive.

  When the timer circuit unit 300n is used as a drive control timer, the time counter 301 is constituted by a subtraction counter, and the time target value is set in the current value register in the time counter 301 by the setting output SET. Good. In this case, the current value register in the time counter 301 is also used as the set value register 302, and the comparison circuit 303 is a circuit that determines whether or not the value of the current value register has become zero. When reaching zero, the comparison coincidence output CMP is generated.

  The above operation is typically described for the case of the timer circuit unit 300ac (counter circuit CNT1) and the timer output unit 304ac (drive control timer TIM1) for odd-numbered cylinders. The same applies to 300bd (counter circuit CNT2) and timer output unit 304bd (drive control timer TIM2).

Next, the operation according to the first embodiment of the present invention shown in FIG.
In FIG. 1, when the power switch 103a is closed, the output contact 102a of the power supply relay is closed, and the power supply voltage Vb (for example, 10V to 16V) is applied from the in-vehicle battery 101 to the in-vehicle engine control device 100A. A stabilized control power supply voltage Vcc (= 5 V) is supplied to the microprocessor 110 via the power supply circuit 120.

  The microprocessor 110 authenticates and verifies the validity of the used start key 103 via the immobilizer 104b, and then continues the operation state of the in-vehicle sensor group 105 and the input / output control program stored in the program memory 112A. Based on the control, the electric load group 106 is controlled, and the drive control timers TIM1 and TIM2 are operated based on the drive control program for the engine drive device 161A.

Next, an authentication verification operation and a drive control operation according to the first embodiment of the present invention will be described with reference to the flowchart of FIG. 4 together with FIGS.
In FIG. 4, Step 403 constitutes a reading confirmation means, Step 407 constitutes an authentication verification means, Step 408 constitutes a start / stop means, Step 409 constitutes an output prohibiting means, and Step 411 Constitutes timer output switching means. Steps 412ac, 412bd, 413ac, and 413bd constitute drive control means 421 for the engine driving device 161A.

  In FIG. 4, when the microprocessor 110 starts operation (step 400), first, it is determined whether or not the operation is the initial operation based on whether or not the initial operation completion flag is set in step 410 (described later) (step 400). 401).

  If it is determined in step 401 that the operation is the first operation (that is, YES), the process proceeds to the next step 402, and if it is determined that the operation is not the first operation (that is, NO), the process proceeds to step 412. The initial operation completion flag set in step 410 is reset when the power is turned on, so that when the power switch 103a is closed, a determination of “YES” is always made once in step 401.

  In step 402, the microprocessor 110 performs communication between the microprocessor 110 and the immobilizer 104b via the synchronization signal transmission line 11 and the data communication line 12A, and the immobilizer 104b passes through the data communication line 12A. The communication data DATA (related to the frequency and amplitude values of the pulse width modulation signal PWM) transmitted to is received as immobilizer information.

  Subsequently, whether or not the read information is normal is determined based on whether or not the communication data DATA (request data) read in step 402 matches the data stored in the program memory 112A (step 403). ).

  If it is determined in step 403 that the read information matches the stored data and is normal (ie, YES), the process proceeds to the next step 404 where the read information does not match the stored data and is abnormal ( That is, if it is determined as NO), the process proceeds to step 408.

  In step 404, the microprocessor 110 sets the logic level of the timer output switching command signal INHB to “L” to allow the signal to pass through the authentication gate circuit 144, and outputs the logic outputs of the cylinder selection gate circuits 116a to 116d. By fixing the level to “L” and generating an ignition / injection prohibition output, the operation of the engine driving device 161A composed of an ignition coil or a fuel injection solenoid valve is stopped.

  Subsequently, the microprocessor 110 generates the pulse width modulation signal PWM using the drive control timer TIM1 configured by the timer circuit unit 300ac (counter circuit CNT1), and immobilizer 104b via the PWM signal transmission line 13. In order to transmit the pulse width modulation signal PWM, the time counter 301 in the timer circuit unit 300ac is reset, and an OFF time (set OFF time) is set in the set value register 302 (step 405). Thereafter, the pulse width modulation signal PWM is generated by the interrupt control operation of the microprocessor 110 (described later with reference to FIG. 5).

  Subsequently, the immobilizer 104 b transmits a radio signal having a frequency inversely proportional to the period of the pulse width modulation signal PWM received from the microprocessor 110 and an amplitude proportional to the duty of the pulse width modulation signal PWM to the start key 103. The password is transmitted to the transponder 104a and the password assigned to the start key 103 is read.

  The microprocessor 110 stops transmission of the pulse width modulation signal PWM after a predetermined time has elapsed, and reads the personal identification number (transponder information) from the immobilizer 104b via the data communication line 12A (step 406).

  Subsequently, it is determined whether or not the password stored in the program memory 112A matches the password read in step 406 (step 407), and the authentication verification matches (ie, YES). If it is determined, it is assumed that the key 103 is a valid start key, and the process proceeds to the next step 410. If it is determined that the authentication verification does not match (ie, NO), the process proceeds to step 408.

  When a valid password is stored in the immobilizer 104b in advance, authentication verification may be performed by the immobilizer 104b and the determination result may be transmitted to the microprocessor 110 via the data communication line 12A.

  In step 408 (starting stop means), if the determination result in step 403 is a reading error (ie, NO), or if the determination result in step 407 is a mismatch (ie, NO), the starting motor ( The engine starting is stopped by interrupting the starting circuit (not shown).

  Further, following step 408, the output signals of the drive control timers TIM1 and TIM2 are reset and the logic output level is maintained at “L” to stop ignition / injection (step 409), and the CPU operation ends. The process proceeds to processing (step 420), and the processing routine of FIG. 4 is terminated.

  On the other hand, in step 410, which is executed when the determination result in step 407 is collation match (that is, YES), an initial operation completion flag is set. Subsequently, the microprocessor 110 sets the logic level of the timer output switching command signal INHB to “H”, fixes the logic level of the output signal of the authentication gate circuit 144 to “L”, and also selects the cylinder selection gate circuit 116a. ˜116d is allowed to pass, the ignition / injection prohibition output is canceled, and the operation of the engine driving device 161A including the ignition coil or the fuel injection electromagnetic valve is made effective (step 411).

  Next, depending on whether the engine rotation period T0 detected in step 512 (see FIG. 5), which will be described later, is 200 ms or less (engine rotation speed Ne is 300 rpm or more) by engine start operation by the starter motor, It is determined whether or not the engine rotational speed Ne has reached a predetermined rotational speed (step 412).

  If it is determined in step 412 that Ne <predetermined rotational speed (that is, NO), the process proceeds to step 412ac in the drive control means 421. If Ne ≧ predetermined rotational speed (that is, YES), it is determined that drive control is performed. The process proceeds to step 413ac in the means 421.

  In step 412ac, the drive control timer TIM1 is reset, and the logic output of the drive control timer TIM1 is maintained at “L” (output stop). Subsequently, the drive control timer TIM2 is reset, the logic output of the drive control timer TIM2 is maintained at “L” (output stop) (step 412bd), and the process proceeds to the CPU operation end process (step 420).

  On the other hand, in step 413ac, as the appropriate value of the drive control timer TIM1, the appropriate value of the valve opening start timing T11 (or excitation start timing T13) in FIG. 2 and the valve opening period T12 (or excitation period T14). The appropriate value is calculated. Subsequently, as an appropriate value of the drive control timer TIM2, an appropriate value of the valve opening start timing T21 (or excitation start timing T23) in FIG. 2 and an appropriate value of the valve opening period T22 (or excitation period T24) Is calculated (step 413bd), and the process proceeds to a CPU operation end process (step 420).

  Note that the set OFF time and the set ON time calculated in steps 413ac and 413bd in the drive control means 421 are transferred and written to the set value registers 302 in the timer circuit units 300ac and 300bd at the time described later with reference to FIG. The

  Further, the appropriate values calculated in steps 413ac and 413bd are mainly determined when the engine driving device 161A is at the ignition timing of the ignition coil, and the time required for burning the fuel related to the fuel injection amount and the ignition coil. In consideration of the time required to flow a predetermined excitation current, the ignition coil is started to be excited, and the ignition is cut off at an appropriate crank angle (before the top dead center) and ignition is performed. The ignition timing is feedback adjusted in accordance with a detection signal (not shown).

  Further, when the engine driving device 161A is in an appropriate valve opening period (corresponding to the fuel injection amount) of the fuel injection solenoid valve, it is mainly proportional to the intake air amount detected by the air flow sensor (not shown). The valve opening timing is determined so as to secure the required fuel supply amount and the valve opening period related to the cylinder pressure and the fuel pressure, and to complete the pre-ignition supply of fuel, and an air-fuel ratio sensor (not shown) The valve opening period is feedback adjusted in accordance with the detection signal of).

  In an operation end step 420 executed following steps 409, 412bd, and 413bd, another operation program is executed after waiting for an operation, and at least after a calculation cycle (for example, 10 ms), the operation start step 400 is resumed. It is supposed to be. The calculation cycle (= 10 ms) is the time required for one revolution of the engine rotating at 6000 rpm.

Next, the interrupt control operation according to the first embodiment of the present invention will be described with reference to the flowchart of FIG.
In FIG. 5, steps 505, 507, 512 a and 515 constitute an operation time setting means 521, and steps 506, 508, 516 and 518 constitute a flag inverting means 522.

  In FIG. 5, the microprocessor 110 performs an input interrupt operation when the detection signal from the crank angle sensor 105a or the interrupt operation command by the comparison coincidence output CMP from the timer circuit unit 300n is input to the interrupt input terminal. Is started (step 500).

  First, the microprocessor 110 temporarily saves the current operation state to enter the calculation saving state, and when step 520 (described later) is executed, the microprocessor 110 returns to the original control flow and continues the calculation. The current state is stored (step 501).

  Subsequently, it is determined in step 410 in FIG. 4 whether or not the initial operation completion flag has been set (step 502). If it is determined that the initial operation completion flag has not been set (ie, NO), The process proceeds to the next step 503, and if it is determined that the setting of the initial operation completion flag has been completed (that is, YES), the process proceeds to step 510.

  In step 503, the logical level of the comparison coincidence output CMP of the timer circuit unit 300ac (represented as the timer circuit unit 300n in FIG. 3) corresponding to the counter circuit CNT1 that generates the pulse width modulation signal PWM is “H”. Is determined.

  If it is determined in step 503 that the comparison coincidence output CMP has become “H” (ie, YES), the process proceeds to the next step 504, where the comparison coincidence output CMP is “L” (ie, NO). If determined, the process proceeds to a return process (step 520), and the interrupt control routine of FIG. 5 is terminated. Note that the comparison coincidence output CMP is based on the fact that the time counter 301 has started counting in step 405 in FIG.

  In step 504, whether or not the output logic level (the logic output of the pulse width modulation signal PWM from the alternating inversion flag) is “H” in the timer output unit 304ac (represented as 304n in FIG. 3). Determine.

  If it is determined in step 504 that the logic level of the output signal of the timer output unit 304ac is “H” (that is, YES), the process proceeds to step 505 in the operation time setting unit 521, and the logic level is “L”. If it is determined that NO (that is, NO), the process proceeds to step 507 in the operation time setting means 521.

  In step 505 in the operation time setting means 521, an OFF time is set in the set value register 302 by a setting output SET. Subsequently, the process proceeds to step 506 in the flag inverting unit 522, the timer output unit 304ac is instantaneously reset, and the logic output is inverted to “L”.

  On the other hand, in step 507 in the operation time setting means 521, an ON time (set ON time) is set in the set value register 302 by the setting output SET. Subsequently, the process proceeds to a step in the flag inverting means 522, the timer output unit 304ac is instantaneously set, and the logic output is inverted to “H”.

  In step 509 following steps 506 and 508 in the flag inverting means 522, the current count value of the time counter 301 is instantaneously reset, and the process proceeds to a return process (step 520). Thereby, the timing of the OFF time or ON time set in step 505 or 507 in the operation time setting means 521 is started, and the interrupt control routine of FIG. 5 is ended.

  Thereafter, when the OFF time or ON time set in step 505 or 507 is reached, the timer circuit unit 300ac generates the comparison coincidence output CMP, and the input interrupt operation start step 500 is activated again. Through the series of operations in steps 503 to 509, the logic output of the timer output unit 304ac is alternately inverted. At this time, the first set time in which the logic level of the timer output unit 304ac is “L” is determined by the OFF time set in step 505, and the logic level of the timer output unit 304ac becomes “H”. The second set time is determined by the ON time set in step 507.

  On the other hand, in step 510 that is executed when it is determined that the initial operation is completed (ie, YES) in step 502, is the interrupt operation started by the detection signal (L → H) of the crank angle sensor 105a? Determine whether or not. If it is determined in step 502 that the detection signal of the crank angle sensor 105a has started from the L level to the H level (ie, YES), the process proceeds to step 511, where the crank angle sensor 105a If it is determined that the interrupt operation is not started due to the detection signal operating (L → H) (ie, NO), the process proceeds to step 513.

  In step 511, the count current value of the timer circuit unit 300rv (counter circuit CNT0) for measuring the rotation period T0 is read, and the current value register is instantaneously reset. Subsequently, the process proceeds to step 512a in the operation time setting means 521, and steps 413ac and 413bd in FIG. 4 are applied to the set value register 302 in the timer circuit unit 300ac and the timer circuit unit 300bd (counter circuits CNT1 and CNT2). The OFF time of the set ON / OFF times calculated in step 1 is set.

  Subsequently, the current value registers in the timer output units 304ac and 304bd (drive control timers TIM1 and TIM2) and the timer circuit units 300ac and 300bd (counter circuits CNT1 and CNT2) are instantaneously reset, or steps 518 and 519 are performed. The state that has been continuously reset is canceled (described later) (step 512b), and the process proceeds to return processing (step 520).

  On the other hand, in step 513, which is executed when it is determined that the determination result in step 510 is not an interruption by the crank angle sensor 105a (that is, NO), the comparison coincidence output CMP (H level) generated by the timer circuit units 300ac and 300bd. ).

  If it is determined in step 513 that the interrupt is due to the comparison coincidence output CMP (H level) (ie, YES), the process proceeds to the next step 514 and is not an interruption due to the comparison coincidence output CMP (H level) (ie, NO). ), The process immediately proceeds to return processing (step 520).

  In step 514, it is determined whether or not the logic level of the output signals (alternate inversion flag) of the timer output units 304ac and 304bd (drive control timers TIM1 and TIM2) is “L”. If it is determined in step 514 that the logical level of the alternating inversion flag is “L” (that is, YES), the process proceeds to step 515 in the operation time setting means 521, and the logical level of the alternating inversion flag is “L”. If not (ie, NO), the process proceeds to step 518 in the flag inverting means 522.

  In step 515 in the operation time setting means 521, the ON time of the set ON / OFF time calculated in step 413ac or 413bd in FIG. 4 is set for the set value register 302 in the timer circuit unit 300ac or 300bd. Set. At this time, the distinction between the timer circuit units 300ac and 300bd for which the ON time is to be set is determined depending on which output of the timer circuit units 300ac and 300bd is the comparison coincidence output CMP determined in step 513.

  Subsequently, the process proceeds to step 516 in the flag inverting means 522, the alternating inversion flag in the timer output unit 304ac or 304bd is instantaneously set, and the logic output level is inverted to “H”. At this time, the distinction between the timer output units 304ac and 304bd subject to the instantaneous setting of the alternating inversion flag to “H” is determined depending on which output the comparison coincidence output CMP determined in step 513 was.

  Subsequently, the current value register of the timer circuit unit 300ac or 300bd (counter circuits CNT1 and CNT2) is instantaneously reset (step 517), and the process proceeds to return processing (step 520). At this time, the distinction between the timer circuit units 300ac and 300bd to be instantaneously reset is determined by which output the comparison coincidence output CMP determined in step 513 is.

  On the other hand, in step 518 in the flag inversion means 522 executed when the alternating inversion flag is determined to be “H” (ie, NO) in step 514, the alternating inversion flag of the timer output unit 304ac or 304bd is continuously set. The logic output level is inverted and maintained at “L”. At this time, the distinction between the timer output units 304ac and 304bd to be subjected to the continuous reset of the alternating inversion flag to “L” is determined depending on which output the comparison coincidence output CMP determined in step 513 is.

  Subsequently, the current value register of the timer circuit unit 300ac or 300bd is continuously reset (step 519), and the process proceeds to a return process (step 520). At this time, the distinction between the timer circuit units 300ac and 300bd that are the targets of continuous reset of the current value register is determined by which output the comparison coincidence output CMP determined in step 513 is.

  The above operations will be summarized and described generally. The series of processing in steps 503 to 509 in FIG. 5 functions as a means for generating the pulse width modulation signal PWM. As a result, the timer output unit 304ac in the microprocessor 110 causes the pulse width modulation signal PWM to be alternately written in steps 505 and 507 (consisting of an OFF time of logic “L” and an ON time of logic “H”). Is generated. The pulse width modulation signal PWM is transmitted to the immobilizer 104b via the authentication gate circuit 144, the driver circuit 145a, the PWM signal transmission line 13 and the receiver circuit 145b in FIG.

  Further, in the series of processing of steps 510 to 512b, the current count value of the timer circuit unit 300rv in FIG. 3 is read, the engine rotation cycle T0 is measured, the current count value is initialized, and the crank angle In synchronization with the operation of the sensor 105a, the timer circuit units 300ac and 300bd are set to OFF time and initialized and restarted.

  In the series of steps 513 to 517, the logic output of the timer circuit units 300ac and 300bd that has generated the comparison match output CMP is inverted to “H”, the ON time is set, and the time counter 301 The current count value is reset to start counting the ON time.

  Further, in the series of processing of steps 513 to 519, the logic output of the timer circuit units 300ac and 300bd that has generated the comparison coincidence output CMP is reversed and returned to “L” until the crank angle sensor 105a operates again. The logic output of the timer output unit 304n is maintained at “L”, the current count value of the time counter 301 is reset, and the time measuring operation is stopped.

  As described above, the in-vehicle engine control apparatus 100A according to the first embodiment of the present invention is supplied with power from the in-vehicle battery 101, and the drive control means 421 for the engine driving device 161A including at least one of the fuel injection solenoid valve and the ignition coil. A transponder 104a provided in the start key 103, and a program memory 112A storing a control program serving as authentication verification means (step 407) for the start key 103 and a microprocessor 110 cooperating with the program memory 112A. An immobilizer 104b for reading out the personal identification number of the start key 103 with a radio signal is connected via the.

  The microprocessor 110 includes a plurality of timer circuit units 300ac and 300bd (counter circuits CNT1 and CNT2) and timer output units 304ac and 304bd (drive control timers TIM1 and TIM2). The program memory 112A includes a timer circuit unit 300ac. , 300bd operating time setting means 521 and timer output switching means (step 411).

  The timer circuit units 300ac and 300bd count the time counter 301 that counts the clock signal 113 for time count, the set value register 302, and the current count value of the time counter 301 reaches the target set value stored in the set value register 302. The comparator circuit 303 generates the comparison coincidence output CMP and drives the timer output unit 304n.

  The timer output units 304ac and 304bd are output circuits that generate logic outputs corresponding to predetermined ON and OFF times that are variably set in the set value register 302 by the microprocessor 110.

  The operation time setting means 521 transfers and stores the OFF time data or the ON time data to the set value register 302, and resets the current count value of the time counter 301 at the start of time measurement.

  The authentication verification unit 407 reads the password by a radio signal having a frequency and an amplitude corresponding to the period and duty of the pulse width modulation signal PWM transmitted from the microprocessor 110, and the read password is stored in the program memory 112A. Alternatively, an authentication determination is made as to whether or not the correct password number stored in advance in the immobilizer 104b matches.

  The pulse width modulation signal PWM is generated by the timer circuit unit 300ac, the operation time setting unit 521, and the timer output unit 304ac, and is composed of a continuous pulse signal having a predetermined OFF time and ON time.

  The timer output switching means 411 generates a timer output switching command signal INHB when the authentication determination result is a coincidence determination, and causes the timer circuit unit 300ac used for generating the pulse width modulation signal PWM to be a drive control timer. Switching is used as TIM1.

  The output signal of the drive control timer TIMn is generated by the timer circuit units 300ac and 300bd, the operation time setting means 521, and the timer output units 304ac and 304bd, and starts operating in synchronization with the detection signal of the crank angle sensor 105a. Thus, a timer output is generated after the first set time corresponding to the set OFF time has elapsed, and the timer output is stopped after the second set time corresponding to the set ON time has elapsed. As a result, the engine drive device 161A is driven by the timer output of the drive control timer TIMn, and one of the timer circuit units 300ac and 300bd is selectively used in the authentication verification unit 407 and the drive control unit 421. Until the coincidence determination is obtained as a result of the authentication verification, the selection switching to the drive control unit 421 is not performed, and the generation of the output signal of the drive control unit 421 is prohibited.

  The timer output units 304ac and 304bd are generated by the flag inverting means 522 stored in the program memory 112A. The operation time setting means 521 alternately transfers OFF time data or ON time data to the set value register 302 and resets the current count value of the time counter 301 at the start of time measurement.

  The flag inversion means 522 inverts the logic output every time the comparison circuit 303 of the time counter 301 generates the comparison coincidence output CMP, and generates an output signal having a logic level of “L” during the OFF time setting period. In the set period, a flag that generates an output signal having a logic level of “H” is set as a timer output. At this time, the clock counter 301 that counts the clock signal 113 for clocking at high speed is used to reduce the control burden on the microprocessor 110 and to obtain a highly accurate timer. Further, since the timer output unit is generated by the input interrupt control of the microprocessor 110, the configuration of the timer circuit unit 300n is simplified and inexpensive.

  The period and duty value of the pulse width modulation signal PWM are stored in both the program memory 112A and the immobilizer 104b, and the program memory 112A includes a control program serving as a read confirmation unit (step 403).

  The read confirmation means 403 in the program memory 112A reads the period and duty stored in the immobilizer 104b in advance, and the microprocessor 110 performs a pulse when the read data matches the correct data stored in the program memory 112A. A width modulation signal PWM is transmitted. Accordingly, it is possible to prevent an unauthorized immobilizer from being used.

  The drive control timer TIM1 includes a timer circuit unit 300ac, an operation time setting unit 521, and a timer output unit 304ac. Start, generate a timer output after the elapse of the first set time corresponding to the set OFF time, start excitation for the ignition coil, and stop the timer output after the elapse of the second set time corresponding to the set ON time To do. Thereby, the excitation of the ignition coil is interrupted and ignition is performed. Therefore, the pulse width modulation signal PWM can be easily generated by changing the operation start command of the ignition control drive control timer that starts operation in synchronization with the operation of the crank angle sensor 105a.

  Further, the output signal of the drive control timer TIM1 is sequentially distributed and supplied to a plurality of cylinders via the gate circuits 116a and 116c for discriminating adjacent ignition cylinders. Timer circuit units 300ac are used. The second drive control timer TIM2 by the other one timer circuit section 300bd is used for the cylinders whose ignition order is an even number. The output signal of the second drive control timer TIM2 is sequentially distributed and supplied to the plurality of cylinders via the gate circuits 116b and 116d for discriminating adjacent ignition cylinders. Therefore, when one of the drive control timers is used, the time of the drive control timer that operates next can be set without delay by calculating the set time of the other drive control timer in advance. it can.

  Further, the output signal of the drive control timer TIM1 is generated by the timer circuit unit 300ac, the operation time setting means 521 and the timer output unit 304ac to give an energization command to the fuel injection solenoid valve and to detect the crank angle sensor 105a. After the first set time corresponding to the set OFF time elapses, the timer output is generated to drive the solenoid valve for fuel injection to open, and the second setting corresponding to the set ON time is started. After the elapse of time, the timer output is stopped and the fuel injection solenoid valve is returned to the closed state. Thus, since the fuel supply timing and the fuel supply period are determined by the timer output, the operation start command of the drive control timer for fuel injection control that starts operation in synchronization with the operation of the crank angle sensor 105a is changed. The pulse width modulation signal PWM can be easily generated.

  The output signal of the drive control timer TIM1 is sequentially distributed and supplied to a plurality of cylinders via the gate circuits 116a and 116c for discriminating adjacent injection cylinders. A timer circuit unit 300ac is used. The second drive control timer TIM2 by the other one timer circuit section 300bd is used for the cylinders whose fuel injection order is an even number. The output signal of the second drive control timer TIM2 is sequentially distributed and supplied to the plurality of cylinders via the gate circuits 116b and 116d for discriminating adjacent injection cylinders. Therefore, when one of the drive control timers is used, the time of the drive control timer that operates next can be set without delay by calculating the set time of the other drive control timer in advance. it can.

Embodiment 2. FIG.
Although not mentioned in the first embodiment, as shown in FIG. 6, a series opening / closing element 130 and an auxiliary opening / closing element 137 are further provided in relation to the engine start key 103 and the starter motor 108. Also good.

  The second embodiment of the present invention will be described below with reference to the circuit block diagram of FIG. In FIG. 6, the control circuit of the starting motor 108 that is omitted in FIG. 1 is mainly shown. Further, the same reference numerals as those described above (see FIG. 1) are attached, or “B” is added after the reference numerals. Furthermore, other configurations and operations are as described above, and FIGS. 2 to 5 can be applied as they are.

  In FIG. 6, the in-vehicle battery 101 is connected to the engine control device 100 </ b> B that controls the engine driving device 161 </ b> B via the output contact 102 a of the power relay 102. The excitation coil 102b of the power relay 102 is driven by a drive transistor 121 (described later). The power switch 103a connected to the engine control device 100B is closed in response to the operation position (from the first rotation position to the third rotation position) of the start key 103, and the start switch 103b is connected to the start key 103 The circuit is closed in response to the third rotation position 103. The immobilizer 104 b reads the password (unique code) added to the start key 103 and inputs it to the microprocessor 110.

  In addition, a starting motor 108 is connected to the engine control device 100B via a parking switch 109 and an electromagnetic relay 107. The starter motor 108 is supplied with power from the in-vehicle battery 101 via the output contact 107a of the electromagnetic relay 107 when the engine is started, and is engaged with an engine ring gear (not shown) by an electromagnetic push-out mechanism (not shown). Rotate the engine.

  The exciting coil 107b of the electromagnetic relay 107 is energized through a parking switch 109 that closes when the shift lever of the vehicle is in the parking position and a series opening / closing element 130 (described later).

  As an internal configuration of the engine control apparatus 100B, the microprocessor 110 is connected to each memory by a bus so as to cooperate with a RAM memory 111 for arithmetic processing and a program memory 112B (for example, a non-volatile flash memory).

  The program memory 111B stores an input / output control program for functioning as the in-vehicle engine control device 100B, as well as the authentication verification unit 407, timer output switching unit 411, and drive control unit described above (see FIGS. 4 and 5). 421 and a control program to be the operation time setting means 521 and unique code data for collation of the personal identification number are stored. The microprocessor 110 is connected to a timer circuit unit 300n similar to that described above (see FIG. 3), and the microprocessor 110 includes a timer output unit 304n driven by the timer circuit unit 300n.

  The constant voltage power supply circuit (control power supply unit PSU) 120 is supplied with power from the output contact 102a of the power supply relay 102, and generates the control voltage Vcc (= 5V) based on the power supply voltage Vb (= 10V to 16V) of the in-vehicle battery 101. The stabilized voltage is supplied to each part in the in-vehicle engine control apparatus 100B including the microprocessor 110.

  The drive transistor 121 that energizes the exciting coil 102b is supplied with a base current from the power switch 103a via the drive resistors 122a and 122b and the diode 122c connected in series with each other, and becomes conductive. Is closed.

  When the output contact 102a is closed and power is supplied to the constant voltage power supply circuit 120 and the microprocessor 110 starts operating, a self-holding drive resistor 123a and a diode 123b are generated from a self-holding drive command DR generated by the microprocessor 110. After that, the base current of the drive transistor 121 is supplied, so that the energizing operation of the power relay 102 is continued even after the power switch 103a is opened, and the microprocessor 110 stops the self-holding drive command DR. At this point, the power relay 102 is turned off.

  The inverting logic element 124 is a power-on monitor signal whose logic level becomes “L” / “H” in accordance with the magnitude of the potential at the connection point of the driving resistors 122a and 122b, that is, the ON / OFF of the power switch 103a. A PWS is generated and input to the microprocessor 110.

  The series open / close element 130 formed of a P-channel field effect transistor has a source terminal connected to the vehicle-mounted battery 101 via the start switch 103b, a drain terminal connected to the excitation coil 107b via the parking switch 109, and a gate. The terminal is connected to the connection point between the open circuit stabilization resistor 132 and the conduction drive resistor 133.

  The open circuit stabilization resistor 132 is connected between the source terminal and the gate terminal of the series switching element 130. The gate terminal of the series switching element 130 is connected to the ground circuit via the conduction drive resistor 133 and the conduction drive transistor 134. The conduction drive transistor 134 formed of an NPN transistor is turned on when a base current is supplied from the start switch 103 b via the start resistor 135 and energizes the electromagnetic relay 107 via the series switching element 130.

  The commutation diode 131 is connected in parallel to a series circuit including the parking switch 109 and the exciting coil 107b. A stable resistor 136 connected to the starting resistor 135 is connected between the base terminal and the emitter terminal of the conduction drive transistor 134.

  The auxiliary open / close element 137 includes a prohibition transistor connected between a base terminal and an emitter terminal of the conduction drive transistor 134, and is driven via a base resistance 138 from a conduction prohibition command output STP generated by the microprocessor 110. . The auxiliary open / close element 137 (forbidden transistor) is turned on by the conduction prohibition command output STP when the passwords do not match or when the engine is rotating, thereby making the conduction drive transistor 134 non-conductive. 107 is turned off. When the microprocessor 110 is in an inoperative state, the auxiliary switching element 137 is rendered non-conductive by the pull-down resistor 139.

Next, the operation of the second embodiment of the present invention shown in FIG. 6 will be described.
In FIG. 6, when the power switch 103a is closed, the driving transistor 121 is turned on via the driving resistors 122a and 122b and the diode 122c, the power relay 102 is energized, and the output contact 102a is closed. Power is supplied to the device 100B.

  As a result, the microprocessor 110 starts operating and generates a self-holding drive command DR, and the conduction of the drive transistor 121 is maintained by the self-holding drive resistor 123a and the diode 123b. When the start switch 103b is closed, the electromagnetic relay 107 is energized via the series opening / closing element 130 and the parking switch 109, and the starter motor 108 starts rotating.

  At this time, if the state of charge of the in-vehicle battery 101 is poor and the environmental temperature is low, the output voltage of the in-vehicle battery 101 is abnormally reduced as power supply to the starter motor 108 is started. However, even in such a poor state, the conduction of the series switching element 130 is maintained. Thereafter, when the rotation of the starting motor 108 increases and the load current decreases, the output voltage of the in-vehicle battery 101 recovers from the abnormally lowered state, and the microprocessor 110 becomes operable without any problem.

  In such an operating state, authentication verification is performed by the immobilizer 104b, and if the verification result is a coincidence determination, normal ignition control and fuel injection control are started, and the engine rotates independently. Thereafter, if the engine speed becomes sufficiently high, a prohibition command output STP is generated from the microprocessor 110, whereby the auxiliary opening / closing element 137 is turned on, the conduction drive transistor 134 and the series opening / closing element 130 are opened, and the starting motor 108 is turned on. Stop over-rotation.

  On the other hand, if the verification verification result by the immobilizer 104b does not match, the ignition control and the fuel injection control are not started, and the prohibition command output STP is immediately generated from the microprocessor 110, and the auxiliary switching element 137 becomes conductive. Then, the conduction drive transistor 134 and the series switching element 130 are opened, and the continuous rotation of the starting motor 108 is prohibited. Thereby, the moving operation of the vehicle using the starter motor 108 as a power source can be prohibited.

  As described above, the in-vehicle engine control apparatus 100B according to the second embodiment of the present invention is supplied with power from the in-vehicle battery 101 and includes at least one of a fuel injection solenoid valve and an ignition coil, as in the first embodiment. A drive control unit 421 for the engine driving device 161B, a program memory 112B storing a control program serving as an authentication verification unit (step 407) for the start key 103, and a microprocessor 110 cooperating with the program memory 112B are provided. An immobilizer 104b for reading out the personal identification number of the start key 103 by a radio signal is connected via a transponder 104a provided in the start key 103.

  Further, the microprocessor 110 includes a plurality of timer circuit units 300n and a timer output unit 304n, and the program memory 112B stores a control program serving as an operation time setting unit 521 and an timer output switching unit (step 411) for the timer circuit unit 300n. Including. The timer circuit unit 300n compares the time counter 301 that counts the clock signal 113 for time count, the set value register 302, and the current count value of the time counter 301 when it reaches the target set value stored in the set value register 302. The comparator circuit 303 generates the coincidence output CMP and drives the timer output unit 304n.

  The timer output unit 304n includes an output circuit that generates a logic output corresponding to a predetermined ON time and OFF time that are variably set in the set value register 302 by the microprocessor 110. The operation time setting means 521 transfers and stores the OFF time data or the ON time data to the set value register 302, and resets the current count value of the time counter 301 at the start of time measurement.

  The authentication verification unit 407 reads the password by a radio signal having a frequency and an amplitude corresponding to the period and duty of the pulse width modulation signal PWM transmitted from the microprocessor 110, and the read password is stored in the program memory 112B or An authentication determination is made as to whether or not the correct password stored in the immobilizer 104b matches the correct password. The pulse width modulation signal PWM is generated by the timer circuit unit 300n, the operation time setting means 521, and the timer output unit 304n, and is composed of continuous pulse signals having a predetermined OFF time and ON time.

  The timer output switching means 411 generates a timer output switching command signal INHB when the authentication determination result is a coincidence determination, and uses the timer circuit unit 300n used for generating the pulse width modulation signal PWM as the drive control timer TIM1. Use switching. The drive control timer TIMn includes a timer circuit unit 300n, an operation time setting unit 521, and a timer output unit 304n. The operation starts in synchronization with the detection signal of the crank angle sensor 105a and the first corresponding to the set OFF time. Timer output is generated after elapse of the set time, and mima output is stopped after elapse of the second set time corresponding to the set ON time. The engine output device 161B is driven by the timer output, and one of the timer circuit units 300n is selectively used in the authentication verification unit 407 and the drive control unit 421, and until a coincidence determination is obtained as a result of the authentication verification. Is not switched to the drive control means 421, and the output of the drive control means 421 is prohibited.

  The drive control timer TIM1 includes a timer circuit unit 300n, an operation time setting unit 521, and a timer output unit 304n. The drive control timer TIM1 operates in synchronization with a detection signal of the crank angle sensor 105a by issuing an energization command to the engine ignition coil. Start, generate a timer output after the elapse of the first set time corresponding to the set OFF time, start excitation for the ignition coil, and stop the mima output after the elapse of the second set time corresponding to the set ON time Ignition is performed by cutting off the excitation of the ignition coil. Therefore, the pulse width modulation signal PWM can be easily generated by changing the operation start command of the ignition control drive control timer that starts operation in synchronization with the operation of the crank angle sensor 105a.

  The drive control timer TIM1 includes a timer circuit unit 300n, an operation time setting unit 521, and a timer output unit 304n. The drive control timer TIM1 issues an energization command to the fuel injection solenoid valve and synchronizes with a detection signal of the crank angle sensor 105a. When the first set time corresponding to the set OFF time elapses after the operation starts, a timer output is generated to open the fuel injection solenoid valve, and the timer is set after the second set time corresponding to the set ON time elapses. The output is stopped and the solenoid valve for fuel injection is returned to the closed state. Thus, since the fuel supply timing and the fuel supply period are determined by the timer output, the operation start command of the drive control timer for fuel injection control that starts operation in synchronization with the operation of the crank angle sensor 105a is changed. The pulse width modulation signal PWM can be easily generated.

  The in-vehicle engine control apparatus 100B includes a series opening / closing element 130 and an auxiliary opening / closing element 137. The series opening / closing element 130 is connected in series to the exciting coil 107b of the electromagnetic relay 107 that connects the in-vehicle battery 101 and the starting motor 108. When the start switch 103b is closed, the engine is started.

  The auxiliary switching element 137 responds to the case where the result of determination by the authentication verification unit 407 is a comparison mismatch, and inhibits the series switching element 130 from conducting. Further, the auxiliary opening / closing element 137 is biased so as not to impede conduction of the series opening / closing element 130 when the microprocessor 110 is in an inoperative state.

Therefore, in the cold start of the engine, even if the voltage of the in-vehicle battery 101 is abnormally lowered due to an excessive start current until the starter motor 108 increases in rotation, the starter motor 108 rotates even if the in-vehicle engine control device 100B becomes inoperable. Can last.
In addition, when the starter motor 108 increases in rotation, the starter current decreases and the output voltage of the in-vehicle battery 101 recovers, so that the in-vehicle engine control device 100B starts operating, and if the authentication verification result is normal, the ignition is performed. Control and fuel injection control are started and the engine can rotate independently. On the other hand, if the verification verification does not match, the engine ignition control and fuel injection control are stopped and the starter motor 108 is also stopped, so that the vehicle cannot be moved using the starter motor 108 as a power source, thereby preventing unauthorized driving. can do.

Embodiment 3 FIG.
In the first and second embodiments (see FIG. 3), the single set value register 302 is provided in the timer circuit unit 300n. However, as shown in FIG. Set value registers 802a and 802b and comparison circuits 803a and 803b may be provided.

Hereinafter, the third embodiment of the present invention will be described mainly focusing on differences from FIG. 1 with reference to the circuit block diagram of FIG. 7 and the block diagram of FIG.
In FIG. 7, the same components as those described above (see FIG. 1) are denoted with the same reference numerals as those described above, or with “C” after the reference numerals.

  7 differs from FIG. 1 in that the data communication line 12C for the immobilizer 104c is a shared line that also serves as a PWM signal transmission line, and the engine driving device 161C is an ignition coil and an electromagnetic for fuel injection. The valve is used together, and the configuration of the timer circuit unit 800n (see FIG. 8) is different.

  In FIG. 7, a vehicle-mounted battery 101 is connected to the vehicle-mounted engine control device 100C via an output contact 102a of a power relay. The start key 103 is integrated with a transponder 104a for transmitting the password added to the start key 103. The transponder 104a performs wireless communication with the immobilizer 104c in the key switch body 104. Do. The immobilizer 104c is connected to the in-vehicle engine control device 100C via the data communication line 12C, reads the PIN number added to the start key 103, and inputs it to the microprocessor 110C.

  The engine driving device 161C (first engine driving device) is configured by engine driving devices 161ac and 161bd including fuel injection solenoid valves (or ignition coils), and output signals of the drive control timers TIM1 and TIM2 Therefore, it is driven via the amplification output circuit 160.

  The engine driving device 171C (second engine driving device) includes engine driving devices 171ac and 171bd including ignition coils (or fuel injection solenoid valves), and output signals of drive control timers TIM3 and TIM4. Thus, it is driven via the amplification output circuit 170. One of the engine driving devices 161C and 171C is a fuel injection solenoid valve, and the other is an ignition coil.

  The microprocessor 110C constituting the main part of the in-vehicle engine control apparatus 100C cooperates with a RAM memory 111 for arithmetic processing, a program memory 112C (for example, a non-volatile flash memory), and a multi-channel AD converter not shown. The detection signals of the analog sensors that operate and are included in the in-vehicle sensor group 105 are taken in via the multi-channel AD converter.

  The program memory 112C stores an input / output control program related to the in-vehicle sensor group 105 and the electric load group 106, and supplies drive control commands to the engine drive devices 161C and 171C by the drive control timers TIM1 to TIM4. A control program is stored.

  The cylinder selection gate circuits 116a to 116d are AND elements connected to the input part of the amplification output circuit 160 for driving the engine driving devices 161ac and 161bd, and a timer is connected to the input terminal of each AND element. An output switching command signal INHB is input. The output signal of the drive control timer TIM1 is input to the cylinder selection gate circuits 116a and 116c, and the output signal of the drive control timer TIM2 is input to the cylinder selection gate circuits 116b and 116d. As in the case of FIG. 1, cylinder selection gate signals OP1 to OP4 are input to the gate circuits 116a to 116d, respectively.

  The cylinder selection gate circuits 117a to 117d are AND elements connected to the input part of the amplification output circuit 170 for driving the engine driving devices 171ac and 171bd. An output switching command signal INHB is input. Further, the output signal of the drive control timer TIM3 is input to the cylinder selection gate circuits 117a and 117c, and the output signal of the drive control timer TIM4 is input to the cylinder selection gate circuits 117b and 117d. Cylinder selection gate signals OP1 to OP4 are connected to the gate circuits 117a to 117d, respectively.

  Note that the timer output switching command signal INHB generated by the microprocessor 110C is “H” when the authentication verification result of the start key 103 is valid, and the drive command for the engine driving device 161C is valid. To.

  As described above with reference to FIG. 2, the output signals of the drive control timers TIM1 to TIM4 become the logic level “H” after the variable first set time has elapsed after the crank angle sensor 105a operates, and the engine drive The driving devices 161C and 171C are driven, and after the variable second set time has elapsed, the logic level returns to “L” and the driving of the engine driving devices 161C and 171C is stopped.

  The cylinder selection gate signals OP1 to OP4 sequentially select the cylinders to be injected and ignited, and the logic level is “in a period during which the engine driving devices 161ac, 161bd, 171ac, 171bd of each cylinder are operating. H ". At least every time the crank angle sensor 105a is operated, the cylinder selection gate signal OP1 and the cylinder selection gate signal OP3 are alternately logically inverted, and the cylinder selection gate signal OP2 and the cylinder selection gate signal OP4 are alternately changed. The logic is inverted. Therefore, the logic levels of the cylinder selection gate signals OP1 and OP3 are not simultaneously “H”, and similarly, the logic levels of the cylinder selection gate signals OP2 and OP4 are not simultaneously “H”.

  The synchronization clock signal CLK generated by the microprocessor 110C is transmitted via the driver circuit 141a in the in-vehicle engine control apparatus 100C, the synchronization signal transmission line 11 as an external wiring, and the receiver circuit 141b in the key switch body 104. It is supplied to the immobilizer 104c.

  Communication data DATA between the microprocessor 110C and the immobilizer 104c is transferred to the immobilizer 104c via the driver circuit 142a in the in-vehicle engine control device 100C, the data communication line 12C, and the receiver circuit 142b in the key switch body 104. At the same time, it is transmitted from the immobilizer 104c to the microprocessor 110C via the driver circuit 143b in the key switch body 104, the data communication line 12C, and the receiver circuit 143a in the in-vehicle engine control device 100C.

  The authentication gate circuit 144 is an AND element that receives the drive control timer TIM1 and the inverted logic signal of the timer output switching command signal INHB as input signals. The output signal of the AND element is connected to the driver circuit 145a and data communication. The signal is supplied to the immobilizer 104c via the line 12C and the receiver circuit 145b in the key switch body 104.

  The drive control timer TIM1 generates and supplies a pulse width modulation signal PWM to the immobilizer 104c until the authenticity of the start key 103 is authenticated, and the immobilizer 104c is connected to the microprocessor 110C. Generates a radio signal having a frequency that is inversely proportional to the period of the pulse width modulation signal PWM transmitted from and an amplitude that is proportional to the duty of the pulse width modulation signal PWM (the ratio between the time and the period when the logic level is “H”) Then, wireless communication is performed with the transponder 104a.

  The drive control timer TIM1 is also used as an authentication control timer. During the period in which the pulse width modulation signal PWM is generated, the logic level of the timer output switching command signal INHB is “L”, and the authentication gate The pulse width modulation signal PWM is transmitted to the immobilizer 104c via the circuit 144. However, at this time, the cylinder selection gate circuits 116a and 116c are stopped by the timer output switching command signal INHB, so that the pulse width modulation signal PWM is not supplied to the engine driving device 161ac.

  When the output generation of the drive control timers TIM2 to TIM4 is stopped during the period when the logic level of the timer output switching command signal INHB is “L”, the interlock circuit indicated by the broken line in FIG. 119 becomes unnecessary. However, if the interlock circuit 119 is connected, the cylinder selection gate circuits 116b, 116d, 117a to 117d are stopped by the timer output switching command signal INHB. The output signals of the drive control timers TIM2 to TIM4 can be reliably stopped.

  However, in view of the fact that there is a problem of exhausting raw gas if fuel injection is performed without ignition, and abnormal ignition may occur if the ignition coil is cut off unexpectedly. It is necessary to consider the relationship between the operating states of the timers TIM1 to TIM4 and the timer output switching command signal INHB.

  The timer circuit unit 800n in the microprocessor 110C includes a counter circuit for generating the drive control timers TIM1 to TIM4, and details thereof will be described later with reference to FIG. Similarly, one of the timer circuit units 800n functions as a means for detecting the engine rotational speed Ne, and is used as a counter circuit for measuring the operating time interval (rotation period T0) of the crank angle sensor 105a.

Next, the timer circuit unit 800n shown in the microprocessor 110C of FIG. 7 will be described with reference to the block diagram of FIG. In FIG. 8, the timer circuit unit 800n and the timer output unit 804n are configured to be connected to the outside of the microprocessor 110C.
In FIG. 8, the same components as those described above (see FIG. 3) are denoted with the same reference numerals as those described above, or with “C” after the reference numerals.

  The timer circuit unit 800n representatively shows each timer circuit unit for generating the drive control timer TIMn (TIM1 to TIM4 in FIG. 7). The clock signal 113 for time measurement is a pulse train signal of a fixed time obtained by dividing a reference clock signal (not shown) supplied to the microprocessor 110C.

  The time counter 801 in the timer circuit unit 800n has a current value register and counts the time clock signal 113. As a result, the value of the current value register in the time counter 801 increases with time. The reset signal RST generated by the microprocessor 110C resets the current count value of the time counter 801 to zero when the logic level is “H”, and stops the input of the time signal by the time clock signal 113.

  The set value registers 802a and 802b (first and second set value registers) in the timer circuit unit 800n include memories in which timed target values are written by setting outputs SETa and SETb from the microprocessor 110C. The comparison circuits 803a and 803b (first and second comparison circuits) compare the count current value of the time counter 801 with the set values of the set value registers 802a and 802b, and when the comparison coincides, The timer output unit 804n composed of a circuit is set or reset. The output signal of the comparison circuit 803b (second comparison circuit) is supplied to the microprocessor 110C as the completion signal FIN.

  As will be described later with reference to FIGS. 9 and 10, the timer circuit unit 800n is used as a drive control timer (TIMn), used as an authentication control timer for generating a pulse width modulation signal PWM, or engine rotation cycle. Used to measure T0.

  Here, as a first example of the timer circuit unit 800n shown in FIG. 8, the control operation of the microprocessor 110C when measuring the rotation period T0 using the timer circuit 800rv will be described.

  First, the current count value of the time counter 801 is reset by the reset output RST, and when the detection signal of the crank angle sensor 105a input to the interrupt input terminal of the microprocessor 110C operates (L → H), The current count value of the time counter 801 is read by the read input RD. Immediately thereafter, the current count value is instantaneously reset again by the reset output RST, and the above operation is repeated thereafter. As a result, the value of the read input RD is obtained as a value proportional to the operation interval time (rotation period T0) of the crank angle sensor 105a.

  Next, as a second example of the timer circuit unit 800n, a control operation of the microprocessor 110C when the pulse width modulation signal PWM is generated using the timer circuit unit 800ac will be described.

  First, the OFF time (the time when the logic level is “L”) is written to the set value register 802a by the set outputs SETa and SETb, and the pulse period (set ON time + set OFF time) is set to the set value register 802b. Write. Subsequently, the count current value of the timer output unit 804ac (804n in FIG. 8) and the time counter 801 is instantaneously reset by the reset signal RST, and the logic output of the timer output unit 804n is set to “L”, and then the time measuring operation is started. To do.

  Thereafter, when the current count value of the time counter 801 reaches the set OFF time stored in the set value register 802a, the comparison circuit 803a generates the first comparison match output, sets the timer output unit 804n, and sets the timer The logic output of the output unit 804n is set to “H”.

  Further, when the time measurement progresses and the current count value of the time counter 801 reaches the pulse period (set ON time + set OFF time) stored in the set value register 802b, the comparison circuit 803b makes the next comparison match. The output is generated, the timer output unit 804n is reset, and the logic output of the timer output unit 804n is set to “L”.

  When the one-round operation is completed, the comparison coincidence output of the comparison circuit 803b is input to the microprocessor 110C as a completion signal FIN, and the microprocessor 110C generates the reset signal RST again. Thereafter, the same operation is repeatedly executed. To do. If the setting OFF time or the pulse period (setting ON time + setting OFF time) is desired to be changed while the pulse width modulation signal PWM is being generated, it can be reset by the setting outputs SETa and SETb. The above operation is the same when the timer circuit unit 800bd is used instead of the timer circuit unit 800ac as the timer circuit unit 800n.

  Next, as a third example of the timer circuit unit 800n, a control operation of the microprocessor 110C when generating a drive control signal for the engine driving devices 161C and 171C using the timer circuit unit 800ac will be described.

  First, the OFF time is written in the set value register 802a by the set outputs SETa and SETb, and the pulse period (set ON time + set OFF time) is written in the set value register 802b. Subsequently, the count output values of the timer output unit 804ac and the time counter 801 are continuously reset by the reset signal RST, and the logic output of the timer output unit 804ac is set to “L”.

  Thereafter, when the logic level of the detection signal of the crank angle sensor 105a connected to the interrupt input terminal of the microprocessor 110C becomes “H”, the microprocessor 110C stops generating the reset signal RST, and the time counter 801 The counting of the clock signal 113 for clocking is started.

  Thereafter, when the current count value of the time counter 801 reaches the set OFF time stored in the set value register 802a, the comparison circuit 803a generates the first comparison match output, sets the timer output unit 804ac, and outputs the timer output. The logic output of the unit 804ac is set to “H”.

  When the time measurement further proceeds and the count current value of the time counter 801 reaches the pulse period stored in the set value register 802b, the comparison circuit 803b generates the next comparison match output and resets the timer output unit 804n. The logic output of the timer output unit 804ac is set to “L”.

  When the one-round operation is completed, the comparison coincidence output of the comparison circuit 803b is interrupted and input to the microprocessor 110C as the completion signal FIN, and the microprocessor 110C continuously generates the reset signal RST until the crank angle sensor 105a operates again. Then, the operation of the time counter 801 is stopped. The above operation is the same when the timer circuit unit 800bd is used as the timer circuit unit 800n.

  As a different form of the timer circuit unit 800n, when the completion signal FIN is generated, the time counting operation of the time counter 801 is automatically stopped inside the timer circuit unit 800n to respond to the next operation of the crank angle sensor 105a. And may be configured to start timing. In this case, the microprocessor 110C supplies a mode selection command to the timer circuit unit 800n, and automatically restarts the timing operation in response to the completion signal FIN if it is desired to generate the pulse width modulation signal PWM. Can do.

Next, the operation of the third embodiment of the present invention shown in FIG.
In FIG. 7, when the power switch 103a is closed, the output contact 102a of the power relay is closed, and the power supply voltage Vb (= 10V to 16V is applied from the in-vehicle battery 101 to the in-vehicle engine control device 100C. The stabilized control power supply voltage Vcc (= 5V) is supplied to the microprocessor 110C via 120.

  The microprocessor 110C authenticates and verifies the correctness of the used start key 103 via the immobilizer 104c, and then continues the operation state of the in-vehicle sensor group 105 and the input / output control program stored in the program memory 112C. The electrical load group 106 is controlled based on the above. Further, the drive control timers TIM1 to TIM4 operate based on a drive control program for the engine drive devices 161C and 171C.

Next, an authentication verification operation and a drive control operation according to the third embodiment of the present invention will be described with reference to the flowchart of FIG. 9 together with FIGS.
9, steps 900 to 912 and 920 are the same processing as steps 400 to 412 and 420 described above (see FIG. 4), and the drive control unit 921 for the engine driving devices 161C and 171C performs steps 913 to 916. Only the point constituted by is different from the above (FIG. 4).

  First, when the microprocessor 110C starts operating (step 900), it is determined whether or not the initial operation completion flag is set (step 901), and it is determined that the operation is the initial operation (ie, YES). If it is determined that the operation is not the first operation (that is, NO), the process proceeds to step 912. The initial operation completion flag set in step 910 is reset when the power is turned on, and when the power switch 103a is closed, it is always determined as “YES” in step 901.

  In step 902, the microprocessor 110C communicates with the immobilizer 104c via the synchronization signal transmission line 11 and the data communication line 12C, and the pulse width modulation signal transmitted from the immobilizer 104c via the data communication line 12C. The communication data DATA regarding each value of the frequency and the amplitude is received.

  Subsequently, in step 903 (reading confirmation means), it is determined whether or not the request data read in step 902 matches the data stored in the program memory 112A, and the read information is normally matched. If it is determined (ie, YES), the process proceeds to step 904, and if it is determined that they do not match (ie, NO), the process proceeds to step 908.

  In step 904, the microprocessor 110C sets the logic level of the timer output switching command signal INHB to “L” to allow the signal to pass through the authentication gate circuit 144 and to select the cylinder selection gate circuits 116a to 116d, 117a to 117a. The logic output level of 117d is fixed to “L”, and the operation of the engine driving devices 161C and 171C (ignition coil or solenoid valve for fuel injection) is stopped.

  Subsequently, in step 905, the microprocessor 110C generates the pulse width modulation signal PWM using the drive control timer TIM1 configured by the timer circuit unit 800ac, and supplies the pulse width to the immobilizer 104c via the data communication line 12C. In order to transmit the modulation signal PWM, the time counter 801 of the timer circuit unit 800ac is reset, and an OFF time and a pulse period (ON time + OFF time) are set in the setting value registers 802a and 802b. Thereafter, the processing shifts to processing in which the pulse width modulation signal PWM is generated by the interrupt control operation of the microprocessor 110C shown in FIG.

  The immobilizer 104 c transmits to the transponder 104 a a radio signal having a frequency inversely proportional to the period of the received pulse width modulation signal PWM and an amplitude proportional to the duty of the pulse width modulation signal PWM, to the start key 103. Read the assigned password.

  The microprocessor 110C stops transmission of the pulse width modulation signal PWM after a predetermined time has elapsed, and then reads the personal identification number from the immobilizer 104c via the data communication line 12C in step 906. Subsequently, in step 907 (authentication verification means), it is verified whether the code number stored in the program memory 112C matches the code number read in step 906, and they match (that is, YES). If it is determined that the key is a valid start key 103, the process proceeds to step 910, and if it is determined that they do not match (that is, NO), the process proceeds to step 908.

  If a valid password is stored in the immobilizer 104c, authentication verification may be performed by the immobilizer 104c, and the determination result may be transmitted to the microprocessor 110C via the data communication line 12C.

  In step 908 (starting stop means), the starting circuit of the starting motor 108 is shut off, and in the subsequent step 909 (output prohibiting means), the outputs of the drive control timers TIM1 to TIM4 are reset and the logic output level is set to “ L "is maintained.

  In step 910, the microprocessor 110C sets an initial operation completion flag, and in subsequent step 911, the logic level of the timer output switching command signal INHB is set to “H”, and the logic level of the output signal of the authentication gate circuit 144 is set. While being fixed to “L”, the cylinder selection gate circuits 116a to 116d and 117a to 117d are allowed to pass through, and the operation of the engine driving devices 161C and 171C (ignition coil or solenoid valve for fuel injection) is made effective. To do.

  Subsequently, in step 912, the engine rotation operation T0 detected in step 1011 (described later with reference to FIG. 10) is, for example, 200 ms or less (the engine rotation speed Ne is 300 rpm or more) due to the engine start operation by the starter motor 108. It is determined whether or not.

  If it is determined in step 912 that the engine rotational speed Ne <predetermined rotational speed (that is, NO), the routine proceeds to step 913 in the drive control means 921, and it is determined that the engine rotational speed Ne ≧ the predetermined rotational speed (that is, YES). Then, the process proceeds to step 915 in the drive control unit 921.

  In step 913, the drive control timers TIM1 and TIM2 are reset to set the logic output of the timer output unit 804n to “L”. In the subsequent step 914, the drive control timers TIM3 and TIM4 are reset to output the timer output. The logic output of the unit 804n is set to “L”.

  In steps 915 and 916, the appropriate values of the valve opening start timing T11 and the excitation start timing T13, the appropriate values of the valve opening period T12 and the excitation period T14, the valve opening start timing T21 and the excitation start timing T23 in FIG. Appropriate values and appropriate values for the valve opening period T22 and the excitation period T24 are calculated. The set OFF time and the set ON time calculated in steps 915 and 916 are transferred and written to the set value registers 802a and 802b in the timer circuit unit 800n at a predetermined time (described later with reference to FIG. 10).

Next, an interrupt control operation according to the third embodiment of the present invention will be described with reference to the flowchart of FIG.
In FIG. 10, steps 1000 to 1002, 1010, and 1020 are the same processes as steps 500 to 502, 510, and 520 described above (see FIG. 5). In this case, the operating time setting unit 1021 is configured by steps 1005 and 1015.

  First, the microprocessor 110C performs an interrupt operation in step 1000 when the detection signal of the crank angle sensor 105a or the completion signal FIN generated by the timer circuit unit 800n is input to the interrupt input terminal as an interrupt operation command. In the subsequent step 1001, the current operation state is temporarily saved, and when the return process in step 1020 is executed, the process returns to the original control flow so that the calculation can be continued.

  In the subsequent step 1002, it is determined whether or not the initial operation completion flag is set in step 910 in FIG. 9, and if it is determined that the setting is not completed (that is, NO), the process proceeds to step 1003 and the setting is completed ( That is, if it is determined as YES), the process proceeds to step 1010.

  In step 1003, it is determined whether or not the logical level of the completion signal FIN in FIG. 8 has become “H”, and it is determined that the logical level of the completion signal FIN has become “H” (that is, YES). For example, the process proceeds to step 1005, and if it is determined that the logic level of the completion signal FIN is not “H” (that is, NO), the process proceeds to a return process (step 1020). Note that the completion signal FIN is based on the fact that the time counter 801 has started counting in step 905 in FIG.

  In step 1005, an OFF time and a pulse period (ON time + OFF time) are set in the setting value registers 802a and 802b by setting outputs SETa and SETb. In the following step 1009, the current count value of the time counter 801 and the timer output unit 804n are instantaneously reset by the reset command RST and the logic output is maintained at “L”, and then the process proceeds to the return process (step 1020). .

  In step 1010, which is executed when the determination result in step 1002 is “YES”, it is determined whether or not the interrupt operation is started by the operation of the crank angle sensor 105a, and the interrupt operation by the operation of the crank angle sensor 105a is determined. If it is determined that the operation is started (that is, YES), the process proceeds to step 1015. If it is determined that the interrupt operation is not started due to the operation of the crank angle sensor 105a (that is, NO), the process proceeds to step 1013.

  In step 1015, an OFF time and a pulse period are set for the set value registers 802a and 802b by the set outputs SETa and SETb to each timer circuit unit 800n. In the subsequent step 1019, the reset current value of the time counter 801 and the timer output unit 804n are instantaneously reset by a reset command RST, or the reset state held in step 1014 described later is canceled, and then the process proceeds to step 1011. Transition.

  In step 1011, the count current value of the time counter 801 in the timer circuit unit 800n for measuring the rotation period T0 is read, and then the current value register in the time counter 801 is instantaneously reset and returned by a reset command RST. The process proceeds to processing (step 1020).

  In step 1013, it is determined whether or not the logic level of the completion signal FIN in FIG. 8 has become “H”, and it is determined that the logic level of the completion signal FIN has become “H” (that is, YES). For example, the process proceeds to step 1014, and if it is determined that the logic level of the completion signal FIN is not “H” (that is, NO), the process immediately proceeds to the return process (step 1020).

  In step 1014, the logic level of the reset signal RST is maintained at “H”, the count current value of the time counter 801 in the timer circuit unit 800n is continuously reset, and the reset of the timer output unit 804n is held. The process proceeds to return processing (step 1020).

  As described above, the in-vehicle engine control apparatus 100C according to the third embodiment of the present invention is driven by the in-vehicle battery 101 and controls the driving of the engine driving devices 161C and 171c including at least one of the fuel injection solenoid valve and the ignition coil. The start key 103 is provided with a means 921, a program memory 112C storing a control program serving as an authentication verification means (step 907) for the start key 103, and a microprocessor 110C cooperating with the program memory 112C. An immobilizer 104c for reading the personal identification number of the start key 103 with a radio signal is connected via the transponder 104a.

  The microprocessor 110C includes a plurality of timer circuit units 800n and a timer output unit 804n, and the program memory 112C stores a control program serving as an operation time setting unit 1021 and a timer output switching unit (step 911) for the timer circuit unit 800n. Including.

  The timer circuit unit 800n includes a time counter 801 that counts the time clock signal 113, set value registers 802a and 802b, and the current count value of the time counter 801 to the target set value stored in the set value registers 802a and 802b. The comparators 803a and 803b generate a comparison coincidence output and drive the timer output unit 804n.

  The timer output unit 804n includes an output circuit that generates a logic output corresponding to predetermined ON and OFF times variably set in the set value registers 802a and 802b by the microprocessor 110C. The operation time setting means 1021 transfers and stores any one of the OFF time data, the ON time data, and the ON / OFF total time to the setting value registers 802a and 802b, and at the start of time measurement, the current count value of the time counter 801 To reset.

  The authentication verification unit 907 reads the password using a radio signal having a frequency and amplitude corresponding to the period and duty of the pulse width modulation signal PWM transmitted from the microprocessor 110C, and the read password is stored in the program memory 112C. Alternatively, an authentication determination is made as to whether the correct answer code stored in advance in the immobilizer 104c matches.

  The pulse width modulation signal PWM is generated by the timer circuit unit 800n, the operation time setting unit 1021, and the timer output unit 804n, and is composed of a continuous pulse signal having a predetermined OFF time and ON time.

  The timer output switching means 911 generates a timer output switching command signal INHB and outputs a timer circuit unit 800n used for generating the pulse width modulation signal PWM when the authentication determination is a coincidence determination to the drive control timer. Switching is used as TIM1.

  The output signal of the drive control timer TIMn is generated by the timer circuit unit 800n, the operation time setting means 1021, and the timer output unit 804n, and starts to operate in synchronization with the detection signal of the crank angle sensor 105a, corresponding to the set OFF time. The timer output is generated after elapse of the first set time, and the timer output is stopped after elapse of the second set time corresponding to the set ON time. As a result, the engine driving devices 161C and 171C are driven by the timer output, and one of the timer circuit units 800n is selectively used in the authentication verification unit 907 and the drive control unit 921, and the matching determination is performed as a result of the authentication verification. Is not switched to the drive control means 921, and output generation of the drive control means 921 is prohibited.

  In addition, the timer circuit unit 800n sets the time counter 801 for counting the time clock signal 113, the set value registers 802a and 802b (first and second set value registers), and the current count value of the time counter 801. Comparison circuits 803a and 803b (first and second comparison circuits) that generate first and second comparison coincidence outputs when the target set values stored in the value registers 802a and 802b are reached, and a timer output unit And a timer output circuit corresponding to 804n.

  The timer output unit 804n is set when the OFF time stored in the set value register 802a (first set value register) has elapsed after the count current value of the time counter 801 is reset, and the set value register 802b. In response to the total value of the ON time and OFF time stored in the (second set value register), the flip-flop circuit is reset when a predetermined ON time elapses.

  Therefore, by using the clock counter 801 that counts the clock signal 113 for clocking at high speed, the control burden on the microprocessor 110C can be reduced, and a highly accurate timer can be obtained, and the timer output unit 804n is provided in the timer circuit unit 800n. Thus, the control burden on the microprocessor 110C can be further reduced.

  Further, the microprocessor 110C transmits a pulse width modulation signal PWM to the immobilizer 104c, and during the period in which the immobilizer 104c reads the password of the start key 103, data communication between the immobilizer 104c and the microprocessor 110C. When it is estimated that the immobilizer 104c has finished reading the code number, the transmission of the pulse width modulation signal PWM is stopped, and the time division operation is performed so as to obtain the code number information or the match determination information from the immobilizer 104c. . Further, since the data communication line 12C between the microprocessor 110C and the immobilizer 104c is the same line that is also used as the transmission line of the pulse width modulation signal PWM, a high-level authentication verification can be performed without increasing the number of signal lines. It can be performed.

  Further, the period and duty value of the pulse width modulation signal PWM are stored in both the program memory 112C and the immobilizer 104c, and the program memory 112C includes a control program serving as a read confirmation unit (step 903). The read confirmation means (step 903) reads the cycle and duty stored in advance in the immobilizer 104c, and when the read data (read data) matches the correct data stored in the program memory 112C, Enable transmission of the pulse width modulation signal PWM from the processor 110C. Accordingly, it is possible to prevent an unauthorized immobilizer from being used.

  The output signal of the drive control timer TIM1 is generated by the timer circuit unit 800n, the operation time setting unit 1021 and the timer output unit 804n, and gives an energization command to the ignition coil of the engine, and the detection signal of the crank angle sensor 105a. The operation is started synchronously, a timer output is generated after the first set time corresponding to the set OFF time has elapsed, the excitation to the ignition coil is started, and the timer is started after the second set time corresponding to the set ON time has elapsed. The output is stopped and the ignition coil is turned off to ignite. Therefore, the pulse width modulation signal PWM can be easily generated by changing the operation start command of the ignition control drive control timer that starts operation in synchronization with the operation of the crank angle sensor 105a.

  The output signal of the drive control timer TIM1 is generated by the timer circuit unit 800n, the operation time setting unit 1021, and the timer output unit 804n, and an energization command is given to the fuel injection solenoid valve to detect the detection signal of the crank angle sensor 105a. The operation starts in synchronization with the first setting time after the first set time corresponding to the set OFF time has elapsed, the fuel injection solenoid valve is driven to open, and the second setting corresponding to the set ON time. After a lapse of time, the timer output is stopped and the fuel injection solenoid valve is returned to the closed state. Thus, since the fuel supply timing and the fuel supply period are determined by the timer output, the operation start command of the drive control timer for fuel injection control that starts operation in synchronization with the operation of the crank angle sensor 105a is changed. The pulse width modulation signal PWM can be easily generated.

  The microprocessor 110C includes drive control means 921 for both the first and second engine driving devices 161C and 171C (either the ignition coil or the fuel injection solenoid valve), and the first engine driving device For 161C, first and second drive control timers TIM1 and TIM2 are used corresponding to the odd-ordered cylinder and the even-ordered cylinder that do not operate adjacently.

  For the second engine drive device 171C, the third and fourth drive control timers TIM3 and TIM4 are used corresponding to the odd-order cylinder and the even-order cylinder that do not operate adjacently. Yes. Each of the output circuits of the first to fourth drive control timers TIM1 to TIM4 is provided with a plurality of cylinder selection gate circuits 116a to 116d and 117a to 117d for selecting the corresponding cylinder.

  Any one of the first to fourth drive control timers TIM1 to TIM4 is also used as the authentication control timer TIM1 for generating the pulse width modulation signal PWM to be transmitted to the immobilizer 104c.

  The output circuit of the authentication control timer TIM1 is connected to an authentication gate circuit 144 that is selectively operated by the timer output switching command signal INHB generated by the timer output switching means (step 911), and the authentication verification means (step 907). Until the collation coincidence determination is performed, the pulse width modulation signal PWM can be transmitted through the authentication gate circuit 144.

  In addition, some or all of the cylinder selection gate circuits 116a to 116d and 117a to 117a include a cylinder selection gate circuit 116a and 116c provided in the output circuit of the drive control timer TIM1 that is also used as an authentication control timer. 117d prohibits the timer output of the drive control timers TIM1 to TIM4.

  Accordingly, since the ignition control and the fuel injection control during the authentication verification process are stopped in the engine starting process, it is possible to suppress the load current of the in-vehicle battery 101 and improve the cold starting ability. That is, until the authentication verification is normally completed, unnecessary discharge of the in-vehicle battery 101 can be suppressed and the low-pressure start characteristic and the cold start characteristic can be improved. Further, the authentication verification can be performed without deteriorating the cold start characteristic of the engine by the in-vehicle battery 101 whose charging state is not good.

  Further, the program memory 112c includes a control program serving as an output prohibition unit (step 909). The output prohibition unit (step 909) does not match the authentication determination result with the case where the authentication verification unit (step 907) is performing the authentication determination. In response to the determination, output generation of the drive control timers TIM2 to TIM4 excluding the authentication control timer TIM1 is stopped. Therefore, even if the normal authentication result is not obtained, the rotation operation of the starting motor 108 is performed, but the ignition control and the fuel injection control are stopped, so that the engine does not rotate independently and is operated illegally. This can be prevented.

It is a circuit block diagram which shows the vehicle-mounted engine control apparatus which concerns on Embodiment 1 of this invention. 2 is a timing chart illustrating output characteristics of a drive control timer in FIG. 1. FIG. 2 is a block diagram illustrating a timer circuit unit and a timer output unit in FIG. 1. It is a flowchart which shows the authentication collation operation | movement and drive control operation | movement by Embodiment 1 of this invention. It is a flowchart which shows the interrupt control operation | movement by Embodiment 1 of this invention. It is a circuit block diagram which shows the vehicle-mounted engine control apparatus which concerns on Embodiment 2 of this invention. It is a circuit block diagram which shows the vehicle-mounted engine control apparatus which concerns on Embodiment 3 of this invention. FIG. 8 is a block diagram illustrating a timer circuit unit and a timer output unit in FIG. 7. It is a flowchart which shows the authentication collation operation | movement and drive control operation | movement by Embodiment 3 of this invention. It is a flowchart which shows the interrupt control operation | movement by Embodiment 3 of this invention.

Explanation of symbols

  12A Data communication line, 12C Data communication line and PWM signal transmission line, 100A, 100B, 100C In-vehicle engine control device, 101 In-vehicle battery, 103 Start key, 103b Start switch, 104 Key switch body, 104a Transponder, 104b, 104c Immobilizer 105a, crank angle sensor, 107 electromagnetic relay, 107b exciting coil, 108 starter motor, 110, 110C microprocessor (CPU), 112A, 112B, 112C program memory, 113 clock signal for timing, 116a-116d gate circuit for cylinder selection, 117a to 117d Cylinder selection gate circuit, 130 series switching element, 137 auxiliary switching element, 144 authentication gate circuit, 161A, 161B engine driving device, 61C first engine driving device, 171C second engine driving device, 300n, 800n, 300ac, 300bd timer circuit unit, 301, 801 time counter, 302 set value register, 303 comparison circuit, 304n, 804n timer output unit , 403, 903 Reading confirmation means, 407, 907 Authentication verification means, 408, 908 Start stop means, 409, 909 Output prohibition means, 411, 911 Timer output switching means, 421, 921 Drive control means, 521, 1021 Operation time setting Means 522 flag inversion means 802a first set value register 802b second set value register 803a first comparison circuit 803b second comparison circuit CMP comparison coincidence output INHB timer output switching command signal PWM Pulse width modulation signal, T M1~TIM4, the drive control for the timer.

Claims (12)

Engine drive connected to various sensors including a crank angle sensor for detecting the operating state of the vehicle-mounted engine, supplied with power from the vehicle-mounted battery, and comprising at least one of a fuel injection solenoid valve and an ignition coil according to the driving state Drive control means for controlling the equipment,
A program memory storing a control program serving as an authentication verification unit for the engine start key, and a microprocessor cooperating with the program memory;
An in-vehicle engine control device connected to an immobilizer for reading out a personal identification number of the start key with a radio signal via a transponder provided in the start key,
The microprocessor cooperates with a plurality of timer circuit units and a timer output unit,
The program memory includes a control program serving as an operation time setting unit and a timer output switching unit for the timer circuit unit,
The timer circuit unit includes a clock counter for counting a clock signal for clocking, a set value register, and a comparison coincidence output when the current count value of the clock counter reaches a target set value stored in the set value register. A comparator circuit that generates and drives the timer output unit;
The timer output unit generates a logic output corresponding to a predetermined ON time and OFF time variably set in the set value register by the microprocessor,
The operation time setting means transfers ON time data and OFF time data corresponding to the ON time and the OFF time, or ON / OFF total time data and ON time data or OFF time data to the set value register. In addition to storing, at the start of timing, reset the current count value,
The authentication verification means reads out and reads out the personal identification number of the start key via the immobilizer with a radio signal having a frequency and an amplitude corresponding to the period and duty of the pulse width modulation signal transmitted from the microprocessor. An authentication determination is performed as to whether or not the personal identification number matches a correct personal identification number stored in advance in the program memory or the immobilizer,
The pulse width modulation signal is generated by the timer circuit unit, the operation time setting unit, and the timer output unit, and includes a continuous pulse signal having a predetermined OFF time and ON time,
The timer output switching means generates a timer output switching command signal when the authentication determination is a coincidence determination, and controls the timer circuit unit used for generating the pulse width modulation signal as a drive control timer. Use as switching and
The drive control timer includes the timer circuit unit, the operation time setting means, and the timer output unit. The timer circuit unit starts operating in synchronization with a detection signal of the crank angle sensor, and is set to OFF. The first comparison coincidence output is generated after elapse of the first set time corresponding to the time, and the next comparison coincidence output is generated after elapse of the second set time corresponding to the set ON time. Timer output is generated during the period from when the match output occurs until the next comparison match output occurs,
The engine driving device is driven by a timer output from the timer output unit,
One of the plurality of timer circuit units is selectively used in the authentication verification unit and the drive control unit, and until a match determination is obtained as a result of the authentication verification by the authentication verification unit, An on-vehicle engine control device characterized in that selection switching to the drive control means is not performed and output generation of the drive control means is prohibited. The timer output unit is generated by flag inversion means stored in the program memory,
The operation time setting means alternately transfers and stores the OFF time data or the ON time data to the set value register, and resets the current count value at the start of timing,
The flag inversion means inverts the logic output every time the comparator circuit of the time counter generates a comparison coincidence output, and the logic level of the logic output becomes “L” in the set period of the OFF time data. The in-vehicle engine control device according to claim 1, wherein a flag in which a logic level of the logic output is “H” is generated as the timer output in a set period of ON time data. The timer circuit unit includes first and second setting value registers as the setting value register, and includes first and second comparison circuits as the comparison circuit,
The first comparison circuit generates a first comparison coincidence output when the current count value reaches a target set value stored in the first set value register;
The second comparison circuit generates a second comparison coincidence output when the current count value reaches a target set value stored in the second set value register,
The timer output unit is set when the OFF time stored in the first set value register elapses after the current count value is reset, and the ON time stored in the second set value register The in-vehicle engine control device according to claim 1, wherein the on-vehicle engine control device is configured by a flip-flop circuit that is reset when a predetermined ON time elapses in response to a total value of the time and the OFF time. The microprocessor transmits the pulse width modulation signal to the immobilizer, and does not perform data communication with the immobilizer during a period in which the immobilizer reads the password of the start key, and the immobilizer At the time when it is estimated that the reading is completed, the transmission of the pulse width modulation signal is stopped, and the time division operation is performed so as to obtain the personal identification number information or the coincidence determination information from the immobilizer,
The in-vehicle engine control device according to claim 1, wherein a communication line between the microprocessor and the immobilizer and a transmission line for the pulse width modulation signal are configured by the same line. Each value of the period and duty of the pulse width modulation signal is stored in advance in both the program memory and the immobilizer,
The program memory includes a control program serving as a read confirmation unit,
The reading confirmation means reads the cycle and duty stored in the immobilizer as read data, and checks whether the read data matches the correct data of the cycle and duty stored in the program memory. ,
The in-vehicle engine control device according to claim 1 or 4, wherein the microprocessor transmits the pulse width modulation signal when the read data matches the correct answer data. The drive control timer issues an energization command to the ignition coil, starts operating in synchronization with a detection signal of the crank angle sensor, generates the timer output after the first set time elapses, and generates the ignition The in-vehicle engine control device according to claim 1, wherein excitation of the coil is started, and after the second set time has elapsed, the timer output is stopped, the excitation of the ignition coil is cut off, and ignition is performed. The engine has a plurality of cylinders that are sequentially controlled to be ignited,
The drive control timer includes first and second drive control timers,
The output signal of the first drive control timer is sequentially distributed and supplied to the plurality of cylinders via a cylinder selection gate circuit that discriminates adjacent ignition cylinders.
For a cylinder with an odd ignition number, one timer circuit portion of the plurality of timer circuit portions is used,
For the cylinders whose ignition order is an even number, the second drive control timer by the other one of the plurality of timer circuit units is used,
The in-vehicle engine control apparatus according to claim 6, wherein an output signal of the second drive control timer is sequentially distributed and supplied to the even-numbered cylinders via the cylinder selection gate circuit. The drive control timer issues an energization command to the fuel injection solenoid valve, starts operation in synchronization with a detection signal of the crank angle sensor, and generates the timer output after the first set time has elapsed. The fuel injection solenoid valve is driven to open, the timer output is stopped after the second set time has elapsed, and the fuel injection solenoid valve is returned to the closed state,
The in-vehicle engine control apparatus according to claim 1, wherein a fuel supply timing and a fuel supply period for the engine are determined by a timer output of the drive control timer. The engine has a plurality of cylinders that are sequentially subjected to fuel injection control,
The drive control timer includes first and second drive control timers,
The output signal of the first drive control timer is sequentially distributed and supplied to the plurality of cylinders via a cylinder selection gate circuit that discriminates adjacent injection cylinders.
For a cylinder with an odd number of fuel injection orders, one timer circuit portion of the plurality of timer circuit portions is used,
For the cylinders with an even number of fuel injection orders, the second drive control timer by the other one of the plurality of timer circuit units is used,
The on-vehicle engine control device according to claim 8, wherein the output signal of the second drive control timer is sequentially distributed and supplied to the even-numbered cylinders via the cylinder selection gate circuit. The start switch responsive to the start key further comprises a series opening / closing element and an auxiliary opening / closing element,
The series open / close element is connected in series to an excitation coil of an electromagnetic relay that connects the vehicle battery and the engine starter motor, and conducts when the engine start switch is closed to start the engine,
The auxiliary switching element responds to the determination result by the authentication verification means being inconsistent and prohibits the series switching element from conducting, and prevents the series switching element from conducting when the microprocessor is inoperative. The vehicle-mounted engine control device according to claim 1, wherein bias is applied to a relationship that does not hinder. The engine has a plurality of cylinders that are sequentially subjected to fuel injection control and ignition control,
The engine driving device is a first engine driving device that is one of the fuel injection solenoid valve or the ignition coil, and a second engine driving device that is the other of the fuel injection solenoid valve or the ignition coil. Including equipment,
The drive control timer includes first to fourth drive control timers,
The drive control means controls both the first and second engine driving devices,
For the first engine drive device, the first and second drive control timers are used corresponding to the odd-ordered cylinder and the even-ordered cylinder that do not operate adjacently,
For the second engine drive device, the third and fourth drive control timers are used corresponding to the odd-order cylinder and the even-order cylinder that do not operate adjacently,
Each of the output circuits of the first to fourth drive control timers is provided with a plurality of cylinder selection gate circuits for selecting the corresponding cylinders,
Any one of the first to fourth drive control timers is also used as an authentication control timer for generating the pulse width modulation signal transmitted to the immobilizer,
The authentication control timer output circuit is connected to an authentication gate circuit that is selectively operated by a timer output switching command signal generated by the timer output switching means.
Until the authentication verification unit performs verification match determination, the pulse width modulation signal can be transmitted through the authentication gate circuit, and
Among the plurality of cylinder selection gate circuits, a part or all of the cylinder selection gate circuits including a cylinder selection gate circuit provided in an output circuit of a dual-purpose drive control timer that is also used as the authentication control timer The on-board engine control device according to claim 6 or 8, wherein a timer output of the drive control timer is prohibited. The program memory includes a control program serving as output prohibiting means,
The output prohibiting means acts when the authentication collating means is performing authentication determination and when the authentication determination result is a mismatch determination, and stops output generation of a drive control timer other than the authentication control timer. The in-vehicle engine control device according to claim 11.

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