JP4239134B2 - Method for manufacturing dielectric isolation wafer for solar cell - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  This inventionFor solar cellsThe method of manufacturing a dielectric isolation wafer of the present invention, more specifically, diffuses light colliding with the bottom surface of the dielectric isolation silicon island, and increases the number of photons that pass through the power generation region of the PN junction to increase power generation efficiency.For solar cellsThe present invention relates to a method for manufacturing a dielectric isolation wafer.
[0002]
[Prior art]
  In recent years, the PN inside the dielectric isolation silicon island (active layer)JoiningA dielectric isolation wafer having a function of a solar cell in which a power generation region portion made of the above is formed has been developed. These semiconductor chips having a plurality of dielectric isolation silicon islands are usually cut and separated one by one by a dicing process, and each is used as a small solar cell array.
  A bonded dielectric isolation wafer is known as a kind of dielectric isolation wafer. This is a laminate of an active layer wafer having a dielectric-isolated silicon island formed on the surface and a support substrate wafer that supports the wafer from the back side.
  Conventionally, the silicon wafer as the material of the active layer wafer has been a mirror-finished wafer having a mirror-finished surface. After bonding, the surface of the silicon wafer becomes the bottom surface of the dielectric isolation silicon island. Therefore, the bottom surface of the dielectric isolation silicon island is mirror finished.
[0003]
  This mirror-finished wafer is usually produced by subjecting a silicon ingot pulled up by the CZ method to the steps of slicing, chamfering, lapping, etching, polishing, and cleaning.
  The mirror surface wafer thus obtained then forms a dielectric separation groove on the mirror-finished surface of the silicon wafer, and forms a dielectric isolation oxide film on the surface of the silicon wafer including the dielectric separation groove, Further, a plurality of dielectrics obtained by laminating a high-temperature polysilicon layer on the surface of the dielectric isolation oxide film by, for example, the CVD method, then grinding and polishing the silicon wafer from the back side, and separating the polished surface with the dielectric isolation oxide film An isolated silicon island appeared, and a power generation region portion formed of a PN junction was formed in the formation region of the dielectric isolated silicon island of this silicon wafer to form an active layer wafer.
[0004]
  Among these, the dielectric separation groove forming step is performed by first covering both front and back surfaces of a silicon wafer with a mask oxide film, and a positive resist film having a thickness of 1.0 to 2.0 μm with a window on the surface of the mask oxide film. Alternatively, a negative resist film is provided, then a window with a predetermined pattern is formed in the mask oxide film using this resist film as a mask, and a portion of the silicon wafer exposed from this window is anisotropically etched to form a dielectric separation groove. Was.
  In addition, according to the dielectric isolation wafer having the function of the solar cell of the prior art, the dielectric isolation oxidation from the depth of the dielectric isolation silicon island where the power generation region portion is formed, in other words, from the surface of the dielectric isolation silicon island. The depth (thickness) to the film was usually about 30 to 60 μm.
[0005]
[Problems to be solved by the invention]
  Thus, in the conventional dielectric isolation wafer, the bottom surface of the dielectric isolation silicon island is mirror-finished. For this reason, the light incident from the outside is only regularly reflected when it passes through the inside of the dielectric isolation silicon island and collides with the dielectric isolation oxide film. As a result, the number of photons passing through the photoelectric conversion unit is small, and only low power generation efficiency can be obtained.
  Further, in the production of a conventional dielectric separation wafer, a mirror surface wafer has been used as an active layer wafer. Therefore, a polishing process that requires a long processing time after etching is required. As a result, the manufacturing time of the dielectric isolation wafer, and thus the manufacturing time of the solar cell, is prolonged and the cost is high.
  Conventionally, the depth from the surface of the dielectric isolation silicon island to the dielectric isolation oxide film has been as deep as about 30 to 60 μm. As a result, the incident light was significantly attenuated while traveling through the island, and the number of photons passing through the power generation region was greatly reduced.
[0006]
  Therefore, the inventor, if the bottom surface of the dielectric isolation silicon island is an etching surface, the light collides with the bottom surface of the dielectric isolation silicon island and diffusely reflects, and the number of photons passing through the power generation region increases. The present invention was completed by discovering that the power generation efficiency of the solar cell is increased.
  In addition, the inventor can suppress a decrease in power generation efficiency due to the depth of the dielectric isolation silicon island if the depth from the surface of the dielectric isolation silicon island to the dielectric isolation oxide film is 30 μm or less. It has been found that the manufacturing process of the dielectric isolation wafer can be simplified by using the bottom surface of the island as an etching surface, and the present invention has been completed.
  In addition, the inventor has developed a new patterning technique using a photolithographic process on the etched surface, which is suitable for the production of the dielectric isolation wafer of the present invention. Enabled etching.
[0007]
OBJECT OF THE INVENTION
  According to the present invention, light colliding with the bottom surface of the dielectric isolation silicon island can be diffusely reflected to improve power generation efficiency.For solar cellsAn object of the present invention is to provide a method for manufacturing a dielectric isolation wafer.
  In addition, the present invention can manufacture a dielectric isolation wafer for solar cells using existing manufacturing equipment, and further reduce the number of manufacturing steps, thereby reducing the manufacturing time and cost of solar cells. It is an object of the present invention to provide a method for manufacturing a dielectric isolation wafer for a solar cell that can achieve the above.
[0008]
[Means for Solving the Problems]
  Claim1According to the invention described in the above, the step of forming a dielectric separation groove on the etched surface on the front side of the etched silicon wafer, and the formation of a dielectric separation oxide film on the surface of the silicon wafer including the dielectric separation groove A step of laminating a polysilicon layer on the surface of the dielectric isolation oxide film, and grinding and polishing the silicon wafer from the back side, and a plurality of dielectrics separated on the polished surface by the dielectric isolation oxide film A step of exposing a body-isolated silicon island, and a step of forming a power generation region portion made of a PN junction in a region where the dielectric-isolated silicon island of the silicon wafer is formed.For solar cellsIt is a manufacturing method of a dielectric isolation wafer.
  As long as the etched silicon wafer (hereinafter, etched wafer) is a silicon wafer whose exposed surface is finally etched, a processing process at an intermediate stage is not limited. For example, a silicon ingot pulled up by the CZ method may be sliced, lapped, and etched. Furthermore, the lapping process may be omitted and the sliced silicon wafer may be etched.
In addition, the material of a solar cell is various dielectric isolation wafers having a dielectric isolation silicon island in which a power generation region portion is formed.
The type of dielectric isolation wafer is not limited. For example, a dielectric single silicon island may be formed on the surface of one single crystal silicon wafer. Alternatively, a bonded dielectric isolation wafer in which a support substrate wafer that supports the active layer wafer with a dielectric isolation silicon island is bonded to the back surface of the active layer wafer may be used.
The internal structure of the dielectric isolation silicon island is not limited. In short, at least one power generation region portion is formed on the surface layer portion, and the dielectric isolation oxide film that reflects light incident from the outside to the silicon portion on the back side of the power generation region portion of this dielectric isolation silicon island Should just be formed. The thickness of the dielectric isolation silicon island is not limited.
The depth from the surface of the dielectric isolation silicon island to the dielectric isolation oxide film, that is, the depth of the active layer is not limited. For example, it may be 30 μm or more or smaller.
The structure of the PN junction is not limited. Each thickness of the P-type layer and the N-type layer is, for example, 1 to 5 μm, and is appropriately determined depending on the device to be manufactured.
The glossiness of the bottom surface of a preferable dielectric isolation silicon island is 30 to 150%. Even if it is less than 20%, good power generation efficiency can be obtained, but it is difficult to achieve a glossiness of less than 20% during alkali etching. On the other hand, if it exceeds 200%, the bottom surface of the dielectric-isolated silicon island becomes too close to the mirror surface, and the number of photons passing through the power generation region does not increase so much. According to a gloss measuring instrument manufactured by Nippon Denshoku Co., Ltd., the glossiness of the mirror surface is 330%. The smaller the value, the rougher the measured surface.
The depth from the surface of the dielectric isolation silicon island to the dielectric isolation oxide film is preferably 30 μm or less.
When this depth exceeds 30 μm, the silicon portion of the dielectric-isolated silicon island becomes too thick, and the degree of attenuation of light traveling through the island increases. As a result, the number of photons reaching the power generation area decreases, and power generation efficiency decreases.
[0009]
  The etched wafer may be an acid-etched wafer or an alkali-etched wafer. Among these, at the time of acid etching of the silicon wafer, for example, a mixed acid solution in which hydrofluoric acid and nitric acid are mixed can be used. At that time, for example, the semiconductor wafer is immersed in a mixed acid solution (room temperature to 50 ° C.) stored in an etching tank to remove distortion on both the front and back surfaces of the wafer due to wrapping and distortion on the outer periphery of the wafer due to chamfering. Usually, etching is 10 to 20 μm on one side and 20 to 40 μm on both sides. When an acid-etched wafer is carried out, bubbles are generated on the exposed surface of the wafer, and undulations with minute irregularities having a period of about 0.05 to 0.20 mm and a height of about 100 nm are generated on both surfaces of the wafer (glossiness 60 to 180%). .
  On the other hand, at the time of alkali etching of the silicon wafer, etching is performed using an alkali etching solution such as NaOH, KOH, ammonia, or the like. The etching temperature is usually 60 to 90 ° C. Even in the case of this alkali etching, bubbles are generated on the exposed surface of the wafer, and the traces remain as fine irregularities of about 1.0 to 2.0 μm in terms of peak to valley (glossiness of 20 to 100%).
[0010]
  When forming the dielectric separation groove on the surface of the etched wafer, an anisotropic etching technique is usually employed. For anisotropic etchant, KOH (IPA / KOH / H₂O), KOH (KOH / H₂ O), KOH (hydrazine / KOH / H₂ An alkaline etching solution such as O) can be employed. Normal conditions can be applied to the anisotropic etching conditions.
  Moreover, general conditions etc. can be employ | adopted as the conditions of each process for forming the window part for anisotropic etching in the resist film of the surface side of an etched wafer.
  As a method for growing the polysilicon layer, a high temperature CVD method can be employed.
This is because the source gas containing silicon is converted into a carrier gas (H₂ This is a method in which silicon produced by thermal decomposition or reduction of a raw material gas is deposited on a silicon wafer heated to a high temperature together with gas etc.). As a compound containing silicon, usually SiCl_Four , SiHCl_ThreeEtc.
  As a reaction furnace, there is also a vertical (pancake) furnace in which a gas is introduced while rotating a susceptor on which a silicon wafer is placed in a dome-shaped quartz bell jar and heated by high frequency induction. In addition, a cylinder (barrel) furnace that rotates a silicon wafer on each side of a hexagonal column-shaped susceptor housed in a quartz container and then rotates the susceptor with gas introduction and an infrared lamp is also used. can do.
[0011]
  The growth temperature of polysilicon differs depending on the furnace heating method. In the most common vertical furnace used for this purpose, 1200 to 1290 ° C, particularly 1320 to 1280 ° C is preferable. If it is less than 1200 degreeC, the problem that a silicon wafer tends to break will arise. Moreover, when it exceeds 1290 degreeC, a slip generate | occur | produces and the problem that a silicon wafer tends to crack will arise.
  The thickness of the polysilicon layer is set to a thickness obtained by adding the thickness of the polysilicon layer to be left to the thickness of 2 to 3 times the depth of the anisotropic etching. If the thickness of the polysilicon layer is less than twice the depth of the anisotropic etching, the anisotropic etching groove may not be sufficiently filled. On the other hand, if it is 3 times or more, it will be deposited unnecessarily thick, which is uneconomical.
[0012]
  PN inside the dielectric silicon islandJoiningThe method of forming the power generation region portion made of is not limited. For example, there is a method of thermally diffusing a specified conductivity type (N-type or P-type) dopant into an etched wafer. In this case, a well-known thermal diffusion method can be employed. That is, using a thermal diffusion furnace, for example, PH_Three, Sb₂ O_ThreeOr BBr_ThreeThe furnace temperature is controlled within an appropriate range of 600 to 1250 ° C. while feeding gas or the like. Specifically, for example, an N-type dopant such as phosphorus having a different conductivity type or a P-type dopant such as boron is thermally diffused on the surface of an etched wafer containing a predetermined concentration of dopant throughout the wafer. As a result, the PN in the silicon island formation regionJoiningAre stacked.
  An ion implantation method can also be employed. That is, this is a method in which an ion implantation apparatus is used to ionize a dopant (impurity) of one conductivity type in a gaseous state, and each is accelerated by an electric field and implanted from the surface of the silicon wafer.
  Doping time of dopant to silicon wafer (PNJoiningThe formation time) is not limited. For example, after forming a dielectric isolation silicon island, a P-type or N-type dopant is thermally diffused or ion-implanted into the surface of the island.
[0013]
  Claim2The invention according to claim 2, wherein the etching surface of the silicon wafer is an acid etching surface with an acidic etching solution or an alkali etching surface with an alkaline etching solution.1Described inFor solar cellsIt is a manufacturing method of a dielectric isolation wafer.
[0014]
  Claim3In the invention described in (2), in the step of forming the dielectric separating groove, the front and back surfaces of the silicon wafer are covered with a mask oxide film or a nitride film, and a resist film with a window is provided on the surface of the mask oxide film or the nitride film. Forming a window of a predetermined pattern in the mask oxide film or nitride film using the resist film as a mask, exposing a part of the silicon wafer from the window, and anisotropically etching the exposed part, The film is made of a positive resist having a thickness of 0.3 to 1.0 μm.1Or claims2Described inFor solar cellsIt is a manufacturing method of a dielectric isolation wafer.
  The mask film may be a mask oxide film or a nitride film.
  The preferred thickness of the positive resist film is 0.6 to 0.7 μm. If it is less than 0.3 μm, the mask oxide film 11 may be peeled off during the subsequent etching. If the thickness exceeds 1.0 μm, the light irregularly reflected by the minute irregularities on the etched surface during patterning exposure that forms a window adversely affects the patterning resolution of the window, and the window cannot be accurately formed. There is a fear.
[0015]
  Claim4In the invention described in (2), in the step of forming the dielectric separating groove, the front and back surfaces of the silicon wafer are covered with a mask oxide film or a nitride film, and a resist film with a window is provided on the surface of the mask oxide film or nitride film Forming a window of a predetermined pattern in the mask oxide film or nitride film using the resist film as a mask, exposing a part of the silicon wafer from the window, and anisotropically etching the exposed part, The film comprises a negative resist having a thickness of 0.3 to 1.0 μm.1Or claims2Described inFor solar cellsIt is a manufacturing method of a dielectric isolation wafer.
  The preferred thickness of the negative resist film is 0.6 to 0.7 μm. When the thickness is less than 0.3 μm, the photoreaction of the negative resist hardly proceeds. If the thickness exceeds 1.0 μm, resolution deterioration due to minute irregularities on the etched surface cannot be ignored.
[0016]
[Action]
  ClaimDescribed in 1 and 2According to the invention ofA dielectric separation groove of the silicon wafer is formed on the etching surface on the front side of the silicon wafer. In this case, for example, the etched surface has a glossiness of 20 to 200%. Thereafter, a dielectric isolation oxide film is formed on the surface of the silicon wafer including the dielectric isolation trench. Thereafter, a polysilicon layer is laminated on the surface of the dielectric isolation oxide film, and the silicon wafer is ground and polished from the back side. Thereafter, a plurality of dielectric isolation silicon islands separated by the dielectric isolation oxide film are exposed on the polished surface. By passing through this step, the silicon island has a bottom surface with a glossiness of 20 to 200%, for example, and this low glossiness increases the number of photons that pass through the power generation region, thereby increasing the power generation efficiency as a solar cell.
  As a result, it is possible to manufacture a dielectric isolation wafer for solar cells using existing dielectric isolation wafer manufacturing equipment and a smaller number of manufacturing steps than before. As a result, the manufacturing time of the solar cell can be shortened and the manufacturing cost can be reduced.
[0017]
  Claim3And claims4According to the invention, since the thickness of the resist film made of a positive resist or a negative resist is set to 0.3 to 1.0 μm, when the resist film is exposed, the light irregularly reflected by the minute irregularities on the etching surface is attached to the window. There is little risk of adversely affecting patterning. As a result, this window can be formed with high accuracy.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, a method of manufacturing a solar cell and a dielectric isolation wafer for the cell according to an embodiment of the present invention will be described.
  FIGS. 1A and 1B are enlarged sectional views of a solar cell according to one embodiment of the present invention. FIG. 2 is a flow sheet showing a manufacturing process of an active layer wafer used for a dielectric isolation wafer according to an embodiment of the present invention. 3 and 4 are cross-sectional views for explaining a process for manufacturing a dielectric isolation wafer according to one embodiment of the present invention.
[0019]
  First, a silicon wafer 10 whose surface to be an active layer wafer is etched is prepared and prepared (FIG. 3A).
  A method for manufacturing the silicon wafer 10 will be specifically described. In FIG. 2, the silicon ingot pulled up by the CZ method is sliced into a 5-inch silicon wafer having a thickness of about 700 μm in the slicing step (S101).
  Next, lapping is performed on the sliced wafer (S102). In this process, silicon wafers are placed between parallel lapping plates, and rotated and ground under pressure while flowing a lapping liquid that is a mixture of alumina abrasive grains, a dispersant, and water. Thereby, both front and back surfaces of the silicon wafer are mechanically wrapped. The lap time is 10-40 minutes. The amount of wrapping is about 40 to 100 μm, including both the front and back surfaces of the wafer. In the present invention, this wrapping step may be omitted.
  Thereafter, in the chamfering step (S103), the outer peripheral portion of the wrapped wafer is chamfered into a predetermined shape by a # 600 metal chamfering grindstone. As a result, the outer peripheral portion of the silicon wafer is formed into a predetermined rounded shape (for example, a MOS type chamfered shape).
[0020]
  Subsequently, the silicon wafer after chamfering is etched (S104). Specifically, the silicon wafer is immersed for a predetermined time in a mixed acid solution (room temperature to 50 ° C.) in which hydrofluoric acid and nitric acid are mixed. The glossiness of both front and back surfaces of the silicon wafer immediately after etching is 20 to 120% as measured by a glossiness measuring instrument manufactured by Nippon Denshoku.
  If necessary, the etched wafer may be subjected to donor killer heat treatment (S105). This prevents the generation of oxygen donors. At the time of heat treatment using this diffusion furnace, a large number of silicon wafers are inserted into a quartz heat treatment boat and heated in an inert gas at 650 to 700 ° C. for about 15 minutes.
  Thereafter, PCR processing may be performed on the outer peripheral portion of the etched wafer (S106). Here, a well-known PCR processing apparatus is used. That is, the cylindrical wafer is rotated by a motor and the outer peripheral surface of the silicon wafer is pressed against the rotating buff outer peripheral surface. Thereby, although the wafer front and back both surfaces are rough, the silicon wafer 10 for the wafer for active layers by which the wafer outer peripheral surface was finished by the mirror surface is produced (FIG. 3 (A)).
[0021]
  Next, the silicon wafer 10 is inserted into a thermal diffusion furnace, and a mask oxide film 11 having a thickness of 1 μm, for example, is formed on the surface of the silicon wafer 10 (FIG. 3B). Instead of the mask oxide film 11, a nitride film (SiNx) may be grown by CVD.
  Then, a positive resist or a negative resist is applied on the mask oxide film 11 to a thickness of 0.3 to 1.0 μm, and then patterned through known pre-baking, exposure, and post-baking to form a photoresist film 12. . At this time, if the thickness of the photoresist film 12 is less than 0.3 μm, the photoreaction of the negative resist hardly proceeds. Even in the case of a positive resist, the mask oxide film 11 may be peeled off later. Furthermore, if the thickness of the photoresist film 12 exceeds 1.0 μm, resolution degradation due to minute irregularities on the etched surface cannot be ignored. Then, a window 12A having a predetermined pattern is formed in the photoresist film 12 (FIG. 3C).
[0022]
  Subsequently, a window 11A having the same pattern is formed in the oxide film 11 through the window 12A, and a part of the surface of the silicon wafer 10 is exposed (FIG. 3D).
  Next, the photoresist film 12 is removed, and after cleaning the wafer surface, the silicon wafer 10 is treated with an anisotropic etching solution (IPA / KOH / H) using the oxide film 11 as a mask.₂ Soak in O) for a predetermined time. As a result, concave portions (dents) having a predetermined pattern are formed on the surface of the silicon wafer. That is, anisotropic etching is performed on the wafer surface to form a dielectric separating groove 13 having a V-shaped cross section (FIG. 3E). The surface layer of the silicon wafer 10 is divided into a large number by the dielectric separating grooves 13. If necessary, a predetermined dopant may be diffused into these divided portions (regions where the dielectric isolation silicon island is formed) to form a diffusion layer.
[0023]
  Next, a dielectric isolation oxide film 14 is formed on the front surface (also the back surface) of the wafer by thermal oxidation (FIG. 3F). At this time, the dielectric isolation oxide film 14 is also formed on the surface of the dielectric isolation groove 13. Then, the wafer surface is cleaned.
  Next, a high-temperature polysilicon layer 16 is grown thickly on the surface of the dielectric isolation oxide film 14 by a high-temperature CVD method at about 1200 to 1290 ° C. (FIG. 4A). Prior to the growth of the high temperature polysilicon layer 16, it is preferable to deposit a seed polysilicon layer on the surface of the dielectric isolation oxide film. This is because high-temperature polysilicon is grown evenly on the surface of the dielectric isolation oxide film 14. Thereafter, the wafer outer peripheral portion is chamfered, and the wafer back surface is flattened as necessary.
  Next, the high-temperature polysilicon layer 16 on the wafer surface is ground and polished to a thickness of about 10 to 80 μm. Thereafter, a low-temperature polysilicon layer 17 having a thickness of 1 to 5 μm is formed on the wafer surface by a low-temperature CVD method at 550 to 700 ° C. Further, the low-temperature polysilicon layer 17 is formed for the purpose of mirroring the bonded surface. The surface is polished (FIG. 4B).
[0024]
  On the other hand, a mirror-finished silicon wafer 20 to be a support substrate wafer is prepared (FIG. 4C). The silicon wafer 20 may be covered with a silicon oxide film. Next, the silicon wafer 10 for the active layer wafer is bonded to the silicon wafer 20 with the mirror surfaces in contact with each other (FIG. 4D). Then, this is heat-treated to increase the bonding strength of the bonded wafer.
  Next, as shown in FIG. 4E, the outer peripheral portion of the active layer wafer is chamfered, and the surface of the active layer wafer is ground and polished. The amount of grinding of this active layer wafer is such that the dielectric isolation oxide film 14 is exposed to the outside, and the dielectric isolation silicon island 30 partitioned by the dielectric isolation oxide film 14 is formed on the surface of the high temperature polysilicon layer 16. Until it appears completely. At this time, the depth from the surface of the dielectric isolation silicon island 30 to the dielectric isolation oxide film 14 is set to 30 μm or less.
[0025]
  Next, an N-type layer 30a (FIG. 1A) or a dopant opposite to the conductivity type of the active layer is diffused into the central portion of the surface of the dielectric isolation silicon island 30 by a known thermal diffusion method. A P-type layer 30b (FIG. 1B) is formed. Thereby, the electric power generation area | region part of a solar cell is formed. That is, when forming the N-type layer 30a (active layer; low-concentration P-type), a silicon oxide film is formed on the surface of the dielectric isolation silicon island 30 using a thermal diffusion furnace, and then the photoresist film 12 is formed. As a result, a buried region pattern is formed in the mask oxide film 11. Then, a part of the mask oxide film 11 is etched and opened using the photoresist film 12 as a mask, and then the photoresist film 12 is cleaned and removed. Subsequently, the dielectric separated wafer is put into a thermal diffusion furnace, and PH_Three While feeding the gas, the furnace temperature is controlled to an appropriate range of about 800 to 1200 ° C. As a result, high concentration phosphorus (N-type dopant) is thermally diffused at the center of the surface of the dielectric isolation silicon island 30 to form the N-type layer 30a. On the other hand, when the P-type layer 30b is formed (active layer; low-concentration N-type), the PH_ThreeBBr instead of gas_ThreeA gas is poured into the furnace, and boron is thermally diffused at a predetermined position to form a P-type layer 30b. Thus, a dielectric isolation wafer for a solar cell in which a PN junction is formed in the silicon island formation region and a power generation region is formed immediately below the high concentration diffusion layer is manufactured (see FIG. 1).
  The obtained dielectric isolation wafer includes a plurality of dielectric isolation silicon (active layers) by a dicing apparatus after electrodes are directly or indirectly formed on the N-type layer 30a and the P-type layer 30b, respectively. Each semiconductor chip is cut and separated to produce a large number of small solar cells.
[0026]
  According to the solar cell obtained in this way, when the depth of the dielectric isolation silicon island 30 is 30 μm or less, the bottom surface thereof is an etched surface with minute irregularities unlike the conventional mirror-finished one. Therefore, compared to this conventional product, irregular reflection of light hitting the bottom surface of this dielectric isolation silicon island 30 occurs, and the number of photons passing through the power generation region increases, thereby improving the power generation efficiency as a solar cell. Can do.
  In addition, since the depth of the dielectric isolation silicon island 30 is made as shallow as 30 μm or less in this manner, the attenuation of light traveling inside the island 30 becomes smaller than that of the conventional deep island. As a result, a decrease in power generation efficiency due to the depth of the island 30 can be suppressed.
  Further, the bottom surface of the dielectric-isolated silicon island having a gloss level of 20 to 200% can be obtained simply by using the surface on the side where the dielectric isolation groove 14 of the silicon wafer 10 is formed as an etching surface. Therefore, it is possible to manufacture a solar cell using existing dielectric isolation wafer manufacturing equipment and with fewer manufacturing steps than in the past. Thereby, shortening of the manufacturing time of a solar cell and cost reduction can be achieved.
  When this solar cell is used to fabricate a MOS type semiconductor relay mainly composed of a light emitting diode and a solar cell, the battery area is reduced and the chip can be highly integrated.
[0027]
  Here, a solar cell having a depth of each dielectric-isolated silicon island (active layer depth) of 30 μm or less was prototyped, and power generation of a general solar cell in which the bottom surface of the dielectric-isolated silicon island was actually mirror-finished The result of a comparative test between the efficiency and the power generation efficiency of the solar cell of the present invention in which the bottom surface of the island is etched (acid etching, alkali etching) is reported.
  In the solar cell, the conductivity type of the dielectric isolation silicon island was N-type, and the conductivity type of the diffusion region was P-type. The resistivity of the N-type layer is 20 to 30 Ω · cm, and the depth from the surface of the dielectric isolation silicon island to the light reflecting layer is 25 μm. 100mW / cm using AM-1 solar simulator as light source for testing²The light was irradiated. For the measurement of glossiness, a gloss measuring device “VG2000” manufactured by Nippon Denka Co., Ltd. is adopted.
  In the case of a general mirror-treated dielectric-isolated silicon island, the glossiness of the bottom surface of the island was 300%, and the power generation efficiency was 8%. In contrast, the average glossiness of the dielectric-isolated silicon island having an acid-etched bottom surface according to the present invention was 93%. The power generation efficiency at this time was about 10.3%. Further, in the case of the dielectric-isolated silicon island where the bottom surface of the present invention was alkali-etched, the glossiness averaged 43% and the power generation efficiency was 10.8%.
[0028]
【The invention's effect】
Claims 1 and 2According to this invention, the surface on the front side of the silicon wafer that will eventually become the bottom surface of the dielectric-isolated silicon island isFor example, as an etched surface with a glossiness of 20-200%Since the dielectric isolation wafer is manufactured, the existing dielectric isolation wafer manufacturing equipment is used and the number of manufacturing processes is smaller than before.Solar cell with high power generation efficiencyCan be manufactured. Thereby, shortening of the manufacturing time and cost reduction of a solar cell can be aimed at.
[0029]
  And claims3And claims4According to the invention, the thickness of the positive resist film or the negative resist film is set to 0.3 to 1.0 μm at the time of forming the dielectric separation groove. There is little risk of adverse effects on window patterning due to the light. As a result, this window can be formed with high accuracy.
[Brief description of the drawings]
1A and 1B are enlarged sectional views of a solar cell according to one embodiment of the present invention.
FIG. 2 is a flow sheet showing a manufacturing process of an active layer wafer used for a dielectric isolation wafer according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view for explaining a process for manufacturing a dielectric separated wafer according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view for explaining a process for manufacturing a dielectric separated wafer according to one embodiment of the present invention.
[Explanation of symbols]
  10 Silicon wafer,
  11 Mask oxide film,
  12 resist film,
  12A window,
  13 Dielectric separation groove,
  14 Dielectric isolation oxide film,
  16 High temperature polysilicon layer (polysilicon layer),
  30 dielectric isolation silicon island,
  30a N-type layer (power generation area),
  30b P-type layer (power generation region part).

Claims (4)

Forming a dielectric separation groove on the etched surface on the front side of the etched silicon wafer;
Forming a dielectric isolation oxide film on the surface of the silicon wafer including the dielectric isolation trench;
Laminating a polysilicon layer on the surface of the dielectric isolation oxide film;
Grinding and polishing the silicon wafer from the back side, and revealing a plurality of dielectric isolation silicon islands separated by the dielectric isolation oxide film on the polishing surface;
A method for producing a dielectric isolation wafer for solar cells, comprising the step of forming a power generation area portion comprising a PN junction in a formation area of a dielectric isolation silicon island of the silicon wafer. The method for producing a dielectric-isolated wafer for a solar cell according to claim 1 , wherein the etching surface of the silicon wafer is an acid etching surface by an acidic etching solution or an alkali etching surface by an alkaline etching solution. Forming the dielectric separation groove,
The front and back surfaces of the silicon wafer are covered with a mask oxide film or nitride film, a resist film with a window is provided on the surface of the mask oxide film or nitride film, and the mask oxide film or nitride film having a predetermined pattern is formed using the resist film as a mask. A step of exposing a portion of the silicon wafer from the window by forming a window and anisotropically etching the exposed portion;
The resist film, method for manufacturing a dielectric separation wafer for solar cell according to claim 1 or claim 2 consisting of positive resist having a thickness of 0.3 to 1.0 [mu] m. Forming the dielectric separation groove,
The front and back surfaces of the silicon wafer are covered with a mask oxide film or nitride film, a resist film with a window is provided on the surface of the mask oxide film or nitride film, and the mask oxide film or nitride film having a predetermined pattern is formed using the resist film as a mask. A step of exposing a portion of the silicon wafer from the window by forming a window and anisotropically etching the exposed portion;
The resist film, method for manufacturing a dielectric separation wafer for solar cell according to claim 1 or claim 2 made of a negative resist having a thickness of 0.3 to 1.0 [mu] m.

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