JP4239301B2 - Surface-emitting type LED, surface-emitting type LED array, and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an optical semiconductor device, and more particularly to a communication LED.
[0002]
[Prior art]
A typical example of a conventional communication LED is a surface emitting LED. In general, a surface-emitting LED has a structure in which current concentrates directly under an electrode and emits the strongest light, and the electrode covers a region immediately under the electrode where light emission is strong, resulting in poor light extraction efficiency to the outside. There is a problem. In order to avoid this, a surface-emitting LED in which an electric current is made to flow in a region shifted from immediately below the electrode is, for example, written by Toshiaki Ikoma, Takashi Kawatoda, Fumio Hasegawa, “Electronic Materials Series Gallium Arsenide” Maruzen Co., Ltd. (1988) 168, 169 (hereinafter referred to as document 1).
[0003]
FIGS. 9A to 9C are cross-sectional views showing the structure of the surface-emitting LED shown in Document 1.
[0004]
[Problems to be solved by the invention]
The surface-emitting LEDs as shown in FIGS. 9A to 9C must be accurately formed at positions where the upper electrode and the rear electrode are shifted from the light-emitting portion, which complicates the manufacturing process and increases the cost. There is a problem of inviting. In addition, in the GaAs / AlGaAs type surface emitting LED as shown in FIG. 9A, the GaAs substrate is opaque to the light output, so that the efficiency of the light emission output is increased in order to increase the efficiency of the light emission output. There is a problem in that the substrate must be deeply etched, which increases the number of manufacturing steps.
[0005]
Further, in the surface-emitting LED array in which such surface-emitting LEDs are arranged in an array, if the processing accuracy when forming the electrodes of each LED is low, the ratio of light shielding for each LED due to dimensional variation of the electrodes However, in order to correct this variation, it is necessary to provide a circuit for separately controlling the current value to be supplied to each LED. There is a problem that it increases.
[0006]
Furthermore, there is a problem that the light emission output varies for each element due to mask misalignment in the manufacturing process of the surface emitting LED and the surface emitting LED array.
[0007]
In view of such a point, the present invention provides a surface-emitting LED having a high light-emission output efficiency, a surface-emitting LED array in which variations in light-emission output are reduced using the surface-emitting LED, and a method for manufacturing the same. With the goal.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a surface emitting LED according to the present invention is formed on a first conductivity type semiconductor substrate. , Including a layer that becomes a light emitting layer and two layers that are located outside and have a larger band gap At least three layers of a first conductivity type semiconductor film are formed, and at least one second conductivity type semiconductor film is formed on the first conductivity type semiconductor film, a predetermined region on the upper surface of the composite semiconductor substrate is Of one conductivity type semiconductor film Layer to be the light emitting layer The second conductivity type semiconductor region reaching the middle of By impurity diffusion A back electrode formed and electrically connected to the first conductivity type semiconductor substrate is formed on the lower surface of the composite semiconductor substrate, and an upper electrode electrically connected to the second conductivity type semiconductor region is the composite semiconductor Formed in a predetermined region on the upper surface of the substrate, and viewed from a direction perpendicular to the surface of the composite semiconductor substrate, the second conductivity type semiconductor region serving as a light emitting portion and the upper electrode are formed at a distance from each other. .
[0010]
The surface-emitting LED according to the present invention is formed on any one of the first conductive semiconductor substrate, the second conductive semiconductor substrate, and the semi-insulating semiconductor substrate. Includes a layer that becomes a light emitting layer and two layers that are located outside and have a larger band gap At least three layers of a first conductivity type semiconductor film are formed, and at least one second conductivity type semiconductor film is formed on the first conductivity type semiconductor film, a predetermined region on the upper surface of the composite semiconductor substrate is Of one conductivity type semiconductor film Layer to be the light emitting layer The second conductivity type semiconductor region reaching the middle of By impurity diffusion A first electrode formed and electrically connected to the three-layer first conductive semiconductor film is formed in a predetermined region on the upper surface of the composite semiconductor substrate, and is electrically connected to the second conductive semiconductor region. A second electrode is formed in a predetermined region on the upper surface of the composite semiconductor substrate, and when viewed from a direction perpendicular to the surface of the composite semiconductor substrate, the second conductivity type semiconductor region serving as a light emitting portion, the second electrode, The first electrodes are formed at positions separated from each other.
[0012]
The method for manufacturing a surface-emitting LED according to the present invention includes a first step of sequentially stacking at least three layers of a first conductive semiconductor film on a first conductive semiconductor substrate, and the first step. A second step of stacking at least one second conductive type semiconductor film on the first conductive type semiconductor film; a second conductive type semiconductor region serving as a light emitting portion; and a second conductive type semiconductor region electrically connected to the second conductive type semiconductor region The upper electrode to be connected is formed on the upper surface of the composite semiconductor substrate formed by the first step and the second step at a position apart from the direction perpendicular to the surface of the composite semiconductor substrate. So as to position Diffusion prevention film with opening And a region positioned in the third step on the upper surface of the composite semiconductor substrate. Region corresponding to the light emitting part In addition, the second conductivity type semiconductor region that reaches the middle of the first conductivity type semiconductor film through the second conductivity type semiconductor film By impurity diffusion A fourth step of forming, a fifth step of forming a back electrode electrically connected to the first conductivity type semiconductor substrate on a lower surface of the composite semiconductor substrate, and a third step of the upper surface of the composite semiconductor substrate. Area positioned in the process of Of the region corresponding to the upper electrode And forming a first layer in order from the side close to the first conductivity type semiconductor substrate, and a second layer. Forming the third layer, and forming the band gap of the third layer to be smaller than the band gap of the first layer so that the band gap of the third layer is the second layer. And adjusting the composition to be larger than the band gap of the second step, the second step, Forming at least one second-conductivity-type semiconductor film and contacting an uppermost layer of the first-conductivity-type semiconductor film; Forming a fourth layer, and adjusting the composition so that the band gap of the fourth layer is larger than the band gap of the second layer, and the fourth step includes the steps of: Forming a second conductivity type semiconductor region so as to reach the middle of the second layer;
[0014]
In the method for manufacturing a surface-emitting LED according to the present invention, at least three layers of the first conductive semiconductor film are formed on any one of the first conductive semiconductor substrate, the second conductive semiconductor substrate, and the semi-insulating semiconductor substrate. A first step of sequentially stacking, a second step of stacking at least one second conductive type semiconductor film on the first conductive type semiconductor film stacked by the first step, and a light emitting portion A second conductive type semiconductor region and a second electrode electrically connected to the second conductive type semiconductor region are formed on the upper surface of the composite semiconductor substrate formed by the first step and the second step. For positioning so as to be formed away from the direction perpendicular to the surface of the composite semiconductor substrate Diffusion prevention film with opening And a region positioned in the third step on the upper surface of the composite semiconductor substrate. Region corresponding to the light emitting part In addition, the second conductivity type semiconductor region that reaches the middle of the first conductivity type semiconductor film through the second conductivity type semiconductor film By impurity diffusion A fourth step of forming and electrically connecting to one of the at least three layers of the first conductive type semiconductor film or the first conductive type semiconductor substrate in a predetermined region on the upper surface of the composite semiconductor substrate; A region positioned in the fifth step of forming the first electrode and the third step on the upper surface of the composite semiconductor substrate Region corresponding to the second electrode A sixth step of forming the second electrode, wherein the first step is performed on any one of the first conductive semiconductor substrate, the second conductive semiconductor substrate, and the semi-insulating semiconductor substrate. The step of forming the first layer, the step of forming the second layer, the step of forming the third layer, the band gap of the second layer, and the band gap of the first layer in order from the adjacent side And adjusting the composition so that the band gap of the third layer is larger than the band gap of the second layer, and the second step comprises: Forming at least one second-conductivity-type semiconductor film and contacting an uppermost layer of the first-conductivity-type semiconductor film; Forming a fourth layer, and adjusting the composition so that the band gap of the fourth layer is larger than the band gap of the second layer, and the fourth step includes the steps of: Forming a second conductivity type semiconductor region so as to reach the middle of the second layer, and the fifth step includes the second electrode of the second conductivity type semiconductor region and the second electrode. Forming in a distant region.
[0017]
The surface-emitting LED or the method of manufacturing the surface-emitting LED according to the present invention can be applied to a surface-emitting LED array in which the surface-emitting LEDs are arranged in an array.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the first to fourth embodiments, the structure of the surface-emitting LED of the present invention and the manufacturing method thereof will be described. However, the structure of the surface-emitting LED array of the present invention and the manufacturing method thereof will be described. The surface-emitting LEDs described in the fourth embodiment are arranged in an array.
[0019]
In the first to fourth embodiments, the first conductivity type is N-type and the second conductivity type is P-type. However, the first conductivity type is P-type and the second conductivity type is N-type. Can also be realized in the same manner. When the first conductivity type is P-type and the second conductivity type is N-type, S, Se, Sn, etc. can be used as impurities.
[0020]
In the first to fourth embodiments, the case where the second conductive type semiconductor region is formed by selective diffusion of impurities will be described. However, the method for forming the second conductive type semiconductor region is not limited to this, It can be realized by other methods such as ion implantation.
[0021]
Furthermore, specific methods and composition ratios such as diffusion and layer formation described in the first to fourth embodiments, composition ratios, concentrations, film thicknesses, impurities, and the like are not limited thereto.
[0022]
(First embodiment)
FIG. 1 is a perspective view showing the external structure of a surface-emitting LED according to the first embodiment of the present invention. 2 and 3 are a top view and a cross-sectional view taken along line AA ′ showing a manufacturing process of the surface-emitting LED according to the first embodiment of the present invention. In FIG. 1, FIG. 2 and FIG. 3, three elements of a surface emitting LED are shown.
[0023]
In FIG. 1, FIG. 2, and FIG. 3, the dimensions, shapes, and arrangement relationships of the respective components are schematically shown to such an extent that the invention can be understood. Moreover, in each figure, the same number is attached | subjected and shown about the same component.
[0024]
A surface-emitting LED 10 shown in FIG. 1 is a part of a surface-emitting LED array, and represents three elements of the surface-emitting LED 10 formed on the composite semiconductor substrate 11. Each surface-emitting LED 10 has an upper electrode 30 formed thereon, and a back electrode is formed on the back surface of the composite semiconductor substrate 11 (not shown).
[0025]
A manufacturing process of the surface-emitting LED according to the first embodiment will be described with reference to FIGS. As shown in FIG. 2 (a), an N-type GaAs buffer layer 13 and an N-type Al constituting the first layer are formed on an N-type GaAs (100) substrate 12 constituting the first conductive semiconductor substrate. _x Ga _1-x N-type Al constituting the As cladding layer 14 and the second layer to be the light emitting layer _y Ga _1-y As active layer 15 and N-type Al constituting the third layer _z Ga _1-z As cladding layer 16 and P-type Al constituting the fourth layer _w Ga _1-w The As carrier transport layer 17 and the P-type GaAs contact layer 18 are sequentially epitaxially grown to form the composite semiconductor substrate 11.
[0026]
Here, when y is 0.15, an LED having an emission wavelength at room temperature of 760 nm is obtained. Since the band gap increases as the Al composition ratio increases in AlGaAs semiconductors, N-type Al _x Ga _1-x As cladding layer 14 and N-type Al _z Ga _1-z The Al composition ratio of the As cladding layer 16 is N-type Al. _y Ga _1-y In order to make it larger than the Al composition ratio of the As active layer 15, x = z = 0.4 is set here. However, it is not always necessary that x = z, and each may be a value larger than y.
[0027]
P-type Al _w Ga _1-w As carrier transfer layer 17 becomes difficult to dope impurities at a high concentration when the Al composition ratio increases, but the Al composition ratio is N-type Al. _y Ga _1-y If it becomes smaller than the As active layer 15, N-type Al _y Ga _1-y Since light emitted from the As active layer 15 is absorbed, w is set to 0.2 here in consideration of these points.
[0028]
Where P-type Al _w Ga _1-w The As carrier transfer layer 17 is an N-type Al which is a light emitting layer by using carriers injected from the upper electrode 30 to be formed later. _y Ga _1-y Since it is transferred to the As active layer 15, it is desirable to reduce the electrical resistance. For this purpose, P-type Al _w Ga _1-w It is necessary to increase the thickness of the As carrier transfer layer 17 or to dope impurities at a high concentration. However, P-type Al _w Ga _1-w When the thickness of the As carrier transfer layer 17 is increased, the time for manufacturing the substrate becomes longer, and the substrate manufacturing cost during mass production increases. In general, since a substrate manufacturing apparatus must perform maintenance work every time a fixed film thickness is manufactured, increasing the film thickness of the substrate substantially reduces the operation time of the substrate manufacturing apparatus, and further increases the cost of substrate manufacturing. Increase. Therefore, P-type Al is used from the viewpoint of reducing substrate manufacturing costs. _w Ga _1-w It is desirable to make the As carrier transfer layer 17 thin. Therefore, P-type Al _w Ga _1-w The electrical resistance is reduced by increasing the carrier concentration of the As carrier transfer layer 17. At this time, the carrier concentration is 1 × 10 ¹⁸ (Cm ^-3 ) If impurities are mixed so as to be above, a desired effect can be obtained. The carrier concentration value for obtaining a desired electric resistance value can be obtained by measuring characteristics under desired conditions by computer simulation.
[0029]
The N-type GaAs buffer layer 13 is provided to improve the crystallinity of the epitaxial film, and the P-type GaAs contact layer 18 is provided to reduce the electrical resistance between the upper electrode 30 and the composite semiconductor substrate 11 to be formed later. Since it is not an essential configuration in FIG.
[0030]
The thickness of each semiconductor layer is, for example, 0.3 μm for the N-type GaAs buffer layer 13 and N-type Al. _x Ga _1-x As cladding layer 14 is 0.5 μm, N-type Al _y Ga _1-y As active layer 15 is 1.0 μm, N-type Al _z Ga _1-z As cladding layer 16 is 0.5 μm, P-type Al _w Ga _1-w The As carrier transfer layer 17 can be 1.0 μm, the P-type GaAs contact layer 18 can be 0.1 μm, and the like, but is not limited to these values.
[0031]
Next, N-type Al _y Ga _1-y A diffusion preventing film 21 having an opening is formed in the selective diffusion region 19 that selectively diffuses partway through the As active layer 15 and the contact region 20 of the upper electrode 30 that will be formed later. As the diffusion prevention film 21, silicon nitride or the like can be used. Here, a silicon nitride film having a thickness of about 2000 mm is used.
[0032]
As shown in FIG. 2B, in order to prevent impurity diffusion into the contact region 20, a diffusion prevention film 23 is formed so as to cover the contact region 20. As the diffusion preventing film 23, an alumina film or the like can be used. Here, an alumina film having a thickness of about 2000 mm is used.
[0033]
Next, Zn is selectively diffused as an impurity in the selective diffusion region 19 to form a P-type impurity diffusion region 24 constituting the second conductivity type semiconductor region. Impurity diffusion is performed by a method such as a vapor phase diffusion method or a solid phase diffusion method. Although not shown in the drawing, in the case of the solid phase diffusion method, ZnO—SiO 2 is formed on the composite semiconductor substrate 11 on which the diffusion prevention films 21 and 23 are formed. ₂ Etc. are formed by sputtering or the like, and subsequently a cap film such as silicon nitride is formed, followed by heating in a furnace at 650 ° C. or higher to introduce impurity Zn.
[0034]
The depth of diffusion is controlled by the thickness of the diffusion preventing films 21 and 23, the heating temperature and the heating time. In this way, in the selective diffusion region 19 that is not covered by either the diffusion prevention film 21 or the diffusion prevention film 23, the N-type Al serving as the light emitting layer is formed. _y Ga _1-y Impurities are diffused partway through the As active layer 15.
[0035]
As shown in FIG. 2C, after the selective diffusion is completed, all the films other than the diffusion prevention film 21 among the films formed on the composite semiconductor substrate 11 are removed by etching or the like. At this time, buffered hydrofluoric acid or the like can be used as the etchant.
[0036]
Next, the light emitting part of each surface emitting LED is separated. Element isolation is performed by etching the composite semiconductor substrate 11. After the etching mask 25 is formed in the formation region of each element with a photoresist or the like on the substrate, the region other than the formation region of each element is etched in an aqueous solution in which phosphoric acid and hydrogen peroxide water are mixed in a desired ratio, for example. To do. A region other than the element formation region is an element isolation region 26. Etching depth is P-type Al _w Ga _1-w There is no particular limitation as long as it is deeper than the As carrier transfer layer 17. In FIG. 2 (c), N-type Al _z Ga _1-z Etching is performed halfway through the As cladding layer 16. After the etching, the etching mask 25 is removed. This element separation is necessary in the case of a surface emitting LED array.
[0037]
As shown in FIG. 3A, an insulating film 27 is formed. As the insulating film 27, silicon nitride or the like can be used. Here, a silicon nitride film having a thickness of about 2000 mm is used. Thereafter, a contact hole 28 penetrating the insulating film 27 is formed by etching or the like. The contact hole 28 is connected to the opening of the contact region 20 previously formed in the diffusion prevention film 21 and is larger than the opening of the contact region 20, more strictly speaking, the contact hole 28 is an opening of the contact region 20. It is formed so as to cover the entire area of the part. By doing so, the position of the contact between the impurity diffusion region 24 and the upper electrode 30 is determined by the diffusion prevention film 21 which is the first sheet of the photolithography mask. Even if a mask misalignment occurs in the process of forming the contact hole 28, the distance between the impurity diffusion region 24 and the contact of the upper electrode 30 is kept constant. When the distance between the impurity diffusion region 24 and the contact of the upper electrode 30 varies among the LEDs, the electric resistance of the carrier transfer layer 17 varies among the LEDs, and the variation in the light emission output of each LED increases.
[0038]
The reason why the contact hole 28 is made larger than the opening of the contact region 20 will be described. When the size of the opening of the contact region 20 and the size of the contact hole 28 are different, the position of the contact formed on the electrode is determined by the smaller position (strictly speaking, the overlapping portion of both). Therefore, when the contact hole 28 is made smaller than the contact region 20, the position of the contact of the upper electrode 30 is determined by the position of the contact hole 28. Here, when a mask misalignment occurs between the diffusion preventing film 21 and the insulating film 27, the impurity diffusion region 24 whose position is determined by the diffusion preventing film 21 and the contact hole 28 whose position is determined by the insulating film 27. The positional relationship with is also shifted. Therefore, the positional relationship between the impurity diffusion region 24 and the contact of the upper electrode 30 is kept constant by keeping the opening of the contact region 20 formed with the same mask as the impurity diffusion region 24 small.
[0039]
As shown in FIG. 3B, the upper electrode 30 is formed by a known method such as a lift-off method. The material of the upper electrode 30 is not particularly limited as long as the material is ohmic-connected to the P-type GaAs contact layer 18, and Au / Zn / Au or the like can be used. The upper electrode 30 is insulated from the composite semiconductor substrate 11 by the insulating film 27.
[0040]
Next, the back electrode 31 is formed. The material of the back electrode 31 is not particularly limited as long as it is a material that is ohmic-connected to the N-type GaAs substrate 12, and AuGe / Ni / Au or the like can be used.
[0041]
In the surface-emitting LED of the present invention thus obtained, most of the carriers supplied from the upper electrode 30 pass through the P-type GaAs contact layer 18 in the vertical direction and pass through the P-type Al. _w Ga _1-w As carrier transport layer 17 is moved to the side, P-type Al _w Ga _1-w Impurity diffusion region 24 of As carrier transfer layer 17 and N-type Al _z Ga _1-z Via the impurity diffusion region 24 of the As cladding layer 16, N-type Al _y Ga _1-y It flows to the impurity diffusion region 24 of the As active layer 15.
[0042]
N type Al _z Ga _1-z As cladding layer 16 and P-type Al _w Ga _1-w The band discontinuity with the impurity diffusion region 24 of the As carrier transfer layer 17 is N-type Al. _y Ga _1-y Since it is larger than the barrier of the pn junction of the As active layer 15, carriers are P-type Al. _w Ga _1-w N-type Al from the impurity diffusion region 24 of the As carrier transfer layer 17 _z Ga _1-z N-type Al without propagating to the As cladding layer 16 _y Ga _1-y It is injected into the pn junction of the As active layer 15. As a result, N-type Al _y Ga _1-y At the pn junction of the As active layer 15, electron-hole emission recombination occurs and light is emitted.
[0043]
Finally, although not shown in the figure, predetermined dicing is performed. That is, the composite semiconductor substrate 11 obtained by forming a plurality of surface-emitting LEDs of the present invention obtained by the steps shown in FIGS. 2 and 3 is diced along a dividing line (not shown) between the LEDs, and a plurality of them are diced. The surface emitting LED is obtained. In the case of a surface-emitting LED array, the composite semiconductor substrate 11 in which a plurality of surface-emitting LED arrays according to the present invention in which surface-emitting LEDs are arranged in an array is completed is used as a dividing line (not shown) between the LED arrays. A plurality of surface emitting LED arrays are obtained by dicing along.
[0044]
(Second embodiment)
The external structure of the surface-emitting LED in the second embodiment of the present invention is as shown in FIG. 4 and 5 are a top view and a cross-sectional view taken along line AA ′ showing a manufacturing process of the surface-emitting LED according to the second embodiment of the present invention. The same FIG. 1 as that of the first embodiment is used as a diagram showing the external structure of the surface-emitting LED in the second embodiment. However, in the internal structure and manufacturing process not shown in FIG. This is different from the embodiment. In FIG. 1, FIG. 4 and FIG. 5, three elements of a surface emitting LED are shown.
[0045]
In FIG. 1, FIG. 4, and FIG. 5, the dimensions, shapes, and arrangement relationships of the respective components are schematically shown to such an extent that the invention can be understood. Moreover, in each figure, the same number is attached | subjected and shown about the same component.
[0046]
A surface-emitting LED 10 shown in FIG. 1 is a part of a surface-emitting LED array, and represents three elements of the surface-emitting LED 10 formed on the composite semiconductor substrate 11. Each surface-emitting LED 10 has an upper electrode 30 formed thereon, and a back electrode is formed on the back surface of the composite semiconductor substrate 11 (not shown).
[0047]
The manufacturing process of the surface-emitting LED according to the second embodiment will be described with reference to FIGS. As shown in FIG. 4 (a), an N-type GaAs buffer layer 13 and an N-type Al constituting the first layer are formed on an N-type GaAs (100) substrate 12 constituting the first conductive semiconductor substrate. _x Ga _1-x N-type Al constituting the As cladding layer 14 and the second layer to be the light emitting layer _y Ga _1-y As active layer 15 and N-type Al constituting the third layer _z Ga _1-z An As cladding layer 16 and an N-type GaAs contact layer 37 are epitaxially grown sequentially to form the composite semiconductor substrate 11.
[0048]
Here, when y is 0.15, an LED having an emission wavelength at room temperature of 760 nm is obtained. Since the band gap increases as the Al composition ratio increases in AlGaAs semiconductors, N-type Al _x Ga _1-x As cladding layer 14 and N-type Al _z Ga _1-z The Al composition ratio of the As cladding layer 16 is N-type Al. _y Ga _1-y In order to make it larger than the Al composition ratio of the As active layer 15, x = z = 0.4 is set here. However, it is not always necessary that x = z, and each may be a value larger than y.
[0049]
The N-type GaAs buffer layer 13 is provided to improve the epitaxial film crystallinity, and the N-type GaAs contact layer 37 is provided to reduce the electrical resistance between the upper electrode 30 and the composite semiconductor substrate 11 to be formed later. Since it is not an essential configuration in the present invention, it is not necessarily provided.
[0050]
The thickness of each semiconductor layer is, for example, 0.3 μm for the N-type GaAs buffer layer 13 and N-type Al. _x Ga _1-x As cladding layer 14 is 0.5 μm, N-type Al _y Ga _1-y As active layer 15 is 1.0 μm, N-type Al _z Ga _1-z The As cladding layer 16 can be 1.5 μm, the N-type GaAs contact layer 37 can be 0.1 μm, and the like, but are not limited to these values.
[0051]
Next, N-type Al _z Ga _1-z A diffusion prevention film 21 having a window is formed in a selective diffusion region 39 that selectively diffuses partway through the As cladding layer 16. As the diffusion prevention film 21, silicon nitride or the like can be used. Here, a silicon nitride film having a thickness of about 2000 mm is used.
[0052]
As shown in FIG. 4B, N-type Al _y Ga _1-y A diffusion control film 43 having an opening in the selective diffusion region 40 that selectively diffuses partway through the As active layer 15 is formed. As the diffusion control film 43, an alumina film or the like can be used. Here, an alumina film having a thickness of about 100 mm is used.
[0053]
As shown in FIG. 4C, Zn is selectively diffused as an impurity in the selective diffusion regions 39 and 40 to form a P-type impurity diffusion region 44 that constitutes the second conductivity type semiconductor region. Impurity diffusion is performed by a method such as a vapor phase diffusion method or a solid phase diffusion method. Although not shown in the figure, in the case of the solid phase diffusion method, ZnO—SiO is formed on the composite semiconductor substrate 11 on which the diffusion prevention film 21 and the diffusion control film 43 are formed. ₂ Etc. are formed by sputtering or the like, and subsequently a cap film such as silicon nitride is formed, followed by heating in a furnace at 650 ° C. or higher to introduce impurity Zn.
[0054]
The depth of diffusion is controlled by the thickness of the diffusion control film 43, the heating temperature, and the heating time. Thus, impurity diffusion does not proceed in the region covered with the diffusion prevention film 21, and the diffusion becomes shallow in the region covered with only the diffusion control film 43 without the diffusion prevention film 21. Since the diffusion is deep in the region not covered with any of the control films 43, a desired diffusion shape can be obtained.
[0055]
That is, in the region where diffusion is deep, N-type Al _y Ga _1-y Impurities are diffused partway through the As active layer 15 to form a second region serving as a light emitting portion in the second conductivity type semiconductor region, and N-type Al is used in a shallow diffusion region. _z Ga _1-z Impurities are diffused partway through the As cladding layer 16 to form a first region that does not serve as a light emitting portion in the second conductivity type semiconductor region.
[0056]
As shown in FIG. 5A, after the selective diffusion is completed, all the films formed on the composite semiconductor substrate 11 are removed by etching or the like. At this time, buffered hydrofluoric acid or the like can be used as the etchant.
[0057]
Next, the light emitting part of each surface emitting LED is separated. Element isolation is performed by etching the composite semiconductor substrate 11. After the etching mask 25 is formed in the formation region of each element with a photoresist or the like on the substrate, the region other than the formation region of each element is etched in an aqueous solution in which phosphoric acid and hydrogen peroxide water are mixed in a desired ratio, for example. To do. A region other than the element formation region becomes an element isolation region 46. The etching depth is not particularly limited as long as it is deeper than the N-type GaAs contact layer 37. In FIG. 5 (a), N-type Al _z Ga _1-z Etching is performed halfway through the As cladding layer 16. After the etching, the etching mask 25 is removed. This element separation is necessary in the case of a surface emitting LED array.
[0058]
As shown in FIG. 5B, an insulating film 27 is formed, and then a contact hole 48 penetrating the insulating film 27 is formed by etching or the like. The position where the contact hole 48 is formed is an error of the substrate manufacturing apparatus so that the end of the contact of the upper electrode 30 to be formed later and the end of the deep diffusion region of the impurity diffusion region 44 as the light emitting portion do not overlap. Considering the formation. For this purpose, when the element isolation region 46 is formed by etching, it is necessary to sufficiently secure the length of the shallow diffusion region in the impurity diffusion region 44. That is, the length of the shallow diffusion region is set sufficiently when the diffusion control film 43 is formed in FIG. 4B, and the element formation region remains sufficiently long when element isolation is performed in FIG. Thus, it is necessary to perform etching.
[0059]
As shown in FIG. 5C, the upper electrode 30 is formed by a known method such as a lift-off method. The material of the upper electrode 30 is not particularly limited as long as it is ohmic-connected to the P-type GaAs contact layer of the impurity diffusion region 44, and Au / Zn / Au or the like can be used. The upper electrode 30 is insulated from the composite semiconductor substrate 11 by the insulating film 27.
[0060]
Next, the back electrode 31 is formed. The material of the back electrode 31 is not particularly limited as long as it is a material that is ohmic-connected to the N-type GaAs substrate 12, and AuGe / Ni / Au or the like can be used.
[0061]
In the surface-emitting LED of the present invention thus obtained, the carrier supplied from the upper electrode 30 is N-type Al. _z Ga _1-z Propagates through the impurity diffusion region 44 of the As clad layer 16 and N-type Al _y Ga _1-y It flows to the impurity diffusion region 44 of the As active layer 15.
[0062]
N type Al _z Ga _1-z The band gap of the As cladding layer 16 is N-type Al. _y Ga _1-y Since it is larger than the band gap of the As active layer 15, carriers are N-type Al. _z Ga _1-z The impurity diffusion region 44 extends beyond the pn junction of the As cladding layer 16 to form N-type Al. _z Ga _1-z N-type Al without propagating to the As cladding layer 16 _y Ga _1-y It is injected into the pn junction of the As active layer 15. This N-type Al _y Ga _1-y At the pn junction of the As active layer 15, electron-hole emission recombination occurs and light is emitted.
[0063]
Finally, although not shown in the figure, predetermined dicing is performed. That is, the composite semiconductor substrate 11 obtained by forming a plurality of surface-emitting LEDs of the present invention obtained by the steps shown in FIGS. The surface emitting LED is obtained. In the case of a surface-emitting LED array, the composite semiconductor substrate 11 in which a plurality of surface-emitting LED arrays according to the present invention in which surface-emitting LEDs are arranged in an array is completed is used as a dividing line (not shown) between the LED arrays. A plurality of surface emitting LED arrays are obtained by dicing along.
[0064]
(Third embodiment)
FIG. 6 is a perspective view showing the external structure of the surface-emitting LED according to the third embodiment of the present invention. FIG. 7 is a top view and AA ′ cross-sectional view showing a manufacturing process of the surface-emitting LED according to the third embodiment of the present invention. In FIG. 6 and FIG. 7, three surface-emitting LEDs are represented, but the number of elements is not limited to this.
[0065]
In FIG. 6 and FIG. 7, the dimensions, shapes, and arrangement relationships of the constituent components are schematically shown to such an extent that the invention can be understood. Moreover, in each figure, the same number is attached | subjected and shown about the same component.
[0066]
The surface-emitting LED 10 shown in FIG. 6 is a part of the surface-emitting LED array, and represents three elements of the surface-emitting LED 10 formed on the composite semiconductor substrate 11. In each surface emitting LED 10, a first electrode 50 common to each element of the LED and an individual second electrode 30 are formed for each element of the LED.
[0067]
Up to the middle of the manufacturing process of the surface-emitting LED in the third embodiment is substantially the same as the manufacturing process in the first embodiment shown in FIGS. 2 and 3A, and is shown in FIG. A manufacturing process shows the process after Fig.3 (a). Therefore, the description of the process steps shown in FIGS. 2 and 3A and the dicing process is omitted.
[0068]
In the first embodiment, the N-type GaAs substrate 12 constituting the first conductivity type semiconductor substrate is used. However, in the third embodiment, the first conductivity type semiconductor substrate and the second conductivity type semiconductor are used. Either a substrate or a semi-insulating semiconductor substrate can be used. Here, the case where the N-type GaAs substrate 12 which is the first conductive type semiconductor substrate is used will be described, but the same applies to the case where another substrate is used.
[0069]
With reference to FIG. 7, a part different from the first embodiment in the manufacturing process of the surface emitting LED in the third embodiment will be described. After the steps shown in FIGS. 2 and 3 (a), as shown in FIG. 7 (a), the upper electrode 30 constituting the second electrode is formed by the same method, material, etc. as in the first embodiment. To do. Hereinafter, the upper electrode 30 is described as the second electrode 30.
[0070]
As shown in FIG. 7B, the insulating film 27 in the first electrode formation scheduled region 51 is removed by a known method such as etching. The first electrode formation scheduled region 51 is determined so as not to contact either the impurity diffusion region 24 or the contact portion of the second electrode 30. Next, an N-type semiconductor layer or an N-type semiconductor substrate electrically connected to the first electrode 50, that is, an N-type GaAs buffer layer 13, an N-type Al _x Ga _1-x As cladding layer 14, N-type Al _y Ga _1-y As active layer 15 and N-type Al _z Ga _1-z In order to expose either the As cladding layer 16 or the N-type GaAs substrate 12, etching or the like is performed on the first electrode formation scheduled region 51 until the desired layer or substrate is reached. In FIG. 7B, the N-type GaAs substrate 12 is etched halfway.
[0071]
Here, when the P-type semiconductor substrate or the semi-insulating semiconductor substrate which is the second conductivity type semiconductor substrate is used instead of the N-type GaAs substrate 12, the first electrode 50 is not connected to these substrates, and N Type semiconductor layer N type GaAs buffer layer 13, N type Al _x Ga _1-x As cladding layer 14, N-type Al _y Ga _1-y As active layer 15 and N-type Al _z Ga _1-z It is connected to any one of the As cladding layers 16.
[0072]
As shown in FIG. 7C, the first electrode 50 is formed in the first electrode formation scheduled region 51 by a known method such as a lift-off method. The material of the first electrode 50 is not particularly limited as long as the material is ohmic-connected to the N-type semiconductor layer or the N-type semiconductor substrate to be connected, and AuGe / Ni / Au or the like can be used. In FIG. 7 (c), the first electrode 50 is connected to the N-type GaAs substrate 12.
[0073]
In the surface-emitting LED of the present invention thus obtained, the first electrode 50 is composed of the N-type GaAs substrate 12, the N-type GaAs buffer layer 13, the N-type Al. _x Ga _1-x As cladding layer 14 and N-type Al _y Ga _1-y When connected to any one of the As active layers 15, the operation is the same as in the first embodiment. The first electrode 50 is N-type Al. _z Ga _1-z When connected to the As cladding layer 16, N-type Al _z Ga _1-z The band gap of the As cladding layer 16 is N-type Al. _y Ga _1-y By making it larger than the band gap of the As active layer 15, the barrier of the pn junction becomes N-type Al. _y Ga _1-y It becomes larger than the barrier of the pn junction of the As active layer 15, and the carrier _y Ga _1-y By being injected into the pn junction of the As active layer 15, electron-hole recombination occurs and light is emitted.
[0074]
The selection of the substrate or layer to which the first electrode 50 is connected also affects the etching depth. When etching up to the N-type GaAs substrate 12, there is a possibility of disconnection due to a large step when the wiring connected to the first electrode 50 is drawn to the surface, and the width of etching becomes wider depending on the depth. Since the N-type GaAs substrate 12 is formed thicker than the N-type semiconductor layer, the etching depth can be easily determined. On the other hand, an N-type GaAs buffer layer 13 which is an N-type semiconductor layer, an N-type Al _x Ga _1-x As cladding layer 14, N-type Al _y Ga _1-y As active layer 15 and N-type Al _z Ga _1-z When etching up to any one of the As cladding layers 16, it is difficult to accurately determine the etching depth because the film thickness is thin, but the possibility of disconnection is low. In consideration of these points, it is desirable to determine an optimum etching depth, that is, a layer or a substrate connected to the first electrode 50.
[0075]
(Fourth embodiment)
The external structure of the surface-emitting LED in the fourth embodiment of the present invention is as shown in FIG. FIG. 8 is a top view and AA ′ cross-sectional view showing a manufacturing process of the surface-emitting LED according to the fourth embodiment of the present invention. Although FIG. 6 which is the same as that of the third embodiment is used as a diagram showing the external structure of the surface-emitting LED in the fourth embodiment, the third structure is not shown in FIG. This is different from the embodiment. In FIG. 6 and FIG. 8, three surface-emitting LEDs are represented, but the number of elements is not limited to this.
[0076]
6 and 8 schematically show the size, shape, and arrangement relationship of each component so that the invention can be understood. Moreover, in each figure, the same number is attached | subjected and shown about the same component.
[0077]
The surface-emitting LED 10 shown in FIG. 6 is a part of the surface-emitting LED array, and represents three elements of the surface-emitting LED 10 formed on the composite semiconductor substrate 11. In each surface emitting LED 10, a first electrode 50 common to each element of the LED and an individual second electrode 30 are formed for each element of the LED.
[0078]
Up to the middle of the manufacturing process of the surface-emitting type LED in the fourth embodiment is substantially the same as the manufacturing process in the second embodiment shown in FIGS. 4, 5A and 5B. The manufacturing process shown in FIG. 8 shows the processes after FIG. Therefore, the description of the steps shown in FIG. 4, FIG. 5 (a) and FIG. 5 (b) and the dicing step will be omitted.
[0079]
In the second embodiment, the N-type GaAs substrate 12 constituting the first conductivity type semiconductor substrate is used. However, in the fourth embodiment, the first conductivity type semiconductor substrate and the second conductivity type semiconductor are used. Either a substrate or a semi-insulating semiconductor substrate can be used. Here, the case where the N-type GaAs substrate 12 which is the first conductive type semiconductor substrate is used will be described, but the same applies to the case where another substrate is used.
[0080]
With reference to FIG. 8, portions of the manufacturing process of the surface-emitting LED according to the fourth embodiment that are different from those of the second embodiment will be described. After the steps shown in FIG. 4, FIG. 5 (a) and FIG. 5 (b), as shown in FIG. 8 (a), the upper electrode 30 constituting the second electrode is the same as in the second embodiment. It is formed by a method, a material or the like. Hereinafter, the upper electrode 30 is described as the second electrode 30.
[0081]
As shown in FIG. 8B, the insulating film 27 in the first electrode formation scheduled region 51 is removed by a known method such as etching. The first electrode formation scheduled region 51 is determined so as not to contact either the impurity diffusion region 44 or the contact portion of the second electrode 30. Next, an N-type semiconductor layer or an N-type semiconductor substrate electrically connected to the first electrode 50, that is, an N-type GaAs buffer layer 13, an N-type Al _x Ga _1-x As cladding layer 14, N-type Al _y Ga _1-y As active layer 15 and N-type Al _z Ga _1-z In order to expose either the As clad layer 16 or the N-type GaAs substrate 12, etching or the like is performed until a desired layer or substrate is reached. In FIG. 8B, the N-type GaAs substrate 12 is etched halfway.
[0082]
Here, when the P-type semiconductor substrate or the semi-insulating semiconductor substrate which is the second conductivity type semiconductor substrate is used instead of the N-type GaAs substrate 12, the first electrode 50 is not connected to these substrates, and N Type semiconductor layer N type GaAs buffer layer 13, N type Al _x Ga _1-x As cladding layer 14, N-type Al _y Ga _1-y As active layer 15 and N-type Al _z Ga _1-z It is connected to any one of the As cladding layers 16.
[0083]
Further, the N-type GaAs contact layer 37 can be electrically connected to the first electrode 50, but the N-type GaAs contact layer 37 is made of N-type Al. _y Ga _1-y Since the band gap is smaller than that of the As active layer 15 and the pn junction barrier is lower, in this case, the N-type GaAs contact layer 37 is formed by using the portion where the first electrode 50 is formed, the contact portion of the second electrode 30 and the impurity diffusion region 44. It is necessary to be electrically separated from the portion forming the.
[0084]
As shown in FIG. 8C, the first electrode 50 is formed in the first electrode formation scheduled region 51 by a known method such as a lift-off method. The material of the first electrode 50 is not particularly limited as long as the material is ohmic-connected to the N-type semiconductor layer or the N-type semiconductor substrate to be connected, and AuGe / Ni / Au or the like can be used. In FIG. 8C, the first electrode 50 is connected to the N-type GaAs substrate 12.
[0085]
In the surface-emitting LED of the present invention thus obtained, the first electrode 50 is composed of the N-type GaAs substrate 12, the N-type GaAs buffer layer 13, the N-type Al. _x Ga _1-x As cladding layer 14 and N-type Al _y Ga _1-y When connected to any one of the As active layers 15, the operation is the same as in the second embodiment. The first electrode 50 is N-type Al. _z Ga _1-z When connected to the As cladding layer 16, N-type Al _z Ga _1-z The band gap of the As cladding layer 16 is N-type Al. _y Ga _1-y By making it larger than the band gap of the As active layer 15, the barrier of the pn junction becomes N-type Al. _y Ga _1-y It becomes larger than the barrier of the pn junction of the As active layer 15, and the carrier _y Ga _1-y By being injected into the pn junction of the As active layer 15, electron-hole recombination occurs and light is emitted.
[0086]
The selection of the substrate or layer to which the first electrode 50 is connected also affects the etching depth. When etching up to the N-type GaAs substrate 12, there is a possibility of disconnection due to a large step when the wiring connected to the first electrode 50 is drawn to the surface, and the width of etching becomes wider depending on the depth. Since the N-type GaAs substrate 12 is formed thicker than the N-type semiconductor layer, the etching depth can be easily determined. On the other hand, an N-type GaAs buffer layer 13 which is an N-type semiconductor layer, an N-type Al _x Ga _1-x As cladding layer 14, N-type Al _y Ga _1-y As active layer 15 and N-type Al _z Ga _1-z When etching up to any one of the As cladding layers 16, it is difficult to accurately determine the etching depth because the film thickness is thin, but the possibility of disconnection is low. In consideration of these points, it is desirable to determine an optimum etching depth, that is, a layer or a substrate connected to the first electrode 50.
[0087]
【The invention's effect】
As described above, according to the first aspect of the present invention, the second conductive type semiconductor region serving as the light emitting portion and the contact portion of the upper electrode for supplying carriers are formed at positions separated from the upper surface of the composite semiconductor substrate. As a result, the light emitting portion and the upper electrode do not overlap each other, and in the conventional surface emitting LED, the light shielded by the upper electrode can be output to the outside, and the light is emitted as compared with the conventional surface emitting LED. The output efficiency can be increased.
[0088]
The invention according to claim 2 is formed at a position where the first region that does not become the light emitting portion of the second conductive type semiconductor region overlaps with the contact portion of the upper electrode that supplies carriers, and the second conductive type semiconductor region The second region serving as the light emitting portion and the contact portion of the upper electrode are formed at positions separated from the upper surface of the composite semiconductor substrate, and the first region and the second region are in contact with each other, thereby emitting light. The part and the upper electrode do not overlap, and the conventional surface-emitting LED can output the light shielded by the upper electrode to the outside, and the light emission output efficiency is higher than that of the conventional surface-emitting LED. It has the effect that it can be done. In addition, the first region of the second conductivity type semiconductor region conducts carriers from the upper electrode to the second region which is the light emitting portion, so that the second region in the composite semiconductor substrate is compared with the invention according to claim 1. There is an effect that a conductive semiconductor film becomes unnecessary.
[0089]
The invention according to claim 3 is that the electrode formed on the back surface of the composite semiconductor substrate in claim 1 is formed on the top surface of the substrate, thereby improving the degree of freedom when mounting the surface emitting LED on the substrate. The type of the substrate used has the effect that not only the first conductive semiconductor substrate but also the second conductive semiconductor substrate or the semi-insulating semiconductor substrate can be used.
[0090]
The invention according to claim 4 is that the electrode formed on the back surface of the composite semiconductor substrate in claim 2 is formed on the top surface of the substrate, thereby improving the degree of freedom when mounting the surface emitting LED on the substrate. The type of the substrate used has the effect that not only the first conductive semiconductor substrate but also the second conductive semiconductor substrate or the semi-insulating semiconductor substrate can be used.
[0091]
The invention according to claim 5 has an effect that the second conductivity type semiconductor region can be easily formed by using the second conductivity type semiconductor region as the impurity diffusion region.
[0092]
In the invention according to claim 6, since the surface-emitting LEDs in the inventions according to claims 1 to 5 are arranged in an array, each surface-emitting LED has a variation in processing accuracy of electrodes. However, there is no need to provide a current value control mechanism for correcting variations in the light emission output without affecting the light emission output, and a surface emitting LED array with good light emission output uniformity without causing an increase in cost. Is obtained.
[0093]
According to the seventh aspect of the present invention, when the second conductive type semiconductor region to be the light emitting portion and the contact portion of the upper electrode for supplying carriers are formed at positions separated from the upper surface of the composite semiconductor substrate, each is formed. By determining the position to be performed in the same process, even if there is a mask misalignment, it is not affected, and the overlapping of the light emitting part and the upper electrode is prevented without increasing the electrode processing accuracy. The light shielded by the upper electrode can be output to the outside, and the light emission output efficiency is increased without complicating the manufacturing process and increasing the cost as compared with the manufacturing process of the conventional surface emitting LED. It has the effect of being able to.
[0094]
According to an eighth aspect of the present invention, a first region that does not serve as a light emitting portion in the second conductivity type semiconductor region and a contact portion of an upper electrode that supplies carriers are formed at overlapping positions. The second region serving as the light emitting portion and the contact portion of the upper electrode are formed at positions separated from the upper surface of the composite semiconductor substrate, and the first region and the second region are manufactured and contacted in the same process. By doing so, it is possible to prevent the light emitting portion and the upper electrode from overlapping without increasing the processing accuracy of the electrode, and in the conventional surface-emitting LED, the light shielded by the upper electrode can be output to the outside. Compared with the manufacturing process of light emitting LED, it has the effect that the efficiency of the light emission output can be increased without causing the manufacturing process to be complicated and the cost to increase. In addition, the first region of the second conductivity type semiconductor region conducts carriers from the upper electrode to the second region which is the light emitting portion, so that the second region in the composite semiconductor substrate is compared with the invention according to claim 5. There is an effect that it is not necessary to form a conductive semiconductor film.
[0095]
The invention according to claim 9 is a substrate to be used in which the electrode formed on the back surface of the composite semiconductor substrate according to claim 7 is formed on the top surface of the substrate, so that the degree of freedom in mounting the surface emitting LED on the substrate is improved. This type has the effect that not only the first conductive type semiconductor substrate but also the second conductive type semiconductor substrate or the semi-insulating semiconductor substrate can be used.
[0096]
The invention according to claim 10 is the substrate used in claim 8, wherein the electrode formed on the back surface of the composite semiconductor substrate is formed on the top surface of the substrate, whereby the degree of freedom in mounting the surface emitting LED on the substrate is improved. This type has the effect that not only the first conductive type semiconductor substrate but also the second conductive type semiconductor substrate or the semi-insulating semiconductor substrate can be used.
[0097]
The invention according to claim 11 has the effect that the second conductive semiconductor region can be easily formed by forming the second conductive semiconductor region by impurity diffusion.
[0098]
According to the twelfth aspect of the present invention, the surface-emitting LEDs in the inventions according to the seventh to eleventh aspects are arranged in an array so that each surface-emitting LED has variations in electrode processing accuracy. Even if it does not affect the light emission output, it is not necessary to provide a current value control mechanism or the like for correcting the variation of the light emission output, and the surface emitting LED with good uniformity of the light emission output without increasing the cost An effect is that the array can be manufactured.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an external structure of a surface emitting LED according to a first embodiment and a second embodiment of the present invention.
FIGS. 2A and 2B are a top view and a cross-sectional view taken along line AA ′ showing a manufacturing process of the surface-emitting LED according to the first embodiment of the present invention. FIGS.
FIGS. 3A and 3B are a top view and a cross-sectional view taken along line AA ′ showing a manufacturing process of the surface-emitting LED according to the first embodiment of the present invention. FIGS.
FIG. 4 is a top view and AA ′ cross-sectional view showing a manufacturing process of a surface-emitting LED according to a second embodiment of the present invention.
FIGS. 5A and 5B are a top view and a cross-sectional view taken along line AA ′ showing a manufacturing process of a surface-emitting LED according to a second embodiment of the invention. FIGS.
FIG. 6 is a perspective view showing an external structure of a surface-emitting LED according to the third embodiment and the fourth embodiment of the present invention.
FIGS. 7A and 7B are a top view and a cross-sectional view taken along line AA ′ showing a manufacturing process of a surface-emitting LED according to a third embodiment of the invention. FIGS.
FIGS. 8A and 8B are a top view and a cross-sectional view taken along line AA ′ showing a manufacturing process of the surface-emitting LED according to the fourth embodiment of the invention. FIGS.
FIG. 9 is a cross-sectional view showing the structure of a surface-emitting LED in a conventional example
[Explanation of symbols]
10 surface-emitting LED, 11 composite semiconductor substrate, 12 N-type GaAs substrate, 13 N-type GaAs buffer layer, 14 N-type Al _x Ga _1-x As cladding layer, 15 N-type Al _y Ga _1-y As active layer, 16 N-type Al _z Ga _1-z As cladding layer, 17 P-type Al _w Ga _1-w As carrier transfer layer, 18 P-type GaAs contact layer, 19, 39, 40 selective diffusion region, 24, 44 impurity diffusion region, 20 contact region, 21, 23 anti-diffusion film, 25 etching mask, 26, 46 element isolation region, 27 Insulating film, 28, 48 contact hole, 30 Upper electrode (second electrode), 31 Back electrode, 37 N-type GaAs contact layer, 43 Diffusion control film, 50 First electrode, 51 First electrode formation region

Claims (6)

On the first conductivity type semiconductor substrate, at least three layers of the first conductivity type semiconductor film including a layer to be a light emitting layer and two layers located outside thereof and having a larger band gap are formed. A second region that reaches a predetermined region of the upper surface of the composite semiconductor substrate on which at least one second-conductivity-type semiconductor film is formed on the semiconductor film and reaches the middle of the light-emitting layer of the first-conductivity-type semiconductor film; A conductive semiconductor region is formed by impurity diffusion ;
A back electrode electrically connected to the first conductive type semiconductor substrate is formed on the bottom surface of the composite semiconductor substrate;
An upper electrode electrically connected to the second conductivity type semiconductor region is formed in a predetermined region on the upper surface of the composite semiconductor substrate,
A surface-emitting LED in which the second conductive semiconductor region serving as a light-emitting portion and the upper electrode are formed at a position apart from the direction perpendicular to the surface of the composite semiconductor substrate. On at least one of the first conductivity type semiconductor substrate, the second conductivity type semiconductor substrate, and the semi-insulating semiconductor substrate, at least a layer that becomes a light emitting layer and two layers that are located outside and have a larger band gap A first conductive semiconductor film having three layers is formed, and the first conductive semiconductor film is formed in a predetermined region on the upper surface of the composite semiconductor substrate in which at least one second conductive semiconductor film is formed on the first conductive semiconductor film. A second conductive type semiconductor region that reaches the middle of the light emitting layer of the conductive type semiconductor film is formed by impurity diffusion ;
A first electrode electrically connected to the three-layer first conductive semiconductor film is formed in a predetermined region on the upper surface of the composite semiconductor substrate;
A second electrode electrically connected to the second conductivity type semiconductor region is formed in a predetermined region on the upper surface of the composite semiconductor substrate;
A surface light emission in which the second conductive semiconductor region, the second electrode, and the first electrode, which are light emitting portions, are formed at positions separated from each other when viewed from a direction perpendicular to the surface of the composite semiconductor substrate. Type LED. A surface-emitting LED array in which the surface-emitting LEDs according to claim 1 or 2 are arranged in an array. A first step of sequentially stacking at least three layers of first conductive semiconductor films on a first conductive type semiconductor substrate, and at least one layer of layers on the first conductive type semiconductor films stacked by the first step A second step of laminating a second conductive type semiconductor film, a second conductive type semiconductor region to be a light emitting portion, and an upper electrode electrically connected to the second conductive type semiconductor region, the first step And an opening for positioning so as to be formed at a position apart from the direction perpendicular to the surface of the composite semiconductor substrate on the upper surface of the composite semiconductor substrate formed by the second step A third step of forming a film , and a region corresponding to the light emitting portion among the regions positioned in the third step on the upper surface of the composite semiconductor substrate, penetrating the second conductive semiconductor film and passing through the second conductive semiconductor film. The second conductivity type semiconductor that reaches the middle of the one conductivity type semiconductor film A fourth step of the band is formed by impurity diffusion, the lower surface of the composite semiconductor substrate, and a fifth step of forming a back electrode is electrically connected to the first conductivity type semiconductor substrate, the compound semiconductor substrate A sixth step of forming the upper electrode in a region corresponding to the upper electrode among the regions positioned in the third step on the upper surface;
The first step includes a step of forming a first layer, a step of forming a second layer, a step of forming a third layer, and a step of forming a third layer in order from the side close to the first conductivity type semiconductor substrate; Adjusting the composition so that the band gap of the second layer is smaller than the band gap of the first layer and the band gap of the third layer is larger than the band gap of the second layer. Prepared,
The second step comprises forming the at least one second conductive semiconductor film and forming a fourth layer in contact with the uppermost layer of the first conductive semiconductor film ; and Adjusting the composition so that the band gap is larger than the band gap of the second layer,
A method for manufacturing a surface-emitting LED, wherein the fourth step includes a step of forming the second conductivity type semiconductor region so as to reach the middle of the second layer. A first step of sequentially stacking at least three first conductive semiconductor films on any of the first conductive semiconductor substrate, the second conductive semiconductor substrate, and the semi-insulating semiconductor substrate; A second step of stacking at least one second conductive type semiconductor film on the first conductive type semiconductor film stacked by the steps; a second conductive type semiconductor region serving as a light emitting portion; and the second conductive type semiconductor A second electrode that is electrically connected to the region is viewed from a direction perpendicular to the surface of the composite semiconductor substrate on the upper surface of the composite semiconductor substrate formed by the first step and the second step. A third step of forming an anti-diffusion film provided with an opening for positioning so as to be formed at a distant position; and the light emitting portion in the region positioned in the third step on the upper surface of the composite semiconductor substrate the corresponding region, transmural a second conductivity type semiconductor layer A fourth step of forming the impurity diffusion of the second conductivity type semiconductor region to reach the middle of the first conductivity type semiconductor film is in a predetermined area of the composite semiconductor substrate upper surface, a three-layer the at least Positioning in a fifth step of forming any one of the one-conductivity-type semiconductor films or a first electrode electrically connected to the first-conductivity-type semiconductor substrate, and in the third step on the upper surface of the composite semiconductor substrate A sixth step of forming the second electrode in a region corresponding to the second electrode among the formed regions ,
The first step includes a step of forming a first layer in order from a side close to any one of the first conductive semiconductor substrate, the second conductive semiconductor substrate, and the semi-insulating semiconductor substrate; A step of forming a layer, a step of forming a third layer, a band gap of the second layer is made smaller than a band gap of the first layer, and a band gap of the third layer is changed to the second layer. Adjusting the composition to be larger than the band gap of the layer of
The second step comprises forming the at least one second conductive semiconductor film and forming a fourth layer in contact with the uppermost layer of the first conductive semiconductor film ; and Adjusting the composition so that the band gap is larger than the band gap of the second layer,
The fourth step includes a step of forming the second conductivity type semiconductor region so as to reach the middle of the second layer,
The method for manufacturing a surface-emitting LED, wherein the fifth step includes a step of forming the first electrode in the second conductive semiconductor region and a region separated from the second electrode. A method for manufacturing a surface-emitting LED array in which the surface-emitting LEDs according to claim 4 are arranged in an array.

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