JP4247685B2 - Multi-track audio control apparatus and multi-track audio control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable the holding definition of audio data reducing a signal processing quantity of audio data holding phases between tracks as it is. <P>SOLUTION: The apparatus has a plurality of audio input/output parts 21A to 21L having input/output control parts 34 changing forcedly read-out addresses when audio data D1 are read out from a ring buffer memory 40 in which audio data D1 of one track are written, a plurality of tracks previously specified are made to be one group, an address position at which the variation of a signal level is less between a signal level of the audio data D1 corresponding to the read-out address before a change by the input/output control part 34 in tracks of half the number or more in the group and a signal level of the audio data D1 corresponding to a read-out address after change is decided as the read-out address after changes in all tracks in the group. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to a multi-track audio control apparatus and a multi-track audio control method, and is suitable for application to, for example, a commercial video tape recorder used in a broadcasting station.

  Conventionally, commercial videotape recorders can respond to requests such as recording a 55-minute program by putting commercials in a recorded normal one-hour program, or broadcasting an hour-long program. Has been made.

  In such a case, the video tape recorder performs a variable speed playback process for 55 minutes or 1 hour 5 minutes by frame thinning, frame interpolation or the like within a range that does not give an unnatural impression to humans regarding the video of the program. (For example, refer to Patent Document 1).

Also, in video tape recorders, simply performing data thinning and data interpolation for audio, as with video, does not maintain the continuity of the audio and gives the user an unnatural impression. For example, audio such as crossfade processing By applying the process, the user feels as comfortable as possible.
Japanese Patent Laid-Open No. 2000-23105

  By the way, in the video tape recorder having such a configuration, for example, since audio signal processing is performed using 12 audio tracks, when the program play function is operated, data interpolation or data thinning is performed in each audio track, or Since cross fading processing and the like are performed, there is a possibility that the phase between the audio tracks is shifted. In such a case, there is a problem that sound image localization in stereo, surround, etc. is distorted.

  In addition, the video tape recorder has a problem in that it is difficult to maintain the quality of the audio data because the amount of signal processing becomes enormous when the crossfading process is performed on all 12 audio tracks.

  The present invention has been made in consideration of the above points, and a multi-track audio control apparatus and a multi-track audio control apparatus capable of reducing the signal processing amount of audio data and maintaining the quality of the audio data while maintaining the phase between the audio tracks. It is intended to propose a track audio control method.

  In order to solve this problem, the multi-track audio control apparatus of the present invention is a multi-track audio control apparatus having an audio data input / output unit corresponding to one track of audio data for a plurality of tracks, which is input from the outside. An audio data input / output unit having a memory for storing audio data, and a read address changing means for forcibly changing a read address when the audio data is read from the memory, and a plurality of tracks designated in advance as one Corresponding to the signal level of the audio data corresponding to the read address before the change by the read address changing means and the read address after the change in the grouping means to be a group and tracks corresponding to the number of the predetermined ratio or more in the group Audio data signal level A signal level change is small address location between, and be provided with a read address determining means to align the phase by determining the read address after the change in all the tracks in the group.

  As a result, the read address can be forcibly changed without changing the phase in all the tracks in the group, so that the amount of signal processing can be greatly reduced, and the read address can be changed without changing the audio data itself. The change in the signal level before and after the change can be suppressed to a small level, and the quality of the audio data can be maintained.

  In the multi-track audio control method according to the present invention, the audio data further comprises a read address changing means for forcibly changing the read address when reading the audio data from the memory for storing the audio data of one track inputted from the outside. A multi-track audio control method for controlling an input / output unit for a plurality of tracks, a grouping step in which a plurality of predetermined tracks are grouped into one group, and a track corresponding to a number greater than a predetermined ratio in the group In the group, an address position having a small signal level change between the signal level of the audio data corresponding to the read address before the change by the read address changing means and the signal level of the audio data corresponding to the read address after the change is Changes in all tracks It was provided a read address determining step to align the phase by determining the read address.

  As a result, the read address can be forcibly changed without changing the phase in all the tracks in the group, so that the amount of signal processing can be greatly reduced, and the read address can be changed without changing the audio data itself. The change in the signal level before and after the change can be suppressed to a small level, and the quality of the audio data can be maintained.

  According to the present invention, the read address can be forcibly changed without changing the phase in all the tracks in the group, so that the signal processing amount can be greatly reduced and the audio data itself can be read without changing. Audio signal quality can be maintained by minimizing changes in the signal level before and after the address change, thus reducing the signal processing amount of the audio data while maintaining the phase between the audio tracks. A multi-track audio control apparatus and a multi-track audio control method that can maintain data quality can be realized.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) Principle of the present invention In the present invention, when the program play function of the video tape recorder is operated, the video of the program read from the video tape is also subjected to variable speed reproduction processing such as frame thinning or frame interpolation. Regardless, the principle of the audio input / output unit to keep the audio pitch unchanged will be described first.

  As shown in FIG. 1, in the audio input / output unit, audio data is written into the ring buffer 40 having a total of 2048 slots at a writing speed of 48 [kHz], for example, and is read from the ring buffer 40 at a constant reading speed of 48 [kHz]. In the case of the standard reproduction process in which the audio data is read, the pitch of the audio output based on the audio data does not change.

  However, in the audio input / output unit, when the program play function of the video camera operates, the audio data is written into the ring buffer 40 at a writing speed of 48 [kHz] ± 5% in accordance with the video variable speed playback process. The audio data is read out at a constant 48 [kHz].

  The reason why the audio data is read at a constant speed of 48 [kHz] is to prevent the change of the pitch of the audio output based on the read audio data.

  In the audio data reading in this case, there is a variation of ± 5% in the writing speed of the audio data, so that a deviation occurs between the writing timing and the reading timing, and the writing speed is 48 [kHz] −5%. In some cases, the read data will eventually overtake the write data, and when the writing speed is 48 [kHz] + 5%, the write data will eventually overtake the read data.

  As shown in FIG. 2, when the audio data has a writing speed of 48 [kHz] −5%, the reading speed 48 [kHz] is constant, so the reading speed is faster than the writing speed. While (p) advances one round (2048 slots), the write data D (r) advances 1945 slots or 1946 slots (2048 slots × 0.95 = 1945.6 slots). For this reason, the read data D (p) catches up with and overtakes the write data D (r) every approximately 20 laps (2048 ÷ (2048−1945.6) = 20 laps).

  As shown in FIG. 3, when the audio data has a writing speed of 48 [kHz] + 5%, the reading speed 48 [kHz] is constant, so the writing speed is faster than the reading speed, and the reading data D While (p) advances one round (2048 slots), write data D (r) advances 2150 slots or 2151 slots (2048 slots × 1.05 = 2150.4 slots). For this reason, the write data D (r) catches up and overtakes the read data D (p) every about 20 laps (2048 ÷ (2150.4−2048) = 20 laps).

  In this way, when the read data D (p) overtakes the write data D (r) or the write data D (r) overtakes the read data D (p), the read data D (p ) Cannot be maintained and noise is generated in the output voice.

  Therefore, as shown in FIG. 4, in the audio input / output unit, for example, when the write data D (r) overtakes the read data D (p), in addition to the ring buffer 40, a cross fade buffer for 256 steps, that is, 256 slots is separately provided. Prepare and copy the read data D (p) before being overtaken by the write data D (r) to the cross-fade buffer for 256 steps, and when the write data D (r) is overtaken, A so-called cross-fade process can be executed by fading in the read data D (p) immediately after being written while gradually copying out the copied read data D (p).

  That is, in the cross-fade processing when the write address exceeds the read address as shown in FIGS. 5A to 5D, the audio input / output unit first reads the read data D (p as shown in FIG. The read data D (p) is copied to the crossfade buffer for 256 slots immediately before the write data D (r) is caught up.

  Next, as shown in FIG. 5B, the audio input / output unit gradually fades out the signal level of the read data D (p) read from the crossfade buffer from the normal level and reads it from the ring buffer 40. The signal level of read data D (p) is gradually faded in from zero.

  Here, in the audio input / output unit, as shown in FIG. 5C, the write data D (r) overtakes the read data D (p) in the ring buffer 40, and after this point, the ring buffer is still read. Unread read data D (p) is overwritten with write data D (r) (shaded area in the figure).

  At this time, the read data D (p) on the ring buffer 40 becomes discontinuous at the overtaken place, but at this point, the signal level of the read data D (p) read from the ring buffer 40 is still sufficiently small. At the same time, since the signal level of continuous read data D (p) read from the crossfade buffer is sufficiently high, the audio input / output unit can listen to the audio even when reading such discontinuous read data D (p). Does not give a sense of incongruity.

  Subsequently, the audio input / output unit reads out from the ring buffer 40 while gradually fading out the read data D (p) of the cross-fade buffer which has been read from the ring buffer 40 so far and continuously. The write data D (r) immediately after the previous write data D (p), which is discontinuous with the read data D (p) that has been written, is read as the read data D (p) “one round ahead” and gradually fades in. As a result, the cross-fade process proceeds, and the read data D (p) of the ring buffer 40 is gradually switched from the read data D (p) of the cross-fade buffer.

  Thereafter, the audio input / output unit completes the cross-fade processing as shown in FIG. 5D, and the write data D (r) immediately after being overwritten by the write data D (r) is read data D (p). Read out at a normal signal level.

  In this case, the audio input / output unit can prevent noise generated when the write data D (r) passes the read data D (p) by the cross-fade process. Despite being discarded (thinned out data), the continuity of the audio data can be maintained in terms of the user's audibility.

  In the cross-fade process when the read address exceeds the write address as shown in FIGS. 6A to 6D, the audio input / output unit first writes the write data D ( Before r) is caught up with the read data D (p), the read data D (p) is copied to the crossfade buffer for 256 slots.

  Next, as shown in FIG. 6B, the audio input / output unit reads and outputs the read data D (p) immediately after being written in the ring buffer 40 as the write data D (r). Is gradually faded out from the normal level, and the read data D (p) (shown by hatching in the figure) that has already been read once is read out from the cross fade buffer for the second time and output. Gradually fade in.

  At this time, since the read data D (p) on the crossfade buffer is “one cycle before”, it is discontinuous with the read data D (p) read from the ring buffer 40 so far. Then, the signal level of the read data D (p) read from the cross-fade buffer is still sufficiently low, and the read data D (read from the ring buffer 40 that is continuous with the read data D (p) read from the ring buffer 40 until now is read. Since the signal level of p) is sufficiently high, the audio input / output unit does not give a sense of incongruity to the user who listens to the audio even when reading such discontinuous read data D (p).

  Subsequently, the audio input / output unit gradually fades out the read data D (p) continuous with the read data D (p) read from the ring buffer 40 so far, while reading the data read from the ring buffer 40 so far. D (p) is the fade-in of the discontinuous read data D (p) “one round before”, and the crossfade process proceeds. From the read data D (p) of the ring buffer 40 Gradually, the data is switched to the read data D (p) “one round before” in the crossfade buffer.

  Thereafter, as shown in FIG. 6C, the audio input / output unit overtakes the write data D (r) by the read data D (p) in the ring buffer 40, and after this point, the ring buffer 40 has already performed once. Read read data D (p) is read for the second time. (The shaded area in the figure).

  At this time, the read data D (p) on the ring buffer 40 becomes discontinuous at the overtaken portion, but at this point, the signal level of the read data D (p) already read from the ring buffer 40 is sufficiently small, At the same time, since the signal level of read data D (p) “one round before” read from the cross-fade buffer is already sufficiently high, the audio input / output unit can read such discontinuous read data D (p). The user who listens to the audio does not feel uncomfortable.

  After the completion of the cross-fade process, the audio input / output unit reads the read data D (p) to be read for the second time from the ring buffer 40 at a normal signal level as shown in FIG.

  In this case, the audio input / output unit can prevent noise that occurs when the read data D (p) overtakes the write data D (r) due to the cross-fade processing, so that the same audio data stored in the ring buffer 40 is again stored. In spite of reading and data interpolation, the audibility of the user can maintain the continuity of the audio data.

  In this case, since the read data D (p) overtakes the write data D (r), the write data D (r) becomes the read data D (p) when the 256-step cross-fade processing is completed. The write data D (r) is not caught up with the read data D (p) while the write data D (r) advances through the ring buffer 40 for about 20 laps.

  Thus, in the video tape recorder, when the write data D (r) is overtaken by the read data D (p), or when the read data D (p) is overtaken by the write data D (r), the crossfade process is performed. However, since signal processing of audio data is performed using twelve audio tracks, the amount of signal processing corresponding to the crossfade processing is enormous, which is not efficient. In addition, in the crossfade process, since two types of audio data are superimposed, the quality of the audio is inevitably lowered.

  Therefore, as shown in FIG. 7, in the audio input / output unit, when the write data D (r) catches up with the read data D (p) due to the speed difference between the write speed and the read speed, the read address Is forcibly changed to the end of the write address to execute a read address jump process.

  At this time, the audio input / output unit forcibly changes the read address to the end of the write address, but if the read address jump process is executed without considering anything, the audio data at the read address before the address change There is a large difference in signal level with the audio data at the read address after the address change, and the continuity of the audio data cannot be maintained and noise may be generated.

  Therefore, in the audio input / output unit, the position where the signal level difference of the audio data is small between the audio data at the read address before the address change and the audio data at the read address after the address change is set as the read address after the change. It is made to decide.

  Specifically, as shown in FIG. 8, when the signal level of the audio data is in the vicinity of the zero cross where the audio data crosses the zero level, the audio input / output unit forcibly causes the current read address to jump to the end of the write address. It is made like that.

  That is, for example, when the write address catches up with the read address, the audio input / output unit is behind the write address that is about one round ahead of the ring buffer 40 from the read address before the address change at the present time. The position where the signal level of the audio data is near the zero cross is determined as the read address after the address change.

  At this time, in the audio input / output unit, the address jump is performed from the read address immediately before the zero crossing to the read address immediately after the zero crossing, so that the continuity of the audio data is increased before and after the address jump. It is designed to maintain and not degrade the audio quality.

  However, the audio input / output unit is not necessarily limited to this. The address jump from the read address immediately before the zero cross to the read address immediately before the zero cross, or the address jump from the read address immediately after the zero cross to the read address immediately after the zero cross, or the zero cross. An address jump may be made from the read address immediately after to the read address immediately before the zero cross.

  Incidentally, as shown in FIG. 9, the audio input / output unit uses a ring buffer 40 having 2048 slots. For example, when the writing speed of audio data is faster than the reading speed, the writing data overtakes the reading data. The minimum delay is reached at the moment, and the delay amount gradually increases thereafter.

  As shown in FIG. 10, the audio input / output unit has a minimum delay at the moment when the read data exceeds the write data, for example, when the read speed of the audio data is faster than the write speed, and then the delay amount gradually increases. To go.

  Therefore, in the audio input / output unit, the read address is set to a position separated from the write address of the audio data by a half value (1024 slots) of the ring buffer 40, and the write timing of the write data D (r) is set. It is desirable to hold the initial delay (21.3 msec) of 1024 slots corresponding to the half circumference of the ring buffer 40 as a delay amount between the read timing of the read data D (p) and the read data D (p).

  However, the audio input / output unit causes the read address to jump after the write address before the read data is caught up with the write data, for example, when the write speed is faster than the read speed. Therefore, control is performed within a certain range (eg, 1024 slots ± 100 slots) that does not deviate significantly from the initial delay of 1024 slots.

  Specifically, as shown in FIG. 11A, the audio input / output unit eventually catches up with the write address when the write speed is faster than the read speed. When k <1024, the read address is forcibly jumped to a position advanced a little further.

  As a result, the audio input / output unit can keep the difference value k between the read address and the write address constant to some extent even when the write speed is faster than the read speed. The delay amount within a certain range that does not deviate can be maintained.

  As shown in FIG. 11B, in the audio input / output unit, when the reading speed is faster than the writing speed, the difference between the reading address and the writing address widens, and the writing address eventually catches up with the reading address. Therefore, the difference value k between the read address and the write address is calculated, and when k> 1024, the address jump is forcibly made to a position where the read address is slightly returned from the present time.

  As a result, the audio input / output unit can keep the difference value k between the read address and the write address constant to some extent even when the read speed is faster than the write speed. The delay amount within a certain range that does not deviate can be maintained.

  By the way, as shown in FIG. 12, the audio data written into the ring buffer 40 in slot units is described in the preceding stage of the actual data indicated by MSB (Most Significant Bit) to LSB (Least Significant Bit) and the actual data. Header.

  In the header of the audio data, “Jump” describes flag information indicating that the current address is a jump address (details will be described later) when the audio data is audio data to be address jumped. The group ID that identifies the group when the desired tracks among the 12 tracks are related to each other is described by 3 bits of “GroupID2”, “GroupID1”, and “GroupID0”, and is converted into “Offset” by analog-digital conversion. The offset amount for removing the DC component superimposed on the subsequent audio data is described.

  As shown in FIG. 13, when a direct current component is superimposed on audio data, the signal level of the entire waveform is increased by the direct current component, and zero crossing in the original audio data on which the direct current component is not superimposed cannot be detected.

  Therefore, the audio input / output control device detects an offset amount for removing the DC component in advance and describes it in “Offset” in the header information of the audio data. Therefore, the audio input / output control device detects a zero cross in the original audio data on which the DC component is not superimposed by detecting a virtual zero cross in which the DC component is removed in advance for the audio data on which the DC component is superimposed. Has been made to get.

  In the header of the audio data (FIG. 12), flag information is described when the signal level of the audio data is a low level of −60 [dB] or less as “Low level”, and the audio data is zero-crossed as “zcFlag1”. The flag information is described immediately before (FIG. 8), and the flag information is described as “zcFlag0” when the audio data is immediately after zero crossing (FIG. 8).

  Therefore, the audio input / output unit refers to the header in the audio data for each 2048 slot and confirms the flag information of “zcFlag1” and “zcFlag0” to determine whether the signal level of the audio data is immediately before the zero cross or just after the zero cross. It is designed so that it can be determined instantaneously.

  Also, in the audio data header, for audio data with a DC component superimposed, flag information is described as “offset zcFlag1” when the original audio data with no DC component superimposed is immediately before the zero cross, and “offset zcFlag0” The flag information is described when the original audio data on which no DC component is superimposed is immediately after zero crossing.

  By the way, as shown in FIG. 8, the audio input / output unit monitors the signal level of the audio data for each slot of the ring buffer 40. As a result, when the signal level of the audio data is equal to or less than zero level, the sign bit “1” representing minus is set as “0”, and “0” representing plus is set as a sign bit when exceeding the zero level.

  Therefore, the audio input / output unit sets “1” as the sign bit because the signal level of the audio data written at the time immediately before the zero crossing (indicated by the symbol W) is equal to or lower than the zero level, Since the signal level of the audio data (shown by a) is also equal to or lower than the zero level, “1” is set as the sign bit, and the signal level of the audio data one time later (shown by the symbol b) with respect to the time immediately before the zero cross Since “0” exceeds the zero level, “0” is set as the sign bit.

  Similarly, the audio input / output unit sets “0” as the sign bit because the signal level of the audio data written at the time immediately after the zero crossing (indicated by the symbol W) exceeds the zero level, and one time before that time ( Since the signal level of the audio data (indicated by symbol a) is less than or equal to zero level, “1” is set as the sign bit, and the audio data signal after one point (indicated by symbol b) is set immediately after the zero crossing. Since the level exceeds the zero level, “0” is set as the sign bit.

  Therefore, the audio input / output unit can determine the timing at which the code bit changes from “1” to “0” at the time of zero crossing by monitoring the code bit for each slot. Can identify the slot indicating “1” as the audio data immediately before the zero cross and set “1” as the flag information of “zcFlag1”, and the slot immediately after the zero cross for the sign bit indicating “0”. “0” is set as flag information of “zcFlag0” that can be grasped as data.

  Note that the audio input / output unit also sets “1” or “0” for the flag information of “offset zcFlag1” and “offset zcFlag0” based on the sign bit, similarly to “zcFlag1” and “zcFlag0”. ing.

(2) Configuration of Multitrack Audio Control Device (2-1) Configuration of Video Tape Recorder As shown in FIG. 14, the video tape recorder 1 inserts the video tape 2 into the inside through the tape insertion port 3, so that the video Video data consisting of video data and 12-track audio data is recorded on the tape, and the video data can be read from the video tape 2 and reproduced. At this time, the video tape recorder 1 can perform variable speed reproduction processing for changing the reproduction speed to 48 [kHz] ± 5% in addition to reproducing the video data recorded on the video tape 2 at the standard speed.

  The video tape recorder 1 is provided with an operation button group 4 for receiving a user operation, a touch panel 5 for displaying an operation status of the video tape recorder 1 and receiving a user operation.

  Further, the video tape recorder 1 is configured to be able to form a group by combining a plurality of desired audio tracks out of 12 tracks, and displays a group setting screen as shown in FIG. 15 on the touch panel 5 and a button BT1. In addition, by operating the BT2 and the like by the user, each track (CH: displayed by channel number) can be set so as to have a group configuration desired by the user.

  In the present embodiment, track 1, track 2, and track 3 (represented as “CH1”, “CH2”, and “CH3” in FIG. 15 respectively) among the 12 tracks of track 1 to track 12) are grouped into one group ( A case where “Group A” is set in FIG. 15 will be described below.

(2-2) Circuit Configuration of Multitrack Audio Control Device By the way, a multitrack audio control device 10 as shown in FIG. The multitrack audio control apparatus 10 is configured to control the audio control units 20A to 20L for 12 tracks corresponding to each audio track by the multitrack control unit 11.

  The multitrack control unit 11 is controlled by a CPU (Central Processing Unit) 12, and a basic program such as an OS (Operational System) read from a ROM (Read Only Memory) 14 via a bus 13, an address jump processing program, and the like These various application programs are developed in a RAM (Random Access Memory) 15 and executed to execute various processes.

  The audio control units 20A to 20L correspond to the tracks 1 to 12, respectively. By controlling the audio data D1A to D1L for one track based on the control of the multitrack control unit 11, each of the audio control units 20A to 20L corresponds to one track. Audio data D5A to D5L are generated and output.

  Since the audio control units 20A to 20L have the same circuit configuration, only the audio data control unit 20A corresponding to the track 1 will be described below.

  Inside the audio control unit 20A, the audio input / output unit 21A generates an audio data D2A by performing an address jump process (details will be described later) on the audio data D1A based on the control of the multitrack control unit 11. This is supplied to the crossfade circuit 23A and the switch 24A.

  The crossfade buffer 22A corresponds to the crossfade buffer shown in FIGS. 5 and 6, temporarily stores audio data for 256 slots, and supplies this as audio data D3A to the crossfade circuit 13A.

  The crossfade circuit 23A generates audio data D4A by performing crossfade processing (FIGS. 5 and 6) on the audio data D2A and D3A based on the control of the multitrack controller 11, and generates the audio data D4A. To supply.

  The switch 24A selects either the terminal 24A1 to which the audio data D2A is supplied or the terminal 24A2 to which the audio data D4A is supplied on the basis of the switching signal SEL sent from the multitrack control unit 11. The audio data supplied to the terminal is output as audio data D5A. Incidentally, the switch 24A normally selects the terminal 24A1 side, and selects the terminal 24A2 side only when the crossfading process is performed.

  As described above, the audio data control unit 10A, based on the control of the multitrack control unit 11, performs either one of the audio data D2A subjected to the address jump processing by the audio input / output unit 21A or the audio data D4A subjected to the crossfade processing. The audio data D5A is output.

(2-3) Configuration of Audio Input / Output Unit In practice, as shown in FIG. 17, the audio input / output unit 21A converts the audio data D1A for each 2048 samples into the low level detector 32 in accordance with the ring buffer 40A having a 2048 slot configuration. The zero cross detector 33 and the ring buffer 40A are input.

  The low level detector 32A is configured to detect that the signal level of the audio data D1A is a low level of −60 [dB] or less in order for the input / output control unit 34A to determine zero crossing. Is output to the input / output control unit 34A having a CPU configuration.

  In practice, as shown in FIG. 18, the low level detector 32A enters from the start step of the routine RT1 and proceeds to the next step SP1, where the signal level of the audio data D1 written into the ring buffer 40A is −60 [dB] or less. It is determined whether the level is low.

  If a negative result is obtained here, the low level detector 32A moves to the next step SP2, sets “0” as the low level flag (LL flag), moves to the next step SP4, and ends the processing. On the other hand, if a positive result is obtained in step SP1, the low level detector 32A moves to the next step SP3, sets “1” as the low level flag, moves to the next step SP4, and ends the processing.

The zero cross detector 33A monitors the signal level of the audio data D1 to detect whether the signal level of the audio data crosses the “0” level, and outputs the detection result to the input / output control unit 34A. To do.

  In practice, the zero-cross detector 33A enters from the start step of the routine RT2 as shown in FIG. 19 and moves to the next step SP11, where the detection result of the offset detector 35A determines whether or not a DC component is superimposed on the audio data D1A. Determine based on.

  Here, as shown in FIG. 20, the offset detector 35A calculates an average value by dividing the total value of the signal levels of the audio data D1A sequentially written in the 2048 slots of the ring buffer 40A by 2048, and the average value is converted into a direct current. It is detected as a component offset amount.

  If a negative result is obtained in step SP11, the zero-cross detector 35A moves to the next step SP13 without performing any processing because no direct current component is superimposed on the audio data D1A.

  On the other hand, if an affirmative result is obtained in step SP11, the zero cross detector 35A has a direct current component superimposed on the audio data D1A, so that the audio data D1A written to the ring buffer 40 is assumed to have no direct current component. After that, the process proceeds to the next step SP13.

  In step SP13, as shown in FIG. 8, the zero-cross detector 35A determines whether or not the sign bit at the next time point (indicated by the symbol b) of the audio data D1A at the current time point (indicated by the symbol W) is “0”. When a negative result is obtained, the process proceeds to the next step SP16, whereas when a positive result is obtained, the process proceeds to the next step SP14.

  In step SP14, the zero-cross detector 35A determines whether or not the sign bit of the audio data D1A at the present time (indicated by the symbol W) is “1”, and if a negative result is obtained, the sign bit that becomes a sequence of the symbols Wb Is “00”, that is, zero crossing is not performed. At this time, the process proceeds to the next step SP16.

  On the other hand, if an affirmative result is obtained in step SP14, this indicates that the sign bit of the sequence of symbols Wb is “10”, that is, zero crossing. At this time, the zero cross detector 35A performs the next step. After moving to SP15 and setting “1” as the flag information of “zcFlag1” immediately before the zero cross, the process moves to step SP19 and the process is terminated.

  In step SP16, the zero cross detector 35A determines whether or not the sign bit at the previous time point (indicated by the symbol a) of the audio data D1A at the current time point (indicated by the symbol W) is “1”, and a negative result is obtained. Then, the process proceeds to step SP19 to end the process, whereas if a positive result is obtained, the process proceeds to the next step SP17.

  In step SP17, the zero cross detector 35A determines whether or not the sign bit of the audio data D1A at the present time (indicated by the symbol W) is “0”, and if a negative result is obtained, the sign bit that becomes a sequence of the symbols aW. Is “11”, that is, it is detected that zero crossing has not occurred, and the process proceeds to step SP19 to end the process.

  On the other hand, if an affirmative result is obtained in step SP17, this indicates that the sign bit of the sequence of symbols aW is “10”, that is, zero crossing. At this time, the zero cross detector 35A performs the next step. After moving to SP18 and setting “1” as the flag information of “zcFlag0” immediately after zero crossing, the process moves to step SP19 and the process is terminated.

  By the way, the multi-track audio control device 10 (FIG. 16) performs low level detection processing and zero crossing on audio data D1A to D1L at the same timing in the audio input / output units 21A to 21L of the audio data control units 20A to 20L corresponding to each track. The detection process is executed in parallel.

  At this time, the multi-track control unit 11 uses the low level flags “zcFlag0” and “zcFlag1” for all tracks in the same group (that is, tracks 1 to 3) set in the video tape recorder 1 (FIG. 14). It is determined whether or not the address jump should be performed simultaneously for all tracks in the group.

  In practice, the CPU 12 of the multi-track control unit 11 enters from the start step of the routine RT3 as shown in FIG. 21 and proceeds to the next step SP21, and refers to the header of the audio data D1 at this time for all tracks in the group. Then, it is determined whether or not “1” is set as the flag information of “zcFlag1” or “zcFlag0” of the header.

  If a positive result is obtained here, this means that "1" is set as the flag information of "zcFlag1" or "zcFlag0", that is, the audio data D1 to be read from the next read address is immediately before the zero cross or just after the zero cross. In this case, the CPU 12 proceeds to the next step SP23.

  On the other hand, if a negative result is obtained in step SP21, this indicates that there is one or more tracks in the group that are neither immediately before the zero crossing nor immediately after the zero crossing at this timing. Control goes to step SP22.

  In step SP22, the CPU 12 determines whether or not at least one of the low level flag “zcFlag0” and “zcFlag1” is “1” in all tracks in the group.

  If a positive result is obtained here, this means that there are tracks in the group immediately before zero crossing or not immediately after zero crossing, but the signal level is very low in all tracks, so even if address jumping at this timing, address jumping This indicates that the change width of the audio signal before and after is very small, and the possibility that the listener feels uncomfortable is extremely low. At this time, the CPU 12 proceeds to the next step SP23.

  On the other hand, if a negative result is obtained in step SP22, this means that an address jump should not be performed at this timing because there is a track with a high signal level in the group at this timing, not immediately before or after the zero crossing. At this time, the CPU 12 moves to the next step SP24 and ends the process.

  In step SP23, the CPU 12 determines that the addresses of the audio data D1A to D1C currently processed in the audio input / output units 21A to 21C are suitable for the address jump, and issues an instruction to the audio input / output units 21A to 21C. Thus, by setting “1” as flag information of “Jump” (FIG. 12) in the header of each audio data D1A to D1C, the current address is set as a jump address, and the process proceeds to the next step SP24 and ends. .

  As described above, the CPU 12 sets at least an address immediately before the zero cross, immediately after the zero cross, or a low level as a jump address in all the tracks in the group. The signal level change width in the data D1 is minimized.

  Incidentally, when a plurality of groups are set, the CPU 12 executes the routine RT3 of the jump address detection processing procedure for each group.

  As described above, the ring buffer 40A has a 2048 slot configuration, and the input audio data D1A is written at a writing speed of 48 [kHz] ± 5% in accordance with the write address supplied from the write address generator 36A (FIG. 17). The data is written for each slot, and the audio data D1A is read and output at a constant reading speed of 48 [kHz] according to the read address supplied from the read address generator 37A.

  At this time, the write address generator 36 and the read address generator 37 generate and input a write address and a read address based on the write address information AW and the read address information AR supplied from the multitrack controller 11 (FIG. 16). The data is sent to the output control unit 34.

  Based on the write address and the read address, the input / output control unit 34 has the actual write address and the actual read address, and the write address information AW and the read address information AR supplied from the multitrack control unit 11. It is determined whether or not they match. If they do not match, the write address and the read address are corrected.

(3) Reading Address Jump Processing Procedure By the way, the video tape recorder 1 (FIG. 14) can change the playback speed of video data based on a user operation instruction as described above. In this case, the writing speed of the audio input / output units 21A to 21L (FIG. 17) to the ring buffers 40A to 40L is faster than the reading speed.

  At this time, the multi-track control unit 11 of the multi-track audio control device 10 maintains the continuity without causing a change in the pitch of the audio while maintaining the phase between the tracks set in the same group according to the address jump processing program. The read address is jumped to an address, and the read address jump processing procedure at this time will be described with reference to the flowchart of FIG.

  In practice, the CPU 12 of the multi-track control unit 11 enters from the start step of the routine RT4, moves to step SP31, and sets the value of the current read address information AR to be read from the ring buffer 40 of each audio input / output unit 21 to “ By adding and outputting “1”, the process proceeds to the next read address, and the process proceeds to the next step SP32.

  In step SP32, the CPU 12 causes each audio input / output unit 21 to send out the header of the audio data D1 written in the slot of the ring buffer 40 corresponding to the next read address, and in all tracks set in the same group, It is determined whether or not “1” is set as flag information of “zcFlag1” or “zcFlag0” in the header.

  If a positive result is obtained here, this means that “1” is set as flag information of “zcFlag1” or “zcFlag0” in all tracks in the same group, that is, reading from the next read address in all tracks. This indicates that the audio data D1 should be data immediately before or after the zero crossing. At this time, the control unit 4 proceeds to the next step SP33.

  In step SP33, the CPU 12 calculates a difference value k between the read address and the write address based on the read address information AR and the write address information AW held in the RAM 15, and the difference value k is 256 (slots). ), The difference value k is greater than 1024 (slots), or the difference value k is in the range of 256 (slots) to 1024 (slots).

  Here, as shown in FIG. 23, when the difference value k is larger than 1024 (slot), this means that there is a considerable margin until the read address catches up with the write address. The CPU 12 proceeds to step SP42 and ends without performing the read address jump process.

  If the difference value k is in the range of 256 (slots) to 1024 (slots), this means that the write address gradually catches up with the read address, and the difference between the read address and the write address is the initial delay. This means that there is a possibility that a certain range (for example, 1024 slots ± 100 slots) has come out. At this time, the CPU 12 proceeds to the next step SP34.

  In step SP34, when the CPU 12 jumps the read address, “1” is set as flag information of “Jump” in the header of the audio data D1, and the read address of the address jump scheduled to be located near the read address. Is the forward zero cross address, and the difference fk between the forward zero cross address and the read address is calculated.

  If the difference fk is 1024 (slots) or more, the CPU 12 is likely to deviate from a predetermined initial delay range (eg, 1024 slots ± 100 slots) if the read address is jumped to the forward zero cross address. The process proceeds to step SP42 and ends without performing the read address jump process.

  On the other hand, when the difference fk is smaller than 1024 (slots), the CPU 12 is likely to fall within a certain initial delay range (for example, 1024 slots ± 100 slots) even if the read address is jumped to the forward zero cross address. In order to perform the address jump process, the process proceeds to the next step SP36.

  If the difference value k is smaller than 256 (slot) in step SP33, this means that the read address is in a state immediately before the write address is caught up, and the CPU 12 proceeds to the next step SP35.

  In step SP35, when the CPU 12 jumps the read address, “1” is set as “Jump” flag information in the header of the audio data D1, and the read address of the address jump scheduled to be located far from the read address. Is the more forward zero cross address, and the difference mk between the read address and the more forward zero cross address is calculated.

  If the difference mk is 1024 (slots) or more, the CPU 12 is likely to deviate from a certain initial delay range (for example, 1024 slots ± 100 slots) if the read address is jumped to the more forward zero cross address. Therefore, the process proceeds to step SP42 and ends without performing the read address jump process.

  On the other hand, when the difference mk is smaller than 1024 (slots), the CPU 12 is likely to be within a certain initial delay range (for example, 1024 slots ± 100 slots) even if the read address is jumped to the more forward zero cross address. The process proceeds to the next step SP36 to perform read address jump processing.

  In step SP36, the CPU 12 skips the audio data D1 by jumping the read address to the forward zero cross address or the more forward zero cross address for all tracks in the group, and the read address is caught up to the write address. In addition, the continuity between the audio data D1 read before the address jump and the audio data D1 read after the address jump is maintained, and the process proceeds to the next step SP42 to end the processing.

  On the other hand, if a negative result is obtained in step SP32, this means that there is a track in which “0” is set as the flag information of “zcFlag1” or “zcFlag0” in the group, that is, zero crossing is not performed at this timing. This indicates that there is audio data D1, and at this time, the CPU 12 proceeds to the next step SP37.

  Here, even if the audio data D1 that does not zero-cross is included in the group, the CPU 12 may have no problem in hearing even if the signal level of the audio data D1 is sufficiently low (−60 [dB] or less). Therefore, the process proceeds to the processing after the next step SP37.

  In step SP37, the CPU 12 refers to the header of the audio data D1, and “1” is set as flag information of any of the “low level (LL) flag”, “zcFlag1”, or “zcFlag0” of the header. It is determined how much the number of tracks (hereinafter referred to as the number of flag set tracks) is relative to the total number of tracks in the group.

  Here, if the number of flag set tracks matches the number of all tracks in the group, this is because any of the “low level flag”, “zcFlag1” or “zcFlag0” is “1” in all the tracks in the group. , The signal level is close to “0” in all the tracks in the group, and even if the address jumps, the signal level is continuous in all the tracks, indicating that there is almost no sense of incongruity. At that time, the CPU 12 moves to step SP33 and performs the same processing as when either “zcFlag1” or “zcFlag0” is “1” in all tracks in the group.

  If the number of flag set tracks is less than half of the total number of tracks in step SP37, this means that none of the “low level flag”, “zcFlag1” or “zcFlag0” is “1” in many tracks in the group. In other words, the signal level is a value far from “0”, and if the address jump is performed at such an address, the signal level becomes discontinuous, indicating that it is not the timing to perform the read address jump process. At this time, the CPU 12 moves to step SP42 and ends the process.

  On the other hand, if the number of flag set tracks is more than half of the total number of tracks in step SP37, this means that one of “low level flag”, “zcFlag1” or “zcFlag0” is “1” in many tracks in the group. That is, the signal level is a value close to “0”. From such an address, any of the “low level flag”, “zcFlag1” or “zcFlag0” is “1” in all the tracks in the group. When the address jump to the jump address “”, the signal level is almost continuous in many tracks, indicating that there is almost no sense of incongruity in hearing. At this time, the CPU 12 proceeds to the next step SP38.

  In step SP38, the CPU 12 calculates the difference value k between the read address and the write address in the same manner as in step SP33, and determines whether or not the difference value k is 256 (slots) or more.

  Here, when the difference value k is 256 (slots) or more, this means that the write address has caught up with the read address, but there is still some margin, so this is not the timing, and zero crossing is next performed on all tracks. This indicates that it is preferable to perform the address jump at the timing. At this time, the CPU 12 proceeds to the next step SP42 and ends without performing the address jump.

  In step SP39, as in step SP35, the CPU 12 sets "1" as flag information of "Jump" in the header of the audio data D1 when the read address is jumped to an address, and is located far from the read address. A read address to be address jumped is a more forward zero cross address, and a difference mk between the read address and the more forward zero cross address is calculated.

  If the difference mk is 1024 (slots) or more, the CPU 12 is likely to deviate from a certain initial delay range (for example, 1024 slots ± 100 slots) if the read address is jumped to the more forward zero cross address. Therefore, the process proceeds to step SP42 and ends without performing the read address jump process.

  On the other hand, when the difference mk is smaller than 1024 (slots), the CPU 12 is likely to be within a certain initial delay range (for example, 1024 slots ± 100 slots) even if the read address is jumped to the more forward zero cross address. The process proceeds to the next step SP40 to perform read address jump processing.

  In step SP40, as in step SP36, the CPU 12 skips the audio data D1 by jumping the read address to the more forward zero cross address for all tracks set in the same group, and the read address becomes the write address. Is prevented in advance, and the process proceeds to the next step SP41.

  At this time, among the tracks in the group, the CPU 12 has a signal level that is substantially continuous before and after the address jump in a track in which any of the “low level flag”, “zcFlag1”, or “zcFlag0” is “1”. However, the track level in which all of the “low level flag”, “zcFlag1” or “zcFlag0” are “0” is a value far from “0” because the signal level before the address jump is a value. The signal level becomes discontinuous due to the address jump, and the sound quality is remarkably deteriorated.

  For this reason, in step SP41, the CPU 12 performs cross-fading as shown in FIG. 5 for each track in the group in which all of the “low level flag”, “zcFlag1”, and “zcFlag0” are “0”. The process is performed to suppress a sudden change in the signal level before and after the address jump, thereby reducing the sense of discomfort in the sense of hearing. Then, the process proceeds to the next step SP42 and the process is terminated.

  Here, as shown in FIGS. 24A to 24D, when the tracks 1 to 3 are set as one group, “Jump” in the header of the audio data D1 in advance at the address ad4 corresponding to the time point t4. It is assumed that the jump address has the flag “1” set. The CPU 12 jumps to the address ad4 corresponding to the time point t4 when the audio data D1 at the address ad1 is read at the time point t1.

  At this time, as shown in FIG. 24A, the CPU 12 has zero-crossing signal levels at both the address ad1 and the address ad4 in the track 1, and the address ad1 and the address ad4 in the track 3 as shown in FIG. In both cases, since the signal level is low, the track 1 and the track 3 can maintain the continuity without substantially changing the signal level when the address jump is simply performed, so that the crossfade processing is not particularly performed.

  On the other hand, in track 2, as shown in FIG. 24B, zero crossing is performed at address ad2 and address ad3, but zero crossing is not performed at address ad1, and the level is not low. Therefore, as shown in FIG. 24C, the CPU 12 jumps from the address ad1 to the address ad4 in accordance with the other tracks in the group (that is, the track 1 and the track 3). The signal level is very different.

  At this time, the CPU 12 gradually fades out the audio data D1B in the vicinity of the address before the track jump, and gradually performs a fade process to fade in the audio data D1B in the vicinity of the address after the track jump. It is designed to reduce unnaturalness in the sense of hearing.

  For example, even when the playback speed is delayed in the video tape recorder 1, the CPU 12 performs read address jump processing for delaying the read address (ie, jumping backward) by the same processing procedure as the read address jump processing procedure RT4 described above. Has been made to do.

(4) Operation and Effect In the above configuration, the CPU 12 of the multitrack audio control apparatus 10 performs audio in the ring buffer 40 of the audio input / output unit 21 in each track in a state where a plurality of tracks are set in advance as one group. When data D1 is written at a writing speed of 48 [kHz] ± 5% and read from the ring buffer 40 at a constant reading speed of 48 [kHz], the data D1 is written according to the difference value k between the writing address and the reading address. The read address is forcibly jumped while maintaining the phase for all tracks in the preset group so that the embedded address does not overtake the read address.

  Therefore, the CPU 12 of the multi-track audio control apparatus 10 can maintain the phase between all the tracks set as a group when the address jump is performed. For example, sound image localization is performed in 2-channel stereo sound, 6-channel surround sound, or the like. The audio playback time can be changed without upsetting the audio.

  At this time, the CPU 12 of the multi-track audio control device 10 causes the audio input / output unit 21 corresponding to each track to perform address jump so as to connect the read address immediately before the zero cross and the read address immediately after the zero cross in as many tracks as possible. Since the change in signal level between the audio data D1 corresponding to the read address before the address jump and the audio data D1 corresponding to the read address after the address jump can be reduced as much as possible, the audio data is actually performed by the address jump. Even if the continuity of D1 is interrupted, the user's audibility gives the impression that the continuity of the audio data D1 is maintained and can output a sound with no change in pitch.

  Further, when the address jump is performed, the CPU 12 of the multi-track audio control device 10 cannot connect the read address immediately before the zero crossing with the read address immediately after the zero crossing, and either one or both of them is a read address whose signal level is low. Similarly, since the change in the signal level of the audio data D1 before and after the address jump can be reduced as much as possible, the impression that the continuity of the audio data D1 is maintained is perceived by the user. Can be given.

  In these cases, the CPU 12 of the multitrack audio control apparatus 10 simply causes the audio input / output unit 21 of each track to perform the address jump of the read address immediately before and immediately after the zero crossing, or at the low level address. Thus, the amount of signal processing can be significantly reduced as compared with the case of performing cross-fade processing that requires many operations such as addition and multiplication.

  Furthermore, the CPU 12 of the multi-track audio control apparatus 10 places the highest priority on maintaining the phase between the tracks. Therefore, if there is a track that causes an address jump at a read address that is not immediately before or immediately after zero crossing or at any low level, By performing the crossfade process on the track, it is possible to prevent the user from feeling uncomfortable as much as possible.

  Further, the CPU 12 of the multi-track audio control apparatus 10 skips the audio data D1 when the read address is advanced by jumping the read address by the audio input / output unit 21 corresponding to each track. In other words, when the read address is returned to the back, the same audio data D1 is read again and data interpolation is performed, so that the audio can be temporally matched with the video subjected to the variable speed playback processing.

  Further, the CPU 12 of the multitrack audio control apparatus 10 holds an initial delay having a certain range of about 1024 slots ± 100 slots as a difference between the read address and the write address in the audio input / output unit 21 corresponding to each track. By controlling, it is possible to avoid in advance the risk that the write address overtakes the read address or the read address overtakes the write address.

  According to the above configuration, when the video tape recorder 1 operates the program play function and outputs sound without changing the pitch in accordance with the video variable speed playback process, the CPU 12 of the multitrack audio control apparatus 10 previously While maintaining the phase between tracks set as a group, the signal processing amount can be greatly reduced without substantially reducing the quality of the audio data D1.

(5) Other Embodiments In the above-described embodiment, when the video tape recorder 1 performs the variable speed playback process of video data by the program play function, the multi-track audio control device 10 has a plurality of tracks in the same group. Although the case where the input / output of the audio data D1 of each track is controlled while maintaining the phase between them has been described, the present invention is not limited to this, and a plurality of tracks are used, for example, when video data editing processing is performed. May be grouped and edited while maintaining the phase between the tracks in the group.

  In the above-described embodiment, the case where the 2048-slot ring buffer 40 is used in the audio input / output unit 21 has been described. However, the present invention is not limited to this, and the 4096-slot in consideration of the audio quality. A ring buffer of 1048 slots may be used in consideration of using a ring buffer or reducing the initial delay.

  Further, in the above-described embodiment, the offset detector 35 calculates an average value by dividing the total value of the signal levels of the audio data D1 sequentially written in the 2048 slots of the ring buffer 40 by 2048, and calculates the average value. Although the case where the offset amount of the DC component is detected has been described, the present invention is not limited to this. For example, an intermediate value between the maximum value and the minimum value of the audio data D1 is detected as the offset amount of the DC component. Also good.

  Furthermore, in the above-described embodiment, the case where all tracks in the group are set immediately before or immediately after the zero crossing, or the address at which the signal level becomes the low level is set as the jump address. However, the conditions for setting the jump address may be variously changed, for example, only the address at which all the tracks in the group are immediately before or after the zero crossing is set as the jump address.

  Furthermore, in the above-described embodiment, the case has been described where it is determined whether or not the number of flag set tracks is half or more of the total number of tracks in step SP37 (FIG. 22), but the present invention is not limited to this. Instead, for example, it may be determined whether or not the number of flag set tracks is an arbitrary ratio or more with respect to the total number of tracks, such as determining whether or not the number of flag set tracks is 70% or more of the total number of tracks.

  Further, in the above-described embodiment, the case where unnecessary DC component (offset) is included in the audio data D1 in the jump address detection processing procedure RT3 (FIG. 21) and the read address jump processing procedure RT4 (FIG. 22) is particularly considered. The case where the jump address is detected and the address jump is performed based on the flag information such as “zcFlag1” and “zcFlag0” is described, but the present invention is not limited to this, and when the audio data D1 includes an offset, Based on flag information such as “offset zcFlag1” and “offset zcFlag0”, a jump address may be detected, an address jump may be performed, or these may be combined.

  Further, in the above-described embodiment, the case where the present invention is applied when the audio data D1 is written for each slot at the writing speed 48 [kHz] ± 5% has been described. However, the present invention is not limited to this. The present invention is applied when the writing speed of the audio data D1 to the ring buffer 10 is a writing speed other than 48 [kHz] ± 5% or when the writing speed fluctuates instead of being fixed. You may do it.

  Further, in the above-described embodiment, the case where the user is allowed to set a group using the group setting screen shown in FIG. 15 is described. However, the present invention is not limited to this, and for example, the group setting screen shown in FIG. It may be displayed on the touch panel 5 of the video tape recorder 1 (FIG. 1) to allow the user to set a group.

  Further, in the above-described embodiment, the case where the multi-track audio control apparatus 10 of the present invention is mounted on the video tape recorder 1 has been described, but the present invention is not limited to this, and the video editing apparatus, voice recorder, You may make it mount in other various electronic devices, such as an audio recording device, a personal computer, a hard-disk recorder, or a mobile telephone.

  Furthermore, in the above-described embodiment, the audio input / output units 21A to 21L as the audio data input / output unit, the grouping unit and the read address determining unit are used as the multitrack audio control unit 10 as the multi-track audio control unit according to the present invention. However, the present invention is not limited to this, and the present invention is not limited to this, and a plurality of audio data input / output units, grouping means, and read address determining means having various configurations are used. A track audio control device may be configured.

  The multi-track audio control apparatus and multi-track audio control method according to the present invention can be applied to, for example, the application of time expansion or time compression of multi-track audio data with high quality.

It is a basic diagram which shows the positional relationship of the write data and read data on a ring buffer. It is a basic diagram which shows a mode that read data overtakes write data. It is a basic diagram which shows a mode that write data overtakes read data. It is an approximate line figure used for explanation of crossfade processing. It is a basic diagram with which it uses for description of the cross-fade process when a write address overtakes a read address. It is a basic diagram with which it uses for description of the cross fade process when a read address overtakes a write address. It is an approximate line figure used for explanation of read address jump processing. It is a basic diagram with which it uses for description of the read address jump process using a zero cross. It is a basic diagram which shows the change of the delay amount when a writing speed is faster than a reading speed. It is an approximate line figure showing change of delay amount when reading speed is faster than writing speed. It is a basic diagram which shows the jump timing of a read address. It is a basic diagram which shows the data structure of audio data. It is a basic diagram which shows the waveform of the audio data on which the direct-current component was superimposed. It is a rough-line perspective view which shows the structure of a video tape recorder. It is a basic diagram which shows a group setting screen. It is a rough-line block diagram which shows the structure of a multitrack audio control apparatus. It is a rough-line block diagram which shows the circuit structure of an audio input / output part. It is a flowchart with which it uses for description of a low level detection process procedure. It is a flowchart with which it uses for description of a zero cross detection process sequence. It is a basic diagram which shows the structure of an offset detector. It is a flowchart with which it uses for description of a jump address detection processing procedure. It is a flowchart which shows the read address jump processing procedure. It is a basic diagram which shows an address jump image. It is a basic diagram with which it uses for description of the address jump in the same group. It is a basic diagram with which it uses for description of the group setting screen by other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Video tape recorder, 5 ... Touch panel, 10 ... Multitrack audio control apparatus, 11 ... Multitrack control part, 12 ... CPU, 20A-20L ... Audio control part, 21A-21L ... Audio input Output unit, 22A to 22L ... cross fade buffer, 23A to 23L ... cross fade circuit, 32 ... low level detector, 33 ... zero cross detector, 34 ... input / output control unit, 40, 40A to 40L ... ... ring buffer.

Claims (16)

A multi-track audio control apparatus having audio data input / output units corresponding to one track of audio data for a plurality of tracks,
An audio data input / output unit having a memory for storing the audio data input from the outside, and a read address changing unit for forcibly changing a read address when reading the audio data from the memory;
Grouping means for grouping a plurality of tracks specified in advance,
In a track corresponding to a number equal to or greater than a predetermined ratio in the group, the signal level of the audio data corresponding to the read address before the change by the read address changing means and the signal of the audio data corresponding to the read address after the change A plurality of tracks, comprising: a read address determining means for aligning a phase by determining an address position having a small signal level change with respect to a level as a read address after the change in all tracks in the group Audio control device. The audio data input / output unit
Crossfade processing means for performing crossfade processing on the audio data;
The read address determining means includes:
When the read address changing means of the audio data input / output unit is forcibly changed, the audio of a track having a large amount of change in the signal level of the audio data among the plurality of the grouped tracks. The multi-track audio control apparatus according to claim 1, wherein the cross-fade processing is executed on a data input / output unit. The read address determining means includes:
In a track having a predetermined ratio or more in the group, the signal level of the audio data corresponding to the read address before the change by the read address changing unit and the signal level of the audio data corresponding to the read address after the change are either 2. The multi-track audio control apparatus according to claim 1, wherein an address position that is equal to or less than a predetermined threshold value is determined as the read address before the change and the read address after the change in all tracks in the group. The read address determining means includes:
In a track having a predetermined ratio or more in the group, the signal level of the audio data corresponding to the read address before the change by the read address changing means is immediately before or immediately after the zero crossing, and the audio data corresponding to the read address after the change is recorded. 2. The multi-track audio control apparatus according to claim 1, wherein an address position immediately after or immediately before the zero crossing is determined as the read address after the change in all tracks in the group. The read address determining means includes:
Instructing the read address changing means of the audio data input / output unit to change the read address according to the difference between the write address for writing the audio data in the memory and the read address in the audio data input / output unit. The multi-track audio control apparatus according to claim 1. The read address determining means includes:
The read address changing means of the audio data input / output unit is forced to change the read address before the write address or the read address catches up with the read address or the write address. The multi-track audio control apparatus according to claim 5. The read address determining means includes:
The read address changing means of the audio data input / output unit does not change the read address when the difference exceeds a predetermined value, and forcibly changes the read address when the difference is less than the predetermined value. The multi-track audio control apparatus according to claim 5, wherein: The read address determining means includes:
2. The multiple tracks according to claim 1, wherein when it is detected that an unnecessary DC component is superimposed on the audio data, the read address after the change is determined in a state where the DC component is removed. Audio control device. A plurality of audio data input / output units having a read address changing means for forcibly changing a read address when reading the audio data from a memory for storing audio data of one track input from the outside are controlled for a plurality of tracks. A track audio control method,
A grouping step of grouping a plurality of predesignated tracks into one group;
In a track corresponding to a number equal to or greater than a predetermined ratio in the group, the signal level of the audio data corresponding to the read address before the change by the read address changing means and the signal of the audio data corresponding to the read address after the change A read address determining step for aligning phases by determining an address position having a small signal level change with respect to a level as a read address after the change in all tracks in the group. Audio control method. The audio data input / output unit
Crossfade processing means for performing crossfade processing on the audio data;
The read address determination step includes
When the read address changing means of the audio data input / output unit is forcibly changed, the audio of a track having a large amount of change in the signal level of the audio data among the plurality of the grouped tracks. The multi-track audio control method according to claim 9, wherein the cross-fade processing is executed on a data input / output unit. The read address determination step includes
In a track having a predetermined ratio or more in the group, the signal level of the audio data corresponding to the read address before the change by the read address changing unit and the signal level of the audio data corresponding to the read address after the change are either 10. The multi-track audio control method according to claim 9, wherein an address position that is equal to or less than a predetermined threshold is determined as the read address before the change and the read address after the change in all tracks in the group. The read address determination step includes
In a track having a predetermined ratio or more in the group, the signal level of the audio data corresponding to the read address before the change by the read address changing means is immediately before or immediately after the zero crossing, and the audio data corresponding to the read address after the change is recorded. The multi-track audio control method according to claim 9, wherein an address position whose signal level is immediately after or immediately before the zero crossing is determined as the read address after the change in all tracks in the group. The read address determination step includes
Instructing the read address changing means of the audio data input / output unit to change the read address according to the difference between the write address for writing the audio data in the memory and the read address in the audio data input / output unit. The multi-track audio control method according to claim 9. The read address determination step includes
The read address changing means of the audio data input / output unit is forced to change the read address before the write address or the read address catches up with the read address or the write address. The multi-track audio control method according to claim 13. The read address determination step includes
The read address changing means of the audio data input / output unit does not change the read address when the difference exceeds a predetermined value, and forcibly changes the read address when the difference is less than the predetermined value. The multi-track audio control method according to claim 13, wherein: The read address determination step includes
10. The multiple tracks according to claim 9, wherein when it is detected that an unnecessary DC component is superimposed on the audio data, the changed read address is determined in a state where the DC component is removed. Audio control method.

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