JP4248804B2 - Semiconductor wafer and method for manufacturing semiconductor wafer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor wafer and a manufacturing method thereof, and more particularly to a semiconductor wafer having an epitaxial layer and a manufacturing method thereof.
[0002]
[Prior art]
FIG. 14 is a flowchart showing a conventional process for manufacturing a general mirror surface wafer. Based on the same figure, the outline of the general manufacturing method of the mirror surface wafer used as a raw material wafer for producing a semiconductor device is demonstrated.
[0003]
First, a semiconductor ingot is grown by the Czochralski method (CZ method), the floating zone melting method (FZ method), or the like (STEP 101). Since the grown single crystal ingot has a distorted outer peripheral shape, the outer periphery of the semiconductor ingot is then ground with a cylindrical grinder or the like in the external grinding step (STEP 102) to prepare the outer peripheral shape of the semiconductor ingot. This is sliced with a wire saw or the like in the slicing step (STEP 103) and processed into a disk-shaped wafer having a thickness of about 500 to 1000 μm, and further, the chamfering process is performed on the outer periphery of the wafer in the chamfering step (STEP 104).
[0004]
Thereafter, planarization is performed by surface grinding and / or lapping (hereinafter referred to as “surface grinding / lapping”) (STEP 105), and chemical polishing is performed in the etching process (STEP 106). Further, the wafer surface is subjected to primary polishing (STEP 107) and secondary polishing (STEP 108), and then an epitaxial growth process (STEP 109) is performed on the wafer surface to obtain a mirror wafer.
[0005]
When manufacturing a semiconductor device by forming a circuit on the surface of a mirror-finished wafer obtained through such a process, it is desirable to obtain as many devices as possible from one wafer. It is required to have a flat shape as close as possible to the part. In other words, in recent high-precision device fabrication, extremely high flatness is required, and for example, a portion that is about 0.1 to 0.2 μm lower than the central portion of the wafer cannot be used. It is desirable to minimize the area. For example, it is desired that the peripheral sag region that is out of the standard is 3 mm from the outer peripheral edge in the normal standard, in recent years 2 mm, preferably within 1 mm.
[0006]
However, in the surface grinding / lapping process (STEP 105), it is difficult to maintain the uniformity of the grinding pressure on the entire surface of the wafer due to the influence of orientation flats and notches formed on the wafer. There is. In general, when the primary polishing step (STEP 107) is performed, the wafer is attached to a glass or ceramic carrier plate (mount plate) via wax or the like, or the wafer is attached to a holding plate provided with a large number of through holes. Is held by vacuum suction, pressed while rotating the wafer relative to the surface plate on which the polishing cloth is stuck, and polishing is performed by supplying a slurry between the polishing cloth and the wafer. At this time, the peripheral portion of the wafer is excessively polished compared to the central portion, and so-called peripheral sag occurs in the peripheral portion near the chamfered portion on the polishing surface side.
[0007]
This peripheral sag occurs in an area of about 5 mm from the outer peripheral edge of the wafer regardless of the product diameter, and the thickness of the wafer is 0.1 to 0. In many cases, the thickness is about 2 μm. Such a peripheral sag deteriorates rapidly as it approaches the outer peripheral end, particularly worse from about 2 mm from the outer peripheral end, and particularly drops rapidly from about 1 mm.
[0008]
In order to solve the above-mentioned problems, Japanese Patent Laid-Open No. 2001-338899 discloses that the wafer is subjected to the first polishing step (STEP 107) in a state where the diameter of the wafer is 1 mm or more larger than the product diameter. The reduced diameter chamfering is performed before the step (STEP 108). In this way, the peripheral polishing generated in the primary polishing process is removed by performing the process up to the primary polishing process in a state where the diameter of the wafer is excessively large and removing the excessively formed area by the chamfering of the diameter. Can do. Then, by performing secondary polishing (mirror polishing), a mirror surface wafer with less peripheral sagging is manufactured.
[0009]
[Problems to be solved by the invention]
In the manufacture of a normal mirror wafer, as shown in FIG. 14, after the secondary polishing step (STEP 108), an epitaxial growth process (STEP 109) is performed on the polished surface of the wafer. In this epitaxial growth process, one or a plurality of mirror-polished wafers are placed in a high-temperature chamber and trichlorosilane gas (SiHCl) is placed. ₃ ) Or the like is supplied to grow an epitaxial layer made of single crystal silicon having a uniform thickness on the mirror polished surface of the wafer.
[0010]
FIG. 13A is a film thickness distribution diagram when an epitaxial layer is grown on a mirror-polished wafer by a conventional manufacturing method. The horizontal axis represents the displacement in the diameter direction of the wafer, and the vertical axis represents the film thickness of the epitaxial layer. As is clear from FIG. 13A, the epitaxial layer becomes thinner than the normal film thickness in the vicinity of the outer peripheral portion of the wafer (outer peripheral end to 2 mm), and the outer peripheral sagging of the epitaxial layer is observed. The thin film portion of the epitaxial layer in the vicinity of the outer peripheral portion of the wafer has a lower resistivity than a normal film thickness portion and does not satisfy a desired resistivity required for a semiconductor chip. Therefore, it cannot be used as a semiconductor chip, and the outer peripheral edge of about 2 mm is discarded at the manufacturing stage of the semiconductor chip. In particular, the larger the wafer diameter is 200 mm or more, the more silicon waste is wasted.
[0011]
Further, at the outer peripheral edge of the wafer, crystals may grow abnormally at the wafer edge during epitaxial growth due to variation in the chamfered shape, and a protruding crown may be recognized. Since the wafer having the crown damages the mask in the circuit pattern alignment process, not only the efficiency of the semiconductor device is deteriorated but also the quality reliability is adversely affected.
[0012]
The thinning of the epitaxial layer in the vicinity of the outer peripheral portion and the generation of a crown at the outer peripheral end are important problems that must be solved together with higher wafer flatness in the recent wafer industry where high quality is required.
[0013]
However, the technique described in the above-mentioned Japanese Patent Application Laid-Open No. 2001-338899 cannot solve the above-described problem caused by epitaxial growth after secondary polishing (mirror polishing).
[0014]
In this regard, JP-A-1-201922 discloses that the wafer edge is chamfered after the epitaxial growth step in order to remove the crown. However, it has been difficult to effectively prevent thinning of the epitaxial layer in the vicinity of the outer peripheral portion of the wafer only by chamfering the outer peripheral end portion.
[0015]
The invention according to the present application has been made in order to solve the above-described problems. The first object of the invention is that the area of the peripheral sag of the wafer thickness is very small, or the peripheral sag is small. It is an object of the present invention to provide a semiconductor wafer that is completely absent and a method for manufacturing the same.
[0016]
The second object of the invention according to the present application is to provide a semiconductor wafer having a highly uniform epitaxial layer that prevents thinning of the epitaxial layer (peripheral sagging) in the vicinity of the outer periphery of the wafer and a method for manufacturing the same. It is to provide.
[0017]
A third object of the invention according to the present application is to provide a method for manufacturing a semiconductor wafer that greatly streamlines the manufacturing process at the time of manufacturing the semiconductor wafer and improves productivity, and does not waste silicon that is a raw material of the semiconductor wafer. It is to provide.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, according to a first aspect of the present invention, in a method of manufacturing a semiconductor wafer by performing epitaxial growth processing on a wafer, the diameter of the wafer during the epitaxial growth processing is larger than a product diameter, A method of manufacturing a semiconductor wafer, comprising removing a peripheral portion of the wafer to the product diameter after the epitaxial growth process.
[0019]
The second invention according to the present application is the method for manufacturing a semiconductor wafer according to the first invention, characterized in that the means for removing the peripheral portion of the wafer is chamfering with a reduced diameter.
[0020]
Further, according to a third invention of the present application, the means for removing the peripheral portion of the wafer is a laser cutting or a laser fusing, and the semiconductor wafer manufacturing method according to the first invention is characterized in that It is.
[0021]
According to a fourth aspect of the present invention, the laser is a YAG laser, CO ₂ The method for producing a semiconductor wafer according to the third aspect, wherein the semiconductor wafer is any one selected from a laser, an excimer laser, a ruby laser, and a sapphire laser.
[0022]
Furthermore, a fifth invention according to the present application is the method for producing a semiconductor wafer according to the third invention, wherein the wavelength of the laser is 152 nm to 10.6 μm.
[0023]
According to a sixth aspect of the present invention, in any one of the third to fifth aspects of the invention, the peripheral portion of the wafer is removed by a laser, and then the outer periphery of the wafer is chamfered. It is a manufacturing method of the semiconductor wafer as described in above.
[0024]
Furthermore, a seventh invention according to the present application is the semiconductor according to any one of the first to sixth inventions, wherein the diameter of the wafer at the time of the epitaxial growth process is 1 mm or more larger than the product diameter. A wafer manufacturing method.
[0025]
In addition, according to an eighth aspect of the present invention, in any one of the first to sixth aspects, the diameter of the wafer during the epitaxial growth process is 1 to 9 mm larger than the product diameter. It is a manufacturing method of a semiconductor wafer.
[0026]
Further, according to a ninth aspect of the present invention, in any one of the first to sixth aspects, the diameter of the wafer during the epitaxial growth process is 2 to 5 mm larger than the product diameter. It is a manufacturing method of a semiconductor wafer.
[0027]
According to a tenth aspect of the present invention, after the epitaxial growth process, before removing the peripheral portion of the wafer, at least the surface of the wafer on which the epitaxial layer is formed is coated with a protective film, The method for manufacturing a semiconductor wafer according to any one of the first to ninth inventions, wherein the protective film is removed after the peripheral portion is removed.
[0028]
Furthermore, an eleventh invention according to the present application includes a step of growing a single crystal ingot, a step of grinding an outer shape, a step of slicing, a step of performing a planarization process on the sliced wafer, And a step of growing the epitaxial layer, wherein the diameter of the wafer up to the step of growing the epitaxial layer is larger than a desired product diameter, and the epitaxial layer is grown. A method for manufacturing a semiconductor wafer comprising a step of removing a peripheral portion of the wafer to the desired product diameter later.
[0029]
Further, the twelfth aspect of the present invention is formed by performing epitaxial growth processing on a wafer having a diameter larger than the product diameter, and removing the peripheral portion of the wafer to the product diameter after the epitaxial growth processing. It is a semiconductor wafer.
[0030]
Furthermore, in a thirteenth aspect of the present invention, an epitaxial growth process is performed on a wafer having a diameter larger than the product diameter, and after the epitaxial growth process, at least the surface of the wafer on which the epitaxial layer is formed is coated with a protective film. The semiconductor wafer coated with the protective film is formed by removing the peripheral portion of the wafer up to the product diameter.
[0031]
A fourteenth aspect of the present invention is a semiconductor wafer in which an epitaxial layer is formed on at least one surface of the wafer, and the epitaxial layer is coated with a protective film on the epitaxial layer.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a method for manufacturing a semiconductor wafer according to the present application will be described in detail with reference to the drawings.
[0033]
[Embodiment 1]
First, a first embodiment will be described with reference to FIGS. FIG. 1 is a flowchart showing an outline of a semiconductor wafer manufacturing method according to the first embodiment. The process shown in the flow is a simplified illustration of the process for manufacturing a semiconductor wafer. As described below, the manufacturing method of the present application is required to have the epitaxial growth step (STEP 7) and the reduced diameter chamfering step (STEP 8) in the order of the flow shown in FIG. As for the number of, various modes are conceivable depending on the specifications of the wafer and each manufacturer.
[0034]
[STEP1]
First, as shown in FIG. 1, a single crystal ingot is first grown by the Czochralski method (CZ method), the floating zone melting method (FZ method), or the like (STEP 1).
[0035]
For example, in the floating zone melting method (FZ method), rod-shaped polycrystalline silicon is melted in a strip with a coil to which a high-frequency voltage is applied in argon gas, a small seed crystal is brought into contact with the melted portion, and then the coil is moved up and down. To move the entire rod to a single crystal.
[0036]
A single crystal ingot can be produced in the same manner by using any of the above floating zone melting method (FZ method) or chocturky method (CZ method). A case where a wafer having a diameter of 200 mm is manufactured using the Czochralski method (CZ method) will be specifically described. FIG. 2 is a longitudinal sectional view schematically showing a single crystal ingot manufacturing apparatus using the CZ method.
[0037]
Reference numeral 22 in FIG. 2 denotes a quartz crucible, which is installed on the crucible support shaft 22a. The crucible 22 is disposed in a chamber 29, and a heater 23 is disposed on the outer periphery of the crucible 22 to surround the crucible 22 and heat the melt 24 in the crucible 22. On the other hand, above the crucible 22, a pulling wire 25 is suspended from the center of the upper portion of the chamber 29 so as to be rotatable and liftable, and a seed crystal 26 is attached to the lower end thereof. The seed crystal 26 rises while being rotated by the pulling wire 25, and a single crystal 27 grows at the lower end that is the contact surface with the melt 24. A supply port 21 is provided in the upper portion of the chamber 29, and high-purity argon gas (see arrow) is constantly supplied from the supply port 21 in order to adjust the atmosphere in the chamber 29 and discharge the evaporated material. In addition, a discharge port is provided in the lower part of the chamber 29, and a vacuum pump 28 is connected to discharge the processed argon gas.
[0038]
First, high-purity polycrystalline silicon is roughly crushed and washed, and then placed in a crucible 22 and heated by a heater 23. At the same time, a necessary amount of a small amount of conductive impurities (additive or dopant) is added. Boron (B) is added to obtain a P-type crystal, and phosphorus (P) and antimony (Sb) are added to form an N-type crystal, and the resistivity of the crystal is controlled by the amount of impurities added.
[0039]
A seed crystal 26 attached to the lower end of a pulling wire 25 made by twisting a piano wire is brought into contact with the silicon melt 24, and the seed crystal 26 is pulled upward while rotating. Although not shown, in order to prevent crystal dislocation, necking is performed after the diameter of the single crystal 27 is enlarged / reduced, and then the diameter of the single crystal 27 is gradually increased to perform shoulder expansion 27a. By adjusting the temperature of the melt 24 and the pulling speed, the single crystal 27 having a crystal diameter and various characteristics can be grown. In particular, when manufacturing a large-diameter wafer, the MCZ method in which a magnetic field is applied to the crucible 22 to reduce the convection of the melt 24 is employed. In the present embodiment, when the diameter 27b of the single crystal 27 reaches 212 mm, the single crystal 27 is pulled up so as to maintain a straight cylindrical shape.
[0040]
During the pulling of the single crystal 27, high purity argon gas is supplied into the chamber 29 from the supply port 21, and the oxygen concentration in the single crystal 27 is controlled within a certain range. At this time, at a depth of about 1 to 3 mm from the outer periphery of the pulled single crystal 27, the oxygen concentration is unstable and crystal defects are likely to concentrate. Therefore, the diameter of the single crystal 27 to be grown is set larger than the actual product diameter of the wafer so that the outer peripheral portion of the single crystal can be removed in a later process. The pulled single crystal 27 is transferred to the next step as a single crystal ingot.
[0041]
[STEP2]
Once the single crystal ingot is grown, the external grinding step (STEP 2) is performed. A single crystal ingot of silicon grown by a floating zone melting method (FZ method) or a chocturkey method (CZ method) has a length of 1.3 m and a weight of about 115 kg. Unnecessary portions of the single crystal ingot, that is, the upper end portion (top portion) and the lower end portion (tail portion) are cut and removed, and the cylindrical portion is cut and separated into several single crystal blocks. Since the shape of the single crystal ingot grown in STEP 1 is not a straight cylindrical shape, but the outer periphery is wavy, it is necessary to grind the outer periphery of the cut single crystal block into a straight cylindrical shape.
[0042]
FIG. 3 is a plan view schematically showing an example of a cylindrical grinder generally used for external grinding. The cylindrical grinding machine includes a work table 33 that is movable in the left-right direction on the main body 30. A work rotation motor 34 is fixed on the work table 33, and a single crystal block 43 is mounted on a rotation shaft 34 a of the work rotation motor 34. A table feed motor 35 is fixed to the main body 30, and the work table 33 moves in the left-right direction on the main body 30 by the rotation of the table feed motor 35.
[0043]
On the main body 30, a grindstone table 39 that is movable in the vertical direction is further provided. On the grindstone table 39, a grindstone rotating motor 37 and a rotating grindstone 31 are provided. The grinding wheel rotating motor 37 and the rotating grinding wheel 31 are wound around the pulleys 38 a and 38 b, and the belt 38 c is wound around. The rotational driving of the grinding wheel rotating motor 37 is transmitted to the rotating grinding wheel 31. A grindstone feed motor 36 is fixed to the main body 30, and the grindstone table 39 moves up and down on the main body 30 by the rotation of the grindstone feed motor 36.
[0044]
In the cylindrical grinding machine, by driving the workpiece rotating motor 34 and the grindstone rotating motor 37, the rotating grindstone 31 and the single crystal block 43 are brought into contact with each other in a rotated state. Then, the outer periphery of the single crystal block 43 is ground by moving the work table 33 in the left-right direction. In the above configuration, the grinding tool is not limited to the rotating grindstone 31, and a cutting tool can be used instead of the rotating grindstone 31.
[0045]
In the external grinding process (STEP 2), the rotational speed of the grinding wheel feed motor 36 is controlled so that the grinding allowance is about 4 mm, the outer diameter of the single crystal block 43 is ground by about 8 mm, and a straight cylindrical shape having a diameter of 204 mm. To process. In anticipation of this grinding allowance, a single crystal 27 having a larger diameter is grown in STEP 1. The grinding allowance may be a fixed amount of about 4 mm regardless of the diameter of the single crystal ingot if the purpose is to shape the outer shape.
[0046]
Further, the cylindrical single crystal block 43 after the external grinding of STEP 2 is the final product so that the defects on the outer peripheral portion of the wafer in the subsequent mirror polishing step (STEP 6) and the epitaxial growth step (STEP 7) can be removed. The diameter of the single crystal ingot is controlled to grow so as to be at least about 2 mm larger than the diameter.
[0047]
When the outer periphery of the single crystal block 43 is ground, an orientation flat (orientation flat) or notch is formed in the longitudinal direction of the single crystal block 43. The orientation flat is a linear notch provided in a part of the outer periphery of the wafer, and the notch is a substantially 90 ° V-shaped notch provided in a part of the outer periphery of the wafer toward the center. . Orientation flats and notches are notches that show the crystal orientation of silicon in semiconductor wafers. By forming them at the single crystal block stage, orientation flats or notches are formed on all wafers when cut into wafers. Batch formation.
[0048]
[STEP3]
Subsequently, the externally ground single crystal block 43 moves to a slicing step (STEP 3). In the slicing process, a blade saw or a wire saw is generally used. FIG. 4 schematically shows an example of a blade saw. The blade saw includes an inner peripheral blade 41 that maintains a plate shape by pulling the periphery of a thin disc-shaped stainless high hardness steel, a support base 42 that bonds the single crystal block 43 cut in STEP 2, and a movement (not shown). Means.
[0049]
First, an adhesive is applied to one side surface of the single crystal block 43 and bonded and fixed to the upper surface of the support base 42. Next, in a state where the inner peripheral blade 41 is rotated in the circumferential direction, the single crystal block 43 is disposed in the inner peripheral blade 41, and the inner peripheral blade 41 is lowered toward the single crystal block 43. After cutting out one wafer 44 from the single crystal block 43, the inner peripheral blade 41 is raised, and after moving the single crystal block 43 in the axial direction (left arrow in the figure) by a predetermined pitch by a moving means (not shown), The inner peripheral blade 41 is lowered again. After repeating the above procedure and slicing the single crystal block 43 into a plurality of wafers 44, the adhesive is dissolved with a chemical solution, and the wafers 44 are peeled off from the support base 42 and separated into single wafers.
[0050]
Since the inner peripheral edge 41 of the blade saw has a thickness of about 0.4 mm and diamond abrasive grains of about 0.1 mm are deposited on the inner periphery, the cutting allowance for each slice of one wafer is about 0. About 6 mm. The thickness of the wafer 44 to be sliced can be controlled by the feed pitch of the single crystal block 43. The time for cutting out one wafer from the single crystal block 43 having a diameter of about 200 mm is about 6 minutes. However, due to difficulties in preparing a wide blade material, it is becoming common to use a wire saw described below for future large-diameter wafers (diameter 300 mm or more).
[0051]
Next, the case where a wire saw is used as means for slicing the single crystal block 43 will be described. FIG. 5 is a perspective view schematically showing an example of a wire saw. The wire saw includes three rollers 55 to 57 that are rotatable between the left and right brackets 51a and 51b (51b shows only a part of the two-dot chain line). In the wire saw shown in the figure, an example in which three rollers 55 to 57 are provided is shown. However, the number of rollers may be two or four or more. The wire 58 is spirally wound around the rollers 55 to 57 at a predetermined pitch, and the wire 58 reciprocates in the linear direction while rotating the rollers 55 to 57 reciprocally. The main body 50 is provided with a work support head 53 to which a single crystal block 43 after external grinding is bonded, so that the work support head 53 can be moved in the vertical direction. Move.
[0052]
A processing liquid containing abrasive grains is supplied in a state in which the wire 58 is reciprocated, and the single crystal block 43 is pressed against the wire 58, so that the single crystal block 43 has a plurality of disks according to the winding pitch of the wire 58. Is cut into wafers. Usually, the single crystal block 43 is cut into a thickness of about 800 to 900 μm. Since the wire saw is sliced by supplying a machining liquid containing abrasive grains of about 0.1 mm to a piano wire having a diameter of less than 0.2 mm, the cutting allowance is about 0.3 mm, which is less than the blade saw. In addition, since a plurality of wafers can be batch-sliced at once, it has an advantage that it can be sliced in a shorter time than a blade saw. Further, even when a large-diameter wafer is cut out, it is less likely to be mechanically restricted. Therefore, it is desirable to use a wire saw particularly when slicing a large-diameter wafer (diameter 300 mm or more).
[0053]
[STEP4]
When the single crystal block 43 is sliced into a wafer shape, the outer periphery of the wafer 44 is generally rough chamfered. However, in this application, rough chamfering at this stage is not an essential process. Accordingly, in this embodiment, the process proceeds to the next surface grinding / lapping step (STEP 4) without performing rough chamfering, but the rough chamfering step is performed between the slicing step (STEP 3) and the surface grinding / lapping step (STEP 4). May be performed.
[0054]
The wafer 44 cut by the blade saw or the wire saw in the slicing step (STEP 3) has a poor flatness and a rough surface, so that it is ground and lapped flatly in the surface grinding / lapping step (STEP 4). The surface grinding / lapping step (STEP 4) may be only surface grinding or only lapping. Alternatively, both surface grinding and lapping may be performed.
[0055]
Surface grinding uses a single-head grinding machine that grinds flatly with a grindstone that fixes one surface of the wafer to the chuck and rotates the other surface, or a double-head grinder that sandwiches and grinds the upper and lower surfaces of the wafer with opposite grinding wheels. Do. In order to cope with the fine pattern of the IC, it is desirable to grind both sides of the wafer with a double-head grinding machine. The double-headed grinding machine includes a horizontal double-headed grinding machine that grinds with a rotating grindstone from the left and right while holding the wafer vertically, and a vertical double-headed grinder that grinds with a rotating grindstone from above and below while holding the wafer horizontally. Here, a vertical double-head grinding machine will be described with reference to the drawings as an example of a grinding machine.
[0056]
FIG. 6 is a front view of a vertical double-head grinding machine. This double-head grinding machine has two grinding surfaces 67a and 68a, which are end faces of a pair of grindstones 67 and 68, and the grinding surfaces 67a and 68a are opposed to each other in a substantially parallel state. The upper grindstone 68 is rotated by the grindstone rotating mechanism 66, and the lower grindstone 67 is rotated by the grindstone rotating mechanism 64. The grindstone rotating mechanism 66 is supported by the frame 63 so as to be movable up and down, and moves in the vertical direction by the rotation of the servo motor 69. The grindstone rotating mechanism 64 is supported by the frame 61 so as to be movable up and down, and moves in the vertical direction by the rotation of the servo motor 60. The wafer 44 is held horizontally by the work support mechanism 65.
[0057]
The thin plate-like wafer 44 sliced in the slicing step (STEP 3) is placed between the upper and lower grindstones 67 and 68 while being supported by the work support mechanism 65, and the upper and lower grindstones 67 and 68 are moved by the grindstone rotating mechanisms 64 and 66. Rotate them counterclockwise. By rotating the servo motors 60 and 69, both the grindstones or one of the grindstones are fed and moved toward the wafer 44, and both surfaces of the wafer 44 contacting the two grinding surfaces 67a and 68a are ground simultaneously. Since the orientation flat or notch is formed in the wafer 44, the wafer 44 can be forcibly rotated using the notch.
[0058]
In rough grinding, the counts of the upper and lower grindstones 67 and 68 are set to 300 to 800, preferably 600 to 700. The peripheral speed of the upper and lower grindstones 67, 68 is set to 800 to 3000 m / min, preferably 1000 to 1500 m / min. Further, the moving amount of the upper grindstone 68 with respect to the wafer 44 is set to 50 to 200 μm / min, preferably 50 to 100 μm / min. The rotation speed of the wafer is set to 5 to 30 rpm, preferably 10 to 25 rpm. In finish grinding, the counts of the upper and lower grindstones 67 and 68 are set to 1500 to 3000, and preferably 1800 to 2200. The peripheral speed of the upper and lower grindstones 67, 68 is set to 800 to 3000 m / min, preferably 1000 to 1500 m / min. Further, the feed movement amount of the upper grindstone 68 with respect to the wafer 44 is set to 3 to 20 μm / min, preferably 10 to 15 μm / min. Further, the rotation speed of the wafer is set to 1 to 10 rpm, preferably 2 to 5 rpm.
[0059]
By wobbling the upper and lower surfaces of the wafer 44 sliced in the slicing step (STEP 3) with a double-head grinding machine, the waviness of the wafer can be removed. However, in order to further improve the flatness of the wafer plate surface, it is desirable to wrap the upper and lower surfaces of the wafer with a lapping machine.
[0060]
FIG. 7 schematically shows an example of a lapping machine. FIG. 7A is a plan view showing a state in which the wafer is accommodated in the carrier, and FIG. 7B is a side view. As shown in FIG. 7B, the lapping machine holds an upper surface plate 71 and a lower surface plate 72 in parallel, and a carrier 73 is disposed therebetween. The carrier 73 has a substantially disc shape, and has a plurality of receiving holes 74 for receiving the wafers 44 on the plate surface. An outer peripheral gear 75 is provided on the outer periphery of the carrier 73 and meshes with an inner peripheral gear 76 provided on the lower surface plate 72. A drive gear 77 is disposed at the center of the lower surface plate 72 and meshes with the outer peripheral gear 75 of the carrier 73.
[0061]
The drive gear 77 can rotate independently of the lower surface plate 72. When the drive gear 77 is rotated, the carrier 73 is rotationally driven by the inner peripheral gear 76 and the drive gear 77, and the carrier 73 rotates. Unlike the grinding machine, the lapping machine does not include abrasive grains in the upper surface plate 71 and the lower surface plate 72, and therefore supplies a processing liquid in which abrasive particles are mixed. The wafer 44 and the upper and lower surface plates 71 and 72 slide relative to each other, and the abrasive grains scrape off from the wafer surface little by little by performing a rolling motion and a sliding motion. In the above wrapping machine, an example in which the upper surface plate 71 and the lower surface plate 72 do not rotate has been described. However, the upper surface plate 71 and the lower surface plate 72 may be rotated in the same direction or in the opposite direction. In the lapping process, wet lapping is generally performed during roughing and dry lapping is performed during finishing.
[0062]
The flatness of the wafer is processed to an extremely high state by the surface grinding / lapping step (STEP 4). At this time, the diameter of the wafer is 204 mm processed by the external grinding process (STEP 2).
[0063]
[STEP5]
After the surface grinding / lapping step (STEP 4), the process proceeds to the next etching step (STEP 5). In the silicon wafer, a processing strain layer is generated by the slicing step (STEP 3) and the surface grinding / lapping step (STEP 4), and the depth of the processing strain generated by the slicing step (STEP 3) is 25 to 50 μm. In the grinding / lapping process (STEP 4), the thickness is 10 to 15 μm. Dirts and impurities such as polishing powder and silicon scrap remain in the processing strain layer. The presence of such a strained layer has adverse effects such as deterioration of device electrical characteristics and malfunction, and also adverse effects such as contamination in the silicon wafer manufacturing process.
[0064]
An etching process (STEP 5) is provided as a subsequent process of the surface grinding / lapping process (STEP 4), mainly for the purpose of removing such processing strain layers and impurities. The etching process is performed by surface treatment (etching) of the wafer by a chemical corrosion method. For wafer etching, HF (reducing agent), HNO ₃ (Oxidizing agent), CH ₃ It is preferable to use a mixed acid of COOH (relaxation agent).
[0065]
In this etching step (STEP 5), the wafer is corroded by the etching solution from the outer peripheral side toward the center, and the diameter of the wafer is reduced to about 203.9 mm.
[0066]
[STEP6]
Thereafter, a mirror polishing step (STEP 6) is performed by a polishing disk. FIG. 8 is a longitudinal sectional view schematically showing an example of a polishing machine. In the polishing disk, a surface plate 81 is horizontally fixed on an upper part of a rotating shaft 84 arranged vertically, and the surface plate 81 includes a polishing cloth 85. A polishing head 83 mounted on a rotating shaft 86 is provided on the surface plate 81. The polishing head 83 has a suction tube 87 and vacuum-sucks the wafer 44 on the lower surface. In addition, a slurry nozzle 82 is provided toward the contact portion between the polishing head 83 and the polishing cloth 85 to supply the slurry 88.
[0067]
In the mirror polishing, one surface of the wafer 44 is sucked and fixed to the polishing head 83, and while the slurry 88 is supplied, the other surface is pressed against the polishing cloth 85 for polishing. This mirror polishing step (STEP 6) can not only flatten the wafer surface, but also remove minute irregularities on the surface.
[0068]
As described above, in the surface grinding / lapping process (STEP 4), it is difficult to maintain the uniformity of the grinding pressure on the entire surface of the wafer due to the influence of orientation flats and notches formed on the wafer. May be. Further, in the mirror polishing step (STEP 6), since the wafer is polished while being compressed into the polishing cloth due to the compression elasticity of the polishing cloth, the polishing pressure in the peripheral portion due to the pressure elasticity of the polishing cloth is high. Excessive polishing occurs at the outer periphery of the substrate, causing peripheral sagging.
[0069]
In order to solve the above problems all at once, the present embodiment is characterized in that a reduced diameter chamfering step (STEP 8) is performed after the next epitaxial growth step (STEP 7). However, this does not prevent the diameter reduction chamfering from being performed before the epitaxial growth step (STEP 7).
[0070]
[STEP7]
By growing a silicon crystal layer on the surface of the wafer after the mirror polishing step (STEP 6), a silicon wafer having no crystal defects and having a desired resistivity is manufactured. This silicon crystal layer is an extremely thin layer having a thickness of about 2 to 10 μm in the case of a wafer having a diameter of about 200 mm and a thickness of about 0.75 mm, and is generally called an epitaxial layer. .
[0071]
As an apparatus for growing an epitaxial layer, there are a single-wafer type for processing wafers one by one and a batch type for processing a plurality of wafers at once. Since the single wafer type is becoming mainstream as the diameter of the wafer increases, in this embodiment, a single wafer type epitaxial manufacturing apparatus will be described in detail, but this does not exclude batch type epitaxial growth.
[0072]
FIG. 9 is a longitudinal sectional view showing a part of a single wafer type epitaxial manufacturing apparatus as an example of the epitaxial manufacturing apparatus. In the chamber 92, a base ring (not shown) is sandwiched from above and below by translucent windows 92a and 92b made of quartz, and the internal closed space serves as a reaction furnace 97. Furthermore, heat sources 98 a and 98 b such as halogen lamps for heating the reaction furnace 97 are provided above and below the chamber 92. Openings are formed on the left and right sides of the chamber 92. The reaction gas and the carrier gas flow from one inflow port 91a, and the reacted gas and the carrier gas are discharged from the other discharge port 91b.
[0073]
In the reaction furnace 97, a susceptor 94 for supporting the wafer 44 at the upper portion is accommodated. The susceptor 94 has a disk shape when viewed from above, and has a diameter larger than that of the wafer 44. On the upper surface of the susceptor 94, a circular wafer storage recess 94a in which the wafer 44 is stored is provided. In this example, the susceptor 94 is a carbon C base material coated with a silicon carbide SiC film. When the wafer 44 is heated, the susceptor 94 serves as a soaking plate for keeping the temperature of the entire wafer 44 uniform. . Therefore, the susceptor 94 has a thickness several times that of the wafer 44, that is, a heat capacity several times that of the wafer 44. In addition, a lift mechanism for moving the wafer 44 up and down relative to the susceptor 94 is provided in order to transport the wafer 44 onto the susceptor 94. The general lift mechanism has a plurality of lift pins 93 extending through the susceptor 94, and the wafer 44 is moved up and down by placing the wafer 44 on the upper ends of these lift pins 93 and moving the lift pins 93 up and down. be able to. With such a lift mechanism, the wafer 44 placed on the hand and carried into the chamber 92 can be transferred onto the susceptor 94, or conversely, the wafer 44 can be transferred from the susceptor 94 to the hand. It becomes possible.
[0074]
A susceptor support shaft 95 that supports the susceptor 94 horizontally and serves as a rotation shaft is fixed to the lower surface of the susceptor 94. The susceptor 94 rotates around the susceptor support shaft 95 in the plane parallel to the plate surface of the wafer 44 during the epitaxial layer growth processing operation. The rotation to the susceptor support shaft 95 is given by a rotation drive mechanism (not shown). The susceptor support shaft 95 is made of translucent quartz so as not to block light from the lower heat source 98b.
[0075]
First, the upper and lower heat sources 98a and 98b are operated to raise the temperature in the processing chamber 92 to a temperature suitable for the growth of the epitaxial layer. The epitaxial layer growth temperature is preferably about 1000 to 1200 ° C., and is controlled so as to maintain the above temperature range while detecting the temperature of the susceptor 94 in the reaction furnace 97 with a thermosensor or the like. Thereafter, a carrier gas is poured from the gas inlet 91a, and the reaction furnace 97 is filled with the carrier gas. Since the reaction furnace 97 has the gas discharge port 91b on the opposite side of the gas inlet 91a, the carrier gas always flows from the gas inlet 91a toward the gas discharge port 91b. The carrier gas is generally hydrogen H ₂ In this embodiment, the hydrogen H is used. ₂ Diborane B as an impurity ₂ H ₆ Is used with only a small amount added. Carrier gas is hydrogen H ₂ Diborane B is about 60 l / min. ₂ H ₆ Is about several cc / min. This carrier gas is usually supplied into the reaction furnace 97 at room temperature (room temperature).
[0076]
Next, when the inside of the reaction furnace 97 is sufficiently heated and filled with the carrier gas, this time, the wafer 44 is carried into the reaction furnace 97. At this time, the wafer 44 has a diameter of 203.9 mm and a thickness of about 0.7 to 0.75 mm. The wafer 44 is placed on a quartz hand (not shown), the hand is inserted into the chamber 92, and the wafer 44 is stored in the wafer storage recess 94 a of the susceptor 94. When the susceptor 94 is rotated and the rotation is stabilized, the reaction gas is supplied into the chamber 92 from the gas inlet 91a. The reaction gas is generally trichlorosilane SiHCl ₃ And dichlorosilane SiH ₂ Cl ₂ Etc. are used. For example, trichlorosilane SiHCl ₃ 15 to 25 percent trichlorosilane SiHCl ₃ And the rest is hydrogen H ₂ It is preferable to supply a mixed gas in the carrier gas at a flow rate of about 10 to 15 l / min. The reactive gas flows on the surface of the wafer 44, and an epitaxial layer starts to grow on the wafer surface. Since the wafer 44 is rotated in a horizontal plane while being accommodated in the susceptor 94, an epitaxial layer having a substantially uniform thickness grows on the surface of the wafer 44. When the epitaxial layer having a desired thickness is grown, the supply of the reaction gas is stopped. Next, the processed wafer 44 is unloaded from the chamber 92 using a hand.
[0077]
At the stage where the above epitaxial growth step (STEP 7) is completed, it is desirable that the wafer be 1 mm or more larger than the desired product diameter. More desirably, the wafer should be 2 mm or more larger than the desired product diameter. In the present embodiment, the wafer at the stage where the epitaxial growth step (STEP 7) has been completed is in a state of a diameter of 203.9 mm that is 3 mm or more larger than the desired product diameter (200 mm). Also, the larger the diameter of the wafer, the better. The difference from the desired product diameter after the epitaxial growth process is preferably within 9 mm at most. In particular, the difference from the desired product diameter is preferably within 5 mm.
[0078]
[STEP8]
Subsequently, the wafer on which the epitaxial layer has been grown is chamfered with a reduced diameter (STEP 8). Various types of chamfering devices are known. For example, while rotating a grindstone with a grindstone axis orthogonal to the rotation axis of the wafer, grinding the outer periphery of the wafer while swinging so as to draw an arc in the thickness direction of the wafer, or rotating the wafer There is a tool in which a grindstone having a grindstone shaft parallel to the shaft is rotated and brought into contact with the wafer and moved along the outer shape of the wafer. In the present embodiment, the latter example will be described with reference to the drawings, but naturally, a chamfering device of the type like the former can also be used.
[0079]
FIG. 10 is a conceptual diagram showing an example of a chamfering device. FIG. 10A is a diagram of the chamfering device viewed from above, and FIG. 10B is a diagram of the chamfering device viewed from the lateral direction. Reference numeral 11 denotes a grindstone for chamfering a wafer. As shown in FIG. 10B, the chamfering grindstone 11 has a grindstone working surface 12 having a shape like two abacus beads in the center. The grindstone working surface 12 has various shapes according to the desired chamfering shape of the wafer, and the chamfering angle and chamfering shape of the wafer are determined according to the shape of the grindstone working surface 12.
[0080]
As shown in FIG. 10A, the chamfering grindstone 11 has a circular shape when viewed from above, and includes a grindstone shaft 13 at the center thereof. The chamfering grindstone 11 has an abrasive grain portion in which diamond abrasive grains of # 600 to # 3000 are bonded and fixed to the grindstone working surface 12 by a metal-based binder. The chamfering apparatus generally has a mechanism capable of moving the chamfering grindstone 11 in a three-dimensional direction relative to the wafer 44.
[0081]
In use, the chamfering grindstone 11 is rotated about the grindstone shaft 13 in the direction of the arrow 14, and the outer peripheral portion of the wafer 44 sucked and held by the wafer holding plate is pressed against the grindstone working surface 12 for grinding. As shown in FIG. 10A, the chamfering grindstone 11 is relatively moved in the direction of the arrow 15 along the outer shape of the wafer 44 with the chamfering grindstone 11 pressed against the wafer 44. Chamfering can be performed while reducing the diameter of the wafer 44 by moving the chamfering grindstone 11 little by little toward the center in the radial direction of the wafer 44 as indicated by the broken line arrow 16 in the figure. Further, at this time, the chamfering grindstone 11 is moved in accordance with the shape of the orientation flat or notch, so that the outer peripheral chamfering of the wafer and the orientation flat or notch portion can be chamfered simultaneously.
[0082]
In the reduced diameter chamfering step (STEP 8), a rough chamfering is usually applied to the outer periphery of the wafer 44 by a chamfering grindstone (vitrified grinding grindstone) in which diamond abrasive grains of about # 600 to 800 are first bonded and fixed to a porcelain binder. Processing is applied. Thereafter, the outer peripheral portion of the wafer 44 is subjected to finishing chamfering with a chamfering grindstone having diamond abrasive grains of about # 1500 to 3000. In this rough chamfering and finishing chamfering process, the chamfering grindstone 11 is cut 3.9 mm toward the center of the wafer, and the outer diameter of the wafer is reduced from 203.9 mm to about 200.0 mm. However, just by chamfering by this grinding, the surface roughness of the chamfered surface is large, and from a microscopic viewpoint, countless small pieces of single crystal silicon are fluffed on the surface of the chamfered surface, and these small pieces are missing. Dust generation may occur in subsequent device processes.
[0083]
Therefore, in order to remove this grinding damage and improve the yield of the device process, the chamfered surface is further mirror-polished. A polishing cloth is generally used for mirror polishing of the chamfered surface. The mirror polishing is performed by pressing the outer peripheral portion of the rotating wafer against a polishing cloth to remove small pieces and pieces of single crystal silicon protruding innumerably from the chamfered surface. In some cases, a polishing thread is used instead of the polishing cloth. At the time of polishing, for example, SiO having an average particle diameter of 20 to 100 nm, preferably an average particle diameter of 40 to 80 nm. ₂ A slurry containing abrasive grains is supplied. The polishing allowance by mirror polishing is almost close to 0. However, in consideration of the polishing allowance at the time of mirror polishing, the wafer may be processed larger by about 1 to 2 μm than the diameter of 200 mm during the rough chamfering and finishing chamfering processes.
[0084]
The above-mentioned reduced diameter chamfering process may cause scratches on the surface of the epitaxial layer when the wafer is held, resulting in micro scratches, and scratches on the epitaxial layer due to grinding debris or polishing debris generated during processing. There is a risk. Therefore, it is preferable to coat a protective film on the surface of at least the epitaxial layer of the wafer before the reduced diameter chamfering process and to remove the protective film after the reduced diameter chamfering process. The material of the protective film is not particularly limited as long as it can be uniformly coated on the wafer surface, functions as a protective film, and can be easily removed after the reduced diameter chamfering process. For example, a wax, a resin such as polyvinyl butyral (PVB) or polyimide having a thickness of about 0.5 μm, or an adhesive sheet used as a mask can be used. These resins and sheets can be easily removed by chamfering the diameter and then removing them with chemicals during heating, peeling, or washing.
[0085]
In the above description, an example in which a large orientation flat or notch is formed in a single crystal block in the wafer external grinding step (STEP 2) in anticipation of the reduction in the wafer diameter in the subsequent process has been shown. Can also be formed by a reduced diameter chamfering step (STEP 8). For example, without forming an orientation flat or notch in the wafer external grinding process (STEP 2), marking is performed by laser marking after the slicing process (STEP 3), and the chamfering grindstone is used in the chamfering process (STEP 8) for the diameter reduction chamfering process Orientation flats and notches can also be formed by controlling the trajectory according to the shape. As a result, in the surface grinding / lapping process (STEP 4) and the mirror polishing process (STEP 6), it is possible to process a perfectly round wafer having no notches such as orientation flats and notches. It is possible to prevent non-uniformity due to the influence of the above, and it is possible to keep the grinding pressure and polishing pressure uniform at the outer periphery of the wafer. In this way, by making the grinding pressure and polishing pressure uniform at the outer peripheral portion of the wafer, it is possible to manufacture a high-quality wafer having a high degree of flatness.
[0086]
The wafer having a diameter of 203.9 mm at the stage of the epitaxial growth process (STEP 7) is reduced to a wafer having a diameter of 200.0 mm, which is an actual product, by the above-mentioned reduced diameter chamfering process (STEP 8). At this time, the thinned (peripheral sagging) portion of the epitaxial layer in the vicinity of the wafer outer peripheral portion generated in the epitaxial growth step (STEP 7) is ground and removed together with the reduced diameter chamfering. Thus, by performing the reduced diameter chamfering step (STEP 8) after the epitaxial growth step (STEP 7), it is possible to prevent the thinning of the epitaxial layer (outer peripheral sag) in the vicinity of the outer peripheral portion of the wafer generated in the epitaxial growth step. Wafers with highly uniform epitaxial layers can be produced. Further, the crown generated at the outer peripheral edge of the wafer in the epitaxial growth step (STEP 7) can also be removed.
[0087]
Further, the influence of excessive grinding on the outer peripheral portion of the wafer generated in the surface grinding / lapping step (STEP 4) and peripheral sagging caused by excessive polishing of the outer peripheral portion of the wafer in the mirror polishing step (STEP 6) can also be removed. .
[0088]
[Embodiment 2]
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 11 is a flowchart showing an outline of a semiconductor wafer manufacturing method according to the second embodiment. The process shown in the flow is a simplified illustration of the process for manufacturing a semiconductor wafer. The manufacturing method of the present application includes a laser cleaving process (STEP 8 ') and a chamfering process (STEP 9') after the epitaxial growth process (STEP 7) as described below.
[0089]
Since the contents from STEP 1 to STEP 7 in the present embodiment are the same as those in the first embodiment, the description is omitted, and only the laser cleaving process (STEP 8 ') and the chamfering process (STEP 9') which are different points are described. To do.
[0090]
In the present embodiment, as in the first embodiment, the wafer at the stage where the epitaxial growth step (STEP 7) has been completed is 3 mm or more larger than the desired product diameter (200 mm) and has a diameter of 203.9 mm. .
[0091]
[STEP8 ']
The wafer is melted or cut by a laser. FIG. 12 is a schematic view showing a state in which the wafer after epitaxial growth is cleaved (fused) with a laser. Lasers used for laser fusing or laser cleaving include solid-state YAG laser, ruby laser, sapphire laser, and gas laser CO ₂ There are lasers, argon ion lasers, helium-neon lasers, semiconductor lasers, dye lasers, excimer lasers, free electron lasers, and the like. Among the above lasers, YAG laser, CO ₂ A laser, an excimer laser, a ruby laser, and a sapphire laser are preferable, and a laser having a laser wavelength of 152 nm to 10.6 μm is particularly preferable.
[0092]
In this STEP 8 ′, the wafer 44 is cut (melted) into a circular shape in order to remove an extra outline portion of the wafer. Since the wafer 44 on which the epitaxial layer has grown in STEP 7 has a substantially round shape, in this laser cutting (melting), the inside of the wafer 44 is cut (melting) about 3.8 mm, and the diameter is 200.1 mm. To the next wafer. At this time, by controlling the locus of the laser 17 by program, it can be cut (melted) into a perfect circle regardless of the outer shape of the wafer 44.
[0093]
In this example, an orientation flat or notch is formed on the wafer in the external grinding process (STEP 2). However, in the external grinding process (STEP 2), the orientation flat or notch is not formed. The orientation flat or notch may be formed for the first time in the laser cleaving process. In this case, the crystal orientation may be measured before laser cutting (melting), and the movement locus of the laser 17 may be programmed so that an orientation flat or notch is formed in part instead of a perfect circle. Alternatively, the orientation of the crystal may be measured after laser cutting, and the orientation flat or notch may be formed by controlling the trajectory of the chamfering grindstone 11 during a chamfering step (STEP 9 ') described later. By forming the orientation flat or notch in the laser cutting step (STEP 8 ′) or the chamfering step (STEP 9 ′) in this way, it is not necessary to form the orientation flat or notch in the external grinding step (STEP 2). As a result, in the surface grinding / lapping process (STEP 4) and the mirror polishing process (STEP 6), it is possible to process a round-shaped wafer having no notches such as orientation flats and notches. It is possible to prevent non-uniformity due to the influence of the above, and it is possible to keep the grinding pressure and polishing pressure uniform at the outer periphery of the wafer. Thus, by making the grinding pressure and polishing pressure uniform at the outer peripheral portion of the wafer, it is possible to manufacture a high-quality wafer having a high degree of flatness.
[0094]
Unlike the case of reduced diameter chamfering in the first embodiment, the outer peripheral portion cut out by laser fusing or laser cleaving can be extracted as a bulk-shaped annular member 18 instead of chips. Also, according to laser cleaving (melting), unlike the case of chamfering with a reduced diameter, the annular member 18 can be cleaved (melting) without supplying a processing liquid, so there is no kerf loss and no waste liquid treatment is required. is there. Further, since the cut ring member 18 can be put into the crucible of the single crystal ingot growth step (STEP 1) without being washed and melted, the reusability as a silicon member is also good. Of course, the annular member 18 may be washed and then put into the crucible.
[0095]
In particular, when the diameter of the wafer increases in the future and changes from the current diameter of 200 mm to a large diameter wafer having a diameter of 300 mm or more, the mass of the annular member 18 becomes very large. Therefore, reusing the annular member 18 extracted by laser cutting (melting) is a very effective means from the viewpoint of reducing the manufacturing cost of the wafer.
[0096]
Moreover, the thinned (outer peripheral sag) portion of the epitaxial layer in the vicinity of the outer peripheral portion of the wafer generated in the epitaxial growth step (STEP 7) can be removed as the annular member 18 by laser cutting (melting). Thus, by performing the laser cleaving step (STEP 8 ') after the epitaxial growth step (STEP 7), it is possible to prevent the epitaxial layer from being thinned (peripheral sagging) in the vicinity of the outer peripheral portion of the wafer generated in the epitaxial growth step. Wafers with highly uniform epitaxial layers can be produced. Further, the crown generated at the outer peripheral edge of the wafer in the epitaxial growth step (STEP 7) can also be removed.
[0097]
Further, the influence of excessive grinding on the outer peripheral portion of the wafer generated in the surface grinding / lapping step (STEP 4) and peripheral sag due to excessive polishing of the outer peripheral portion of the wafer in the mirror polishing step (STEP 6) are also removed as the annular member 18. can do.
[0098]
Also, when the diameter of the wafer is reduced by chamfering, it takes about 40 seconds. When the diameter of the wafer is reduced by laser cutting (melting), it takes about 10 seconds, and the processing speed is high. Time can be significantly reduced. Furthermore, laser cutting (melting) is also suitable for the work environment because the processing sound is quiet and does not generate dust.
[0099]
[STEP 9 ']
Subsequently, the outer periphery of the wafer whose diameter has been reduced by the laser cleaving step (STEP 8 ') is chamfered. Hereinafter, although it demonstrates using FIG. 10 similarly to STEP8 of 1st Embodiment, since the thing similar to what was demonstrated in STEP8 is used as a chamfering apparatus, description is given about the specific structure of the apparatus. Omitted.
[0100]
The chamfering grindstone 11 is rotated about the grindstone shaft 13 in the direction of the arrow 14, and the outer peripheral portion of the wafer 44 sucked and held by the wafer holding plate is pressed against the grindstone working surface 12 for grinding. As shown in FIG. 10A, the chamfering grindstone 11 is relatively moved in the direction of the arrow 15 along the outer shape of the wafer 44 with the chamfering grindstone 11 pressed against the wafer 44. In the present embodiment, since there is no intention to reduce the diameter of the wafer in the chamfering step, the cutting amount of the chamfering grindstone 11 may be very small. That is, the feed movement amount of the chamfering grindstone 11 in the direction of the broken line arrow 16 may be small.
In this example, the wafer is cut by 0.1 mm and the diameter of the wafer is processed from 200.1 mm to 200.0 mm. Further, at this time, the chamfering grindstone 11 is moved in accordance with the shape of the orientation flat or the notch, so that the chamfering of the outer shape of the wafer and the chamfering of the orientation flat or the notch can be performed simultaneously.
[0101]
In the chamfering process, rough chamfering is generally performed on the outer periphery of the wafer by a chamfering grindstone (vitrified grindstone) in which diamond abrasive grains of approximately # 600 to 800 are bonded and fixed to a porcelain binder. After that, a finish chamfering process is performed on the outer peripheral portion of the wafer with a chamfering grindstone having diamond abrasive grains of about # 1500 to 3000.
[0102]
Thereafter, the chamfered surface is further mirror-polished. A polishing cloth is generally used for mirror polishing of the chamfered surface. The mirror polishing is performed by pressing the outer peripheral portion of the rotating wafer against a polishing cloth to remove small pieces and pieces of single crystal silicon protruding innumerably from the chamfered surface. In some cases, a polishing thread is used instead of the polishing cloth. At the time of polishing, for example, SiO having an average particle diameter of 20 to 100 nm, preferably an average particle diameter of 40 to 80 nm. ₂ A slurry containing abrasive grains is supplied. The polishing allowance by mirror polishing is almost close to 0. However, in consideration of the polishing allowance at the time of mirror polishing, the wafer may be processed larger by about 1 to 2 μm than the diameter of 200 mm during rough chamfering and finishing chamfering.
[0103]
In the chamfering step (STEP 9 '), when the wafer is held, the surface of the epitaxial layer may be chucked to cause a fine scratch, and the epitaxial layer may be damaged by grinding residue or polishing residue generated during processing. Therefore, it is preferable to coat a protective film on at least the epitaxial layer surface of the wafer before the chamfering process and remove the protective film after the chamfering process. The material of the protective film is not particularly limited as long as it can be uniformly coated on the wafer surface, functions as a protective film, and can be easily removed after chamfering. For example, a wax, a resin such as polyvinyl butyral (PVB) or polyimide having a thickness of about 0.5 μm, or an adhesive sheet used as a mask can be used. After chamfering, these resins and sheets can be easily removed by heating, peeling, or removing with chemicals in a cleaning process.
[0104]
According to the present embodiment, the outer peripheral portion cut by laser fusing or laser cleaving is extracted as a bulk-shaped annular member instead of chips, unlike the case of reduced diameter chamfering in the first embodiment. Can do. Therefore, the laser-cleaved (fused) annular member can be reused as a silicon member by being introduced into the crucible of the single crystal ingot growth step (STEP 1) and melted. Further, according to laser cutting (melting), unlike the case of reduced diameter chamfering, cutting (melting) can be performed without supplying a working fluid. Therefore, the laser-cleaved (fused) ring member can be put into the crucible of the single crystal ingot growth step (STEP 1) without washing.
[0105]
In particular, when the diameter of a wafer increases in the future and changes from a current diameter of 200 mm to a large diameter wafer having a diameter of 300 mm or more, the mass of the portion to be reduced in the wafer manufacturing process becomes very large. . For this reason, adopting laser cutting (melting) for reducing the diameter of the wafer and reusing the extracted member is a very effective means from the viewpoint of reducing the manufacturing cost of the wafer.
[0106]
The mirror surface wafer manufactured by the method shown in the first and second embodiments has a desired product diameter and is excellent in flatness over the entire wafer surface, particularly near the outermost peripheral portion. There is no peripheral sagging that suddenly falls into the measurement area, and the yield rate of wafers can be significantly improved. Further, by using such a wafer, a circuit can be formed on the entire surface, and the productivity of the semiconductor device can be improved. In addition, in the method according to the present invention, the apparatus used in the conventional mirror surface wafer manufacturing process can be used as it is, and since it is not necessary to add another apparatus, a mirror surface wafer having excellent surface characteristics can be easily produced at low cost. Can be manufactured.
[0107]
In any of the first and second embodiments, the external grinding step (STEP 2) can be omitted, and the surface grinding / lapping step (STEP 4) and the etching step (STEP 5) can be omitted. You can also. Further, for example, the manufacturing process of the wafer according to the present invention described in each embodiment is an example, and it is needless to say that cleaning can be appropriately performed between the processes. In particular, the steps from STEP 1 to STEP 7 can be replaced, omitted, or added in a part of the steps without departing from the spirit of the present application.
[0108]
Needless to say, the present invention can be applied to either single-side polishing or double-side polishing. As for the material and size of the wafer, there is no limitation in carrying out the present invention. Of course, semiconductor wafers such as silicon, GaAs, GaP, and InP of the diameter that are currently manufactured can be manufactured in the future. The present invention can also be applied to a large wafer.
[0109]
[Implementation data]
The effects when a wafer is manufactured using a conventional manufacturing method and when the wafer is manufactured using the manufacturing method of the present invention will be specifically described below.
[0110]
A plurality of quadrangles of a predetermined size were sampled from the manufactured wafer, and the difference from the desired wafer thickness was determined for each sample. And the value of each sample was averaged and the average value was computed. As a result, the sub flatness SFQR of the wafer manufactured by the conventional manufacturing method was 0.146 μm. In contrast, the sub-flatness SFQR of the wafer manufactured by the manufacturing method of the present invention was 0.116 μm. From the results of the sub flatness SFQR, an improvement in flatness of 0.03 μm was observed.
[0111]
Furthermore, according to the present invention, it is possible to prevent the outer peripheral sagging of the epitaxial layer at the outer peripheral portion of the wafer. FIG. 13B shows the result. FIG. 13B is a film thickness distribution diagram when an epitaxial layer is grown on a mirror-polished wafer by the manufacturing method of the present invention. The horizontal axis represents the displacement in the diameter direction of the wafer, and the vertical axis represents the film thickness of the epitaxial layer. Compared with the wafer manufactured by the conventional manufacturing method shown in FIG. 13A, it can be seen that the drop in the thickness of the epitaxial layer in the vicinity of the outer peripheral portion is significantly less. In addition, a plurality of squares having a predetermined dimension were sampled from the manufactured wafer, and the percentage of the difference from the target value of the film thickness of the epitaxial layer was determined for each sample. And the value of each sample was averaged and the average value was computed. As a result, the film thickness Δt of the epitaxial layer manufactured by the conventional manufacturing method was 2.11%. On the other hand, the film thickness Δt of the epitaxial layer manufactured by the manufacturing method of the present invention was 0.93%. From the result of the film thickness Δt of the epitaxial layer, an improvement of 1.18% was observed.
[0112]
Next, a plurality of quadrangles of a predetermined size were sampled from the manufactured wafer, and the percentage of the difference from the target value of the resistivity of the epitaxial layer was determined for each sample. And the value of each sample was averaged and the average value was computed. As a result, the resistivity Δρ of the epitaxial layer manufactured by the conventional manufacturing method was 10.07%. On the other hand, the resistivity Δρ of the epitaxial layer manufactured by the manufacturing method of the present invention was 7.49%. The result of the resistivity Δρ of the epitaxial layer showed an improvement of 2.58%.
[0113]
【The invention's effect】
According to the wafer manufacturing method of the present invention, it is possible to manufacture a wafer having a very small peripheral sagging region of the wafer thickness or no peripheral sagging at all.
[0114]
Further, according to the wafer manufacturing method of the present invention, it is possible to prevent the epitaxial layer from being thinned (peripheral sagging) in the vicinity of the wafer outer peripheral portion, and to manufacture a semiconductor wafer having a highly uniform epitaxial layer.
[0115]
Furthermore, according to the wafer manufacturing method of the present invention, the manufacturing process at the time of semiconductor wafer manufacturing is greatly streamlined to improve productivity, and the silicon that is the raw material of the semiconductor wafer is prevented from being wasted. Can do. As a result, the manufacturing cost of the semiconductor wafer can be significantly reduced.
[Brief description of the drawings]
FIG. 1 is a flowchart showing an outline of a method for manufacturing a semiconductor wafer in a first embodiment of the present invention;
FIG. 2 is a longitudinal sectional view schematically showing a single crystal ingot manufacturing apparatus using a CZ method.
FIG. 3 is a plan view schematically showing a cylindrical grinder used for external grinding.
FIG. 4 is a perspective view schematically showing an example of a blade saw.
FIG. 5 is a perspective view schematically showing an example of a wire saw.
FIG. 6 is a front view showing an example of a vertical double-head grinding machine.
FIG. 7A is a conceptual diagram schematically showing the plane of the lapping machine, and FIG. 7B is a conceptual diagram schematically showing the side surface of the lapping machine.
FIG. 8 is a longitudinal sectional view schematically showing an example of a polishing disk.
FIG. 9 is a longitudinal sectional view showing a part of a single wafer type epitaxial manufacturing apparatus as an example of the epitaxial manufacturing apparatus;
FIG. 10A is a conceptual diagram schematically showing a plane of the chamfering device, and FIG. 10B is a conceptual diagram schematically showing a side surface of the chamfering device.
FIG. 11 is a flowchart showing an outline of a method for manufacturing a semiconductor wafer in a second embodiment of the present invention;
FIG. 12 is a schematic diagram showing a state in which a wafer after epitaxial growth is cleaved (fused) by a laser.
13A is a film thickness distribution diagram when an epitaxial layer is grown on a wafer after mirror polishing by a conventional manufacturing method, and FIG. 13B is a mirror polishing by the manufacturing method of the present invention. It is a film thickness distribution diagram when an epitaxial layer is grown on a subsequent wafer.
FIG. 14 is a flowchart showing an outline of a conventional method for manufacturing a semiconductor wafer.
[Explanation of symbols]
11 ... Whetstone for chamfering
12 ... Wheel surface
13 ... Whetstone shaft
14 ... Arrow
15 ... Arrow
16 ... dashed arrow
17 ... Laser
18 ... Ring member
21 ... Supply port
22 ... crucible 22a ... crucible support shaft
23 ... Heater
24. Melt
25 ... Pulling wire
26 ... Seed crystal
27 ... Single crystal 27a ... Shoulder spread
28 ... Vacuum pump
29 ... Chamber
30 ... Body
31 ... Rotating whetstone
33 ... Work table
34 ... Work rotating motor 34a ... Rotating shaft
35 ... Table feed motor
36 ... Wheel feeding motor
37 ... Wheel driving motor
38a ... pulley 38b ... pulley 38c ... belt
39 ... Whetstone table
41 ... Inner peripheral blade
42 ... support stand
43 ... Single crystal block
44 ... wafer
50 ... Body
51a ... Bracket 51b ... Bracket
53 ... Work support head
54 ... Work feed motor
55 ... Laura
56 ... Laura
57 ... Laura
58 ... Wire
60 ... Servo motor
61 ... Frame
63 ... Frame
64: Whetstone rotation mechanism
65. Work support mechanism
66 ... Wheel rotation mechanism
67 ... Whetstone 67a ... Grinding surface
68 ... Whetstone 68a ... Grinding surface
69 ... Servo motor
71 ... Upper surface plate
72 ... Lower surface plate
73 ... Career
74 ... Housing hole
75 ... Outer gear
76 ... Inner gear
77 ... Drive gear
81 ... surface plate
82 ... Slurry nozzle
83 ... Polishing head
84 ... Rotating shaft
85 ... Polishing cloth
86 ... Rotating shaft
87 ... Suction tube
88 ... Slurry
91a ... Inlet 91b ... Discharge port
92 ... Chamber 92a ... Window 92b ... Window
93 ... Lift pin
94: Susceptor 94a: Recess for storing wafer
95 ... Susceptor support shaft
97 ... Reactor
98a ... Heat source 98b ... Heat source.

Claims (14)

In a method of manufacturing a semiconductor wafer by performing epitaxial growth processing on the wafer,
The wafer is not formed with orientation flats or notches until the epitaxial growth process, and the diameter of the wafer during the epitaxial growth process is larger than the product diameter.
After the epitaxial growth process, the peripheral portion of the wafer is removed to the product diameter to further form an orientation flat or notch ,
A method for manufacturing a semiconductor wafer. 2. The method of manufacturing a semiconductor wafer according to claim 1, wherein the means for removing the peripheral portion of the wafer is reduced diameter chamfering, cleaving with a laser, or fusing with a laser . In a method of manufacturing a semiconductor wafer by performing epitaxial growth processing on the wafer,
The diameter of the wafer at the time of the epitaxial growth process is larger than the product diameter, and after the epitaxial growth process, the peripheral portion of the wafer is removed up to the product diameter by cleaving by laser or fusing by laser ,
A method for manufacturing a semiconductor wafer. The laser is
YAG laser, CO ₂ laser, excimer laser, ruby laser, a method of manufacturing a semiconductor wafer according to claim 3, characterized in that any one selected from among sapphire laser.   4. The method of manufacturing a semiconductor wafer according to claim 3, wherein a wavelength of the laser is 152 nm to 10.6 [mu] m. After removing the peripheral portion of the wafer by laser, chamfering the outer periphery of the wafer,
The method for producing a semiconductor wafer according to any one of claims 3 to 5, wherein:   The method of manufacturing a semiconductor wafer according to claim 1, wherein a diameter of the wafer during the epitaxial growth process is 1 mm or more larger than a product diameter.   The method of manufacturing a semiconductor wafer according to claim 1, wherein a diameter of the wafer during the epitaxial growth process is 1 to 9 mm larger than a product diameter. After the epitaxial growth process, before removing the peripheral portion of the wafer, at least the surface of the wafer where the epitaxial layer is formed is coated with a protective film,
Removing the protective film after removing the peripheral portion of the wafer;
The method for producing a semiconductor wafer according to any one of claims 1 to 8 , wherein: A semiconductor having a step of growing a single crystal ingot, a step of grinding an outer shape, a step of slicing, a step of planarizing a sliced wafer, and a step of growing an epitaxial layer on at least one surface of the wafer In the wafer manufacturing method,
The diameter of the wafer up to the step of growing the epitaxial layer shall be larger than the desired product diameter,
After the step of growing the epitaxial layer, there is a step of removing the peripheral portion of the wafer to the desired product diameter by laser cutting or laser cutting .
A method for manufacturing a semiconductor wafer. A semiconductor having a step of growing a single crystal ingot, a step of grinding an outer shape, a step of slicing, a step of planarizing a sliced wafer, and a step of growing an epitaxial layer on at least one surface of the wafer In the wafer manufacturing method,
Until the step of growing the epitaxial layer, do not form orientation flats and notches in the wafer, the diameter of the wafer is larger than the desired product diameter,
After the step of growing the epitaxial layer, there is a step of removing a peripheral portion of the wafer to the desired product diameter and further forming an orientation flat or notch .
A method for manufacturing a semiconductor wafer. A wafer having a diameter larger than the product diameter without orientation flats or notches being formed until the epitaxial growth process is subjected to an epitaxial growth process.
After the epitaxial growth process, a semiconductor wafer in which a peripheral portion of the wafer is removed up to the product diameter and an orientation flat or notch is further formed. An epitaxial growth process is performed on a wafer having a diameter larger than the product diameter,
A semiconductor wafer formed by removing the peripheral portion of the wafer to the product diameter by laser cutting or laser fusing after the epitaxial growth process. After the epitaxial growth process, before the peripheral portion of the wafer is removed , at least the surface of the wafer on which the epitaxial layer is formed is coated with a protective film,
The semiconductor wafer according to claim 12 or 13, wherein a peripheral portion of the wafer is removed up to the product diameter.

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