JP4249741B2 - Bus system and information processing system including bus system - Google Patents

Description

  The present invention relates to a bus system and an information processing system including the bus system, and in particular, data for sharing a control command line between a plurality of buses having different bit widths and transferring data to each other while converting the bit widths. The present invention relates to a bus system including a conversion unit and an information processing system including the bus system.

2. Description of the Related Art In recent years, attention has been focused on techniques for reducing LSI design time and development costs by designing LSIs by connecting previously developed circuit blocks as design property (Intellectual Property: IP) cores. Since such circuit blocks are often developed independently, there are differences in bus width and input / output interface between the blocks. Therefore, in order to connect each block, a technique for absorbing the difference in bus width and input / output interface is required. For example, a bridge circuit described in Japanese Patent Application Laid-Open No. 2000-311132 is used as an interface circuit that absorbs such interface differences.
JP 2000-311132 A

As shown in FIG. 39, the bus connection circuit using the bridge circuit includes a first bus 1001 including a 64-bit data line and a control command line, and a second bus 1002 including a 32-bit data line and a control command line. A bus bridge circuit 1003 connected between the bus 1001 and the bus 1002, a bus master unit 1004, 1005 having a 64-bit data line connected to the first bus 1001, and a bus slave having a 64-bit data line. Units 1006, 1007, bus master units 1008, 1009 having 32-bit data lines connected to the second bus 1002, bus slave units 1010, 1011 having 32-bit data lines, and the first bus 1001 side Arbitration circuit 1012 and arbitration circuit on the second bus 1002 side And a 013.

The operation of the conventional bus connection circuit will be described below with reference to FIG. Data transfer methods include non-split transfer in which command transfer and data transfer are continuously performed, and split transfer in which command transfer and data transfer are discontinuously performed. explain.

When the bus master unit 1004 receives a read command and an address output from an external master unit (not shown) such as a CPU, the bus master unit 1004 outputs an arbitration request signal to the arbitration circuit 1012 in order to obtain the bus right of the first bus 1001. . The arbitration circuit 1012 grants the bus right of the first bus 1001 to the bus master unit 1004 by outputting an arbitration grant signal after arbitration. The bus master unit 1004 that has obtained the bus right outputs a read command, an address, and a device ID (a number uniquely assigned to each connected master) to the first bus 1001 via the control command line. The bus right of the first bus 1001 is released.

The bus bridge circuit 1003 receives the read command, address, and device ID output to the first bus 1001 and detects from the address that it is a read command for the bus slave unit 1011. Since the bus slave unit 1011 is connected to the second bus 1002, the bus bridge circuit 1003 outputs an arbitration request signal to the arbitration circuit 1013 in order to obtain the bus right of the second bus 1002. The arbitration circuit 1013 gives the bus right of the second bus 1002 to the bus bridge circuit 1003 by outputting an arbitration grant signal after arbitration. The bus bridge circuit 1003 that has obtained the bus right outputs the read command, the address, and the device ID to the second bus 1002, and releases the bus right of the second bus 1002.

The bus slave unit 1011 detects that the address indicates itself, receives the read command, and transfers the read command to an external slave unit (not shown) connected to the bus slave unit 1011. The external slave unit that has received the read command performs processing based on the read command and outputs read data to the bus slave unit 1011. The bus slave unit 1011 that has received the read data outputs an arbitration request signal to the arbitration circuit 1013 in order to obtain the bus right of the second bus 1002. The arbitration circuit 1013 gives the bus right of the second bus 1002 to the bus slave unit 1011 by outputting an arbitration grant signal after arbitration.

The bus slave unit 1011 that has obtained the bus right outputs the read data and the device ID to the second bus 1002, and releases the bus right of the second bus 1002. The bus bridge circuit 1003 detects that the data is output to the bus master unit 1004 from the device ID output to the second bus 1002, outputs an arbitration request signal to the arbitration circuit 1012, and the arbitration circuit 1012 And the arbitration grant signal is output to give the bus right of the first bus 1001 to the bus bridge circuit.

The bus bridge circuit 1003 that has obtained the bus right converts the received 32-bit width read data into 64-bit width data, outputs the read data together with the device ID to the first bus, and grants the bus right of the first bus 1001. Open. Since the device ID on the first bus 1001 matches the own device ID, the bus master unit 1004 takes in the read data on the first bus 1001 and outputs the fetched data to the external master unit. In this way, non-split transfer based on the read command is executed.

In the case of split transfer based on the write command, the operation is as follows. After securing the bus right of the first bus 1001, the bus master unit 1004 outputs the write command, address, and write data to the first bus, and releases the bus right of the first bus 1001. The bus bridge circuit 1003 that has received the 64-bit write data secures the right of the second bus 1002 based on the address, and then converts the 64-bit write data into 32-bit write data, The address is output to the second bus 1002 together with the address, and the bus right of the second bus 1002 is released. The bus slave unit 1011 receives a write command and write data and transfers them to the external slave unit. The external slave unit performs a write data write operation based on the write command.

In the case of non-split transfer, the bus slave units 1006, 1007, 1010, 1011 do not need to secure the bus right, so in FIG. 39, arbitration requests between the bus slave units and the arbitration circuits 1012, 1013 are shown. The line and the arbitration grant line will be described as not existing.

In the case of the non-split transfer based on the read command, the bus master unit 1004 does not release the bus right of the first bus 1001 until the read data from the bus slave unit 1011 is received. The bus right of the bus 1002 is not released until read data is received from the bus slave unit. The non-split transfer based on the write command is almost the same as the split transfer except that the bus master unit 1004 does not release the first bus right after outputting the write data, the write command, and the address to the first bus 1001. Therefore, explanation is omitted.

As described above, the number of times of acquiring the bus right, that is, the number of times that arbitration is required by the arbitration circuit, is 4 split transfers when executing a read command, 2 times when performing non-split transfer, and both when transferring a write command. 2 times. Usually, at least 4 clocks are required for one arbitration operation, so 8 to 16 clocks are required for the arbitration operation.

  As described above, in the conventional bus connection circuit, the bus bridge circuit has a large number of arbitrations for performing data transfer between the buses, so the time required for the arbitration operation is long. descend. Furthermore, when the write command is executed, the bus master unit releases the bus right of the first bus and finishes the bus cycle before the write data transfer to the slave side is completed. There is a risk of loss. Therefore, when a transfer error occurs, an extra circuit for notifying the bus master unit of the transfer error is required.

Further, in order to notify the transfer error to the bus master unit, it is necessary that the bus bridge circuit acquires the bus right of the first bus through arbitration by the arbitration circuit, and further arbitration occurs when a transfer error occurs. The number of times increases, and the throughput of the bus deteriorates. If the right of the first bus is not released, write data will not be lost when an error occurs, but the first bus will be occupied until the bus cycle is completed, so the bus usage efficiency will be reduced. To do.

In the conventional bus connection circuit, the bus bridge circuit 1003 needs to be equipped with bus control circuits corresponding to the bus master unit and the bus slave unit in the first bus and the second bus, respectively. Therefore, in the conventional bus control circuit described above, the bus bridge circuit includes a bus master control circuit for the first bus, a bus master control circuit for the second bus, a bus slave control circuit for the first bus, and a bus for the second bus. A total of four slave control circuits are required. Thus, the circuit scale of the bus bridge circuit increases corresponding to the number of buses connected to the bus bridge circuit.

The present invention has been made in view of the above-described circumstances, and there are few clock cycles for bus connection in read access and write access, and there is no risk of data loss at the time of a transfer error. An object of the present invention is to provide a bus connection circuit, an information processing system using the bus connection circuit, and a storage medium storing connection information of the bus connection circuit, which requires a small amount of hardware in terms of circuit configuration.

  In order to solve the above problems, a first invention according to a bus system includes a common control command bus for commonly connecting control command lines of a plurality of buses having data lines having different bit widths, and a data line having the different bit widths. And a data conversion circuit for converting the bit width between these data lines, so that the bit width can be mutually converted in the same bus cycle between a plurality of buses having data lines having different bit widths. It is characterized by comprising.

According to a second aspect of the present invention, there is provided a first bus connected to the first interface means via a first control command line and a first bit width data line, and a second control. The second bus connected to the second interface means via the command line and the data line of the second bit width is connected in common to the first and second control command lines, and the common command information is A common control command bus to be transmitted, a data conversion circuit for connecting the first and second data lines and converting the bit widths of the respective data lines, and an arbitration request from the first and second interface means And an arbitration circuit for arbitrating the bus rights of the first and second buses.

According to a third aspect of the present invention, there is provided a first write bus connected to the first interface means via the first write control command line and the write data line having the first bit width, A first read bus connected to the first interface means via a read control command line and a read data line of the first bit width; a second write control command line and a write of a second bit width; A second write bus connected to the second interface means via the data line, and a second read control command line and a read data line having the second bit width connected to the second interface means. A second read bus, a first common control command bus for commonly connecting the first write control command line and the second write control command line, and the first A second common control command bus that commonly connects the read control command line and the second read control command line, and the first write bus and the second write bus, and the write bus A write data conversion circuit that performs bit width conversion between the first read bus and the second read bus, and a read data conversion circuit that performs bit width conversion between the read buses, In response to a request from the first or second interface, a first arbitration circuit that arbitrates the bus right of the first and second write buses, and a request from the first or second interface And a second arbitration circuit that performs arbitration of the bus right of the first and second read buses in response.

According to a fourth aspect of the bus system, n buses having different bit widths for connecting the master side interface means and the slave side interface means via the control command line and the data line, Data conversion for performing bit width conversion between data lines having different bit widths, each of which is connected to a common control command bus for commonly connecting the control command lines of the n buses and the data lines of the n buses. A circuit; and an arbitration circuit that performs arbitration for the n buses simultaneously.

According to a fifth aspect of the present invention, there is provided a first bus having a data line having a first bit width, a first unit connected to the first bus, and data having a second bit width. A second bus having a line, a second unit connected to the first bus, and the first bus when a command is output from the first unit to the second unit. And an arbitration circuit that performs arbitration of the second bus at the same time, a conversion circuit that performs a conversion operation between a first bit and a second bit between the first bus and the second bus, And a common control command bus for connecting the first bus and the second bus.

In the first to fifth aspects of the bus system, the common control command bus and the data conversion circuit are provided, so that data is read and written with a small number of clock cycles between buses having different data line bit widths. can do.

According to a sixth aspect of the bus connection circuit, the first output signal and the first enable signal output from the first unit having the first data bit width, and the first data bit width are set. Receiving the second output signal and the second enable signal output from the second unit having the first or second output in response to the activation of the first or second enable signal. A first selection circuit that selectively outputs a signal, and a third output signal and a third enable signal output from a third unit having a second data bit width different from the first data bit width. Receiving the third output signal and the third enable signal supplied via the conversion unit, the output of the first selection circuit, and the signal based on the first and second enable signals, When the first or second enable signal is active, the output of the first selection circuit is supplied to the first and second units, and when the third enable signal is active, the third output signal is supplied. And a second selection circuit for supplying the first and second units.

According to a seventh aspect of the bus connection circuit, the first output signal and the first enable signal output from the first bus master unit having the first data bit width, and the first data bit width. Receiving the second output signal and the second enable signal output from the second bus master unit, and in response to the first or second enable signal becoming active, the first or second A first selection circuit that selectively outputs an output signal, and a third output signal and a third enable signal output from a third bus master unit having a second data bit width different from the first data bit width And based on the third output signal, the third enable signal, the output of the first selection circuit, and the first and second enable signals supplied via the conversion unit. When the first or second enable signal is active, the output of the first selection circuit is supplied to the bus slave unit having the first data bit width and the third enable signal is received. A second selection circuit is provided that supplies the third output signal to the bus slave unit when a signal is active.

An eighth invention according to the bus connection circuit includes a first output signal and a first enable signal output from a first bus slave unit having a first data bit width, and the first data bit width. Receiving the second output signal and the second enable signal output from the second bus slave unit of the first bus, and in response to the first or second enable signal becoming active, A first selection circuit that selectively outputs two output signals, a third output signal output from a third bus master unit having a second data bit width different from the first data bit width, and a third output signal An enable signal, which is supplied to the third output signal, the third enable signal, the output of the first selection circuit, and the first and second enable signals supplied via the conversion unit. It receives the signal that brute,
When the first or second enable signal is active, the output of the first selection circuit is supplied to the bus master unit having the first data bit width, and when the third enable signal is active, And a second selection circuit for supplying a third output signal to the bus master unit.

In the sixth to eighth aspects of the bus connection circuit, the bus can be easily configured using the selection circuit. In addition, since the information processing system can be assembled including the first to fifth bus connection circuits, high-speed operation is possible.

  In the bus control circuit and the bus system of the present invention, first, the number of arbitration operations when acquiring the bus right between a plurality of buses having data lines having different bit widths can be reduced, so that the bus use efficiency is improved. And high speed access between the bus master unit and the bus slave unit. Secondly, the present invention is not limited to connecting two types of buses having different bus widths, and can be applied to connecting three or more types of buses having different bus widths. .

Third, even when a data transfer error occurs, since there is a common control command bus that connects the first bus and the second bus, the transmission destination can be notified of the occurrence of the data transfer error. Finally, since a plurality of bus master units and slave units can be controlled by a common control circuit, the circuit configuration can be simplified and the required amount of hardware can be reduced.

  Hereinafter, a typical embodiment of the present invention will be described with reference to FIG. The embodiment of the present invention includes a data conversion unit provided between the bus 1 and the bus 2, a common command bus 50 that connects the control command line of the bus 1 and the control command line of the bus 2, and the bus 1 And an arbitration circuit provided in common to the bus master unit and the bus slave unit connected to the bus 2. Hereinafter, a detailed description will be given using examples.

FIG. 1 is a block diagram showing a configuration of a bus system according to a first embodiment of the present invention, and FIG. 2 is a diagram showing a system configuration including a common control command bus of the bus system of the present embodiment. 3 is a diagram showing the configuration of the bus master unit in this embodiment, FIG. 4 is a diagram showing the configuration of the data conversion unit in this embodiment, and FIG. 5 is a diagram showing the configuration of the bus slave unit in this embodiment. FIG. 6 is a timing chart showing a data transfer operation at the time of read access from a 32-bit bus master unit to a 64-bit bus slave unit in this embodiment, and FIG. 7 is a timing chart of the 64-bit bus master unit in this embodiment. FIG. 8 is a timing chart showing a data transfer operation during read access to a 32-bit bus slave unit. FIG. 9 is a timing chart showing a data transfer operation at the time of write access from a 64-bit bus master unit to a 32-bit bus slave unit, and FIG. 9 shows from the 32-bit bus master unit to the 64-bit bus slave unit in this embodiment. 6 is a timing chart showing a data transfer operation during write access.

As shown in FIG. 1, the bus system (bus connection circuit) of this embodiment is connected to a bus 1 connected to a control command line and a 64-bit data line, and to a control command line and a 32-bit data line. A bus 2, a data conversion unit 3, a common control command bus 50 for connecting the control command lines of the bus 1 and the bus 2, and bus master units 4 and 5 connected to the bus 1 via a control command line and a 64-bit data line And bus slave units 6, 7, bus master units 8, 9 and bus slave units 10, 11 connected to the bus 2 via control command lines and 32-bit data lines, and bus master units 4, 5, 8, 9, and And an arbitration circuit 12 connected to the bus slave units 6, 7, 10, and 11.

In this embodiment, a read bus for transferring read data and a write bus for transferring commands and write data are common, and a bus having a data width of 64 bits and a bus having a data width of 32 bits are used. A bus connection circuit for connecting between them will be described. In this embodiment, it is assumed that split transfer is performed during read access.

Here, the bus master unit indicates an interface unit between the external master unit and the bus. The external master unit is a unit having a function of issuing a command, and corresponds to, for example, a central processing unit (CPU), a DMA controller for controlling DMA (Direct Memory Access) transfer of data to a memory, and the like. In FIG. 1, a CPU 114, a 64-bit DMA controller (master) 115, a 32-bit PCI bridge (master) 118, and an Ethernet (registered trademark) 119 with a 32-bit DMA controller are shown as external master units.

The bus slave unit indicates an interface unit between the external slave unit and the bus. The external slave unit is a unit that performs processing in response to a command issued by the external master unit, and corresponds to, for example, an input / output circuit (I / O) or a memory. FIG. 1 shows a memory 116, a 64-bit DMA controller (slave) 117, a 32-bit PCI bridge (slave) 120, and an Ethernet (slave) 121 with a 32-bit DMA controller as external slave units.

The bus 1 is composed of a 64-bit data line for transmitting / receiving 64-bit data and a control command line for transmitting / receiving a control command, and the bus 2 is 32 for transmitting / receiving 32-bit data. It consists of a bit data line and a control command line for sending and receiving control commands. The control command line of the bus 1 and the control command line of the bus 2 are connected via a common control command bus 50. The data conversion unit 3 performs a bit width conversion between 64-bit data and 32-bit data between the bus 1 and the bus 2, for example, converts 32 bits into 64 bits, or 64 bits. Convert bits to 32 bits.

The bus master units 4 and 5 are connected to the bus 1 via a control command line and a 64-bit data line, and the bus master units 8 and 9 are connected to the bus 2 via a control command line and a 32-bit data line. Yes. Each bus master unit provides an interface between the external master unit and the bus 1 or the bus 2. The bus slave units 6 and 7 are connected to the bus 1 via a control command line and a 64-bit data line, and the bus slave units 10 and 11 are connected to the bus 2 via a control command line and a 32-bit data line. Has been. Each bus slave unit provides an interface between the bus 1 or bus 2 and the external slave unit.

The arbitration circuit 12 performs arbitration of the bus right in the bus 1 and the bus 2 according to the arbitration request signal output from each bus master unit or bus slave unit, and when the bus right is established, the request source The bus master unit or bus slave unit is notified of the acquisition of the bus right.

The basic operation flow of the present invention will be briefly described below. When the external master unit executes a read command, it is as follows. The CPU 114 outputs a read command for the 32-bit PCI bridge (slave) 120 to the bus master unit 4. The bus master unit 4 makes an arbitration request to the arbitration circuit 12 and acquires the bus rights of the bus 1 and the bus 2. The bus master unit 4 that has acquired the bus right outputs a read command to the bus 1, and the read command on the bus 1 is transmitted to the bus 2 via the common command bus 50. The bus slave unit 10 that has received the read command via the bus 2 transmits the read command to the 32-bit PCI bridge 120.

The 32-bit PCI bridge 120 outputs data to the bus slave unit 10 based on the read command, and the bus slave unit 10 outputs the received data to the bus 2 for sending to the CPU 114. Since the data on the bus 2 is 32-bit data and the receiving CPU 114 has a 64-bit data width, the data conversion unit 3 performs conversion from 32-bit data to 64-bit data. Are output to bus 1. The bus master unit 4 that has received the converted data via the bus 1 transmits the data to the CPU 114.

The operation when the external master unit executes a write command is as follows. The CPU 114 outputs a write command and write data for the 32-bit PCI bridge (slave) to the bus master unit 4. The bus master unit 4 makes an arbitration request to the arbitration circuit 12 and obtains the bus right for the bus 1 and the bus 2. The bus master unit 4 that has obtained the bus right outputs a write command and write data to the bus 1. The write command is transmitted to the bus 2 via the common control bus 50, and the write data is converted from 64-bit data to 32-bit data by the data conversion unit 3 and transmitted to the bus 2. The bus slave unit 10 receives write data and a write command via the bus 2 and transmits them to the 32-bit PCI bridge.

Next, the signal lines of the bus connection circuit of FIG. 1 will be described in detail with reference to FIG. In the figure, (1) to (13) represent the following control command lines and signal lines of the common control command bus.

The control command lines of the bus 1 are (1): Frame 64, (2): Master, (3): Address, (4): CMD, (5): DID, (7): Dvalid64, (8): ACK, (9): NACK, (10): Devsel is transmitted. The 64-bit data line of the bus 1 transmits (6): Data64. The control command lines of the bus 2 are (11): Frame 32, (2): Master, (3): Address, (4): CMD, (5): DID, (13): Dvalid32, (8): ACK, (9): NACK, (10): Devsel is transmitted. The 32-bit data line of the bus 2 transmits (12): Data32. The common control command bus 50 is connected between the bus 1 and the bus 2 (2): Master, (3): Address, (4): CMD, (5): DID, (8): ACK, (9): NACK, (10): Transmit Devsel.

Here, Frame 64 is information indicating occupation of a 64-bit bus, Master is information indicating transfer from the bus master unit to the bus slave unit, Address is address data for specifying the bus slave unit, Cmd is command data indicating the type of command, DID data is a device ID for specifying the bus master unit, Data 64 is transfer data on the 64-bit data line in the bus 1, and Dvalid 64 is transfer data on the data line. Information indicating the valid period of ACK, ACK is information indicating that the selected unit can perform the requested operation, and NACK is that the selected unit performs the requested operation. Devsel is an external slave unit Information indicating that the bus is selected, Frame 32 is information indicating the occupation of the 32-bit bus, Data 32 is transfer data on the 32-bit data line in the bus 2, and Dvalid 32 is on the 32-bit data line. The information indicating the valid period of the transfer data is shown.

However, it is assumed that the DID data is a unique value for each bus master unit. The DID data may be given from outside the bus master or may be held in a register in the bus master.

The system configuration diagram shown in FIG. 2 shows a case where the bus structure is a multiplexer type, but in the case of a three-state buffer type, it is necessary to distinguish between an ACK signal of 32 bits and a case of 64 bits. The explanation is omitted because it is the same except there is. Hereinafter, the operation of the present embodiment will be described with reference to a timing chart and descriptions of each component block.

In the first embodiment of the present invention, a command is sent from the CPU 30 having a 32-bit data width connected to the bus master unit 9 to the external slave unit 40 having a 64-bit data width connected to the bus slave unit 6. The bus system in the case where is output will be described with reference to FIG. 2, FIG. 3, FIG. 4, FIG. Note that data on the bus is controlled by split transfer.

First, the configuration of the bus master units 4, 5, 8, and 9, the data conversion unit 3, and the bus slave units 6, 7, 10, and 11 will be described. As shown in FIG. 3, the bus master units 4, 5, 8, and 9 include a bus address buffer 31A, a bus command buffer 31B, a bus write data buffer 32, a bus read data buffer 33, a bus master control circuit 34, and multiplexers 35A and 35B. , 35C, 36, a DID comparison circuit 37, and a timing control circuit 38.

As shown in FIG. 4, the data conversion unit 3 includes a data buffer 21, a timing control unit 22, and multiplexers 23, 24, 25, and 26. As shown in FIG. 5, the bus slave units 6, 7, 10, and 11 include bus command buffers 41A, 41B, and 41C, a bus write data buffer 42, a bus read data buffer 43, a bus slave control circuit 44, a multiplexer 45, An address comparison circuit 46 and a timing control circuit 47 are included.

Next, in the block diagram of FIG. 2, the internal operation of each unit when a read command is output from the CPU 30 to the memory 40 will be described in detail with reference to the timing chart of FIG. Note that the CPU 30 as the external master unit sends the bus master unit 9 address data ADD for designating the memory 40 as the external slave unit connected to the bus slave unit 6, and the write command and read to the memory 40. Command data CMD for sending a command, and when the command data CMD includes a write command, write data to be written to the memory 40 by the write command and a transfer request signal Mreq for requesting the bus master unit 9 to transfer these data. Output. However, as shown in FIG. 12, the command data CMD includes a bit indicating whether it is a read access or a write access, and the amount of data transferred at one time includes the size indicated in bytes. .

The CPU 30 outputs an address ADD, command data CMD indicating a read command, and a transfer request signal Mreq to the bus master unit 9. The address ADD and command data CMD output from the CPU 30 are respectively held in the bus address buffer 31A and the bus command buffer 31B of the bus master unit 9, and the timing control circuit 38 that receives the transfer request signal Mreq controls the transfer start signal by the bus master control. Output to the circuit 34. (The timing so far is not shown.)

The bus master control circuit 34 that has received the transfer start signal outputs an arbitration request signal Mreq to the arbitration circuit 12 in order to obtain a bus right. The arbitration circuit 12 performs arbitration in response to the received arbitration request signal Mareq, confirms that the Frame32 signal is inactive (indicated by a circle on the Frame32 signal in FIG. 6), and then performs the arbitration grant signal Magrnt. A signal is output to give the bus master unit 9 the bus right for the bus 1 and the bus 2. Since the arbitration operation of the arbitration circuit 12 is generally well known, the description thereof is omitted. The bus master control circuit 34 that has received the arbitration grant signal Magrnt outputs an active Frame 32 signal and a Master signal to the bus control line, and outputs a read selection signal.

The multiplexers 35A, 35B, 35C, and 36 output DID data, address data ADD, and command data CMD to the bus DID line, bus address line, and bus command line, respectively, in response to the read selection signal. It is assumed that the DID is supplied from the outside of the bus master unit 9. Address data ADD, command data CMD, DID data, and an active Master signal output to the bus 2 are transmitted to the bus 1 via the common control command bus 50. The data conversion unit 3 in FIG. 2 connected between the bus 1 and the bus 2 outputs the Frame 32 signal of the bus 2 to the bus 1 as a Frame 64 signal by the timing control unit 22. The Bus 32 and the Bus 1 can be occupied simultaneously by the Frame 32 signal and the Frame 64 signal. That is, the bus 1 and the bus 2 having different bus widths can be occupied by one arbitration by the arbitration circuit 12.

The bus slave unit 6 of FIG. 5 connected to the bus 1 compares the address data ADD on the bus 1 with an address comparator 46 to determine whether it is within the address range indicated by the map address line. When the address data ADD is within the address range indicated by the map address line, the address comparator 46 outputs a coincidence signal to the bus slave control circuit 44 and indicates a Devsel signal indicating that the device has been selected. To the bus control line. The bus slave control circuit 44 outputs a write permission signal in response to the coincidence signal. The bus slave control circuit 44 determines whether or not the memory 40 can execute the process requested by the command data CMD in response to the coincidence signal. If there is, the Nack signal is output. Here, the slave control circuit 44 outputs an Ack signal on the assumption that the memory 40 can execute the command.

The Ack signal is supplied to the timing control unit 22 of the data conversion unit 3 via the bus control line and the bus 2 in the 64-bit control command line, and the bus master via the bus control line and the bus 1 in the 32-bit control command line. It is supplied to the bus master control circuit 34 of the unit 9. Here, since the case of split transfer is assumed, the bus master control circuit 34 inactivates the Frame 32 signal in response to the input Ack signal and supplies a completion signal to the timing control circuit 38. The timing control circuit 38 that has received the completion signal outputs a completion signal MCmdAck to the CPU 30. At this time, the Frame 64 signal is also made inactive in response to the Frame 32 becoming inactive. In this way, the bus 1 and the bus 2 are released from the occupation.

The bus slave control circuit 44 of the bus slave unit 6 outputs a Devsel signal and an Ack signal and outputs a transfer start signal to the timing control circuit 47. The command data, address data, and DID data written to the bus command buffers 41A to 41C in response to the write permission signal output from the bus slave control circuit 44 are sent from the timing control circuit 47 in response to the transfer start signal. It is supplied to the memory 40 together with a transfer request signal to be output. When the command data (read command) is supplied to the memory 40 and the read data in the memory 40 is ready, the memory 40 supplies the read data to the bus read data buffer 43 and controls the completion signal with timing. Output to the circuit 47. The timing control circuit 47 outputs a read data transfer start signal to the bus slave control circuit 44 in response to the completion signal.

The bus slave control circuit 44 that has received the read data transfer start signal outputs an arbitration request signal Sareq to the arbitration circuit 12 in order to obtain the right to occupy the bus. The arbitration circuit 12 performs arbitration in response to the arbitration request signal Sareq, and outputs an arbitration grant signal Sagrnt signal. The bus slave control circuit outputs an active Frame 64 signal indicating the occupation of the bus 1 in response to the arbitration grant signal Sagnt signal. The Frame 64 signal on the bus 1 becomes the Frame 32 signal of the bus 2 via the timing control unit 22 of the data conversion unit 3 in the same manner as the Frame 32 signal output by the bus master unit 9. The bus slave control circuit 44 outputs command data CMD and DID data for specifying the master together with the Frame 64 signal.

Command data and DID data are sent from the bus 1 to the bus 2 via the common control command bus. The bus master control circuit 34 connected to the bus 2 outputs a comparison signal when the Master signal is inactive, and the DID comparison circuit 37 is activated by the comparison signal. Therefore, the DID comparison circuit 37 compares the DID data on the bus DID line of the bus 1 with the DID value of the bus master unit. When the DID comparison circuit 37 outputs a coincidence signal, the bus master control circuit 34 outputs an Ack signal to the bus control line of the bus 1.

The bus slave control circuit 44 that has received the Ack signal on the bus control line via the common control command bus and the bus 2 outputs a read permission signal and also outputs a Dvalid64 signal indicating that the data on the 64-bit data line is valid. Activate. The multiplexer 45 sequentially outputs the read data RD0 to RD3 written in the bus read data buffer 43 to the 64-bit bus read data line in response to the read permission signal.

The data conversion unit 3 receives the read data RD0 to RD3 having a 64-bit width via the 64-bit data line of the bus 1 and writes the read data to the 64-bit data buffer via the multiplexers 23 and 24. At this time, the 64-bit read data is divided into upper 32-bit read data and lower 32-bit read data corresponding to the multiplexers 23 and 24, and written into the data buffer 21 by a write selection signal from the timing control unit. I'm stuck. The written 64-bit read data is sequentially read as 32-bit read data corresponding to the 32-bit output selection signal from the timing control unit 22. At this time, the timing control unit 22 outputs a 32-bit output selection signal and activates Dvalid32 indicating that the 32-bit data RD0 to RD7 are valid.

Here, it is assumed that the timing control unit 22 controls bit conversion corresponding to which bus the Frame signal and the Ack signal are sent from. That is, when the timing control unit 22 receives the Frame 32 signal and receives the Ack signal from the 64-bit control command line, the timing control unit 22 receives the Frame 64 signal from the 32-bit control command line and conversely receives the Ack signal from the 32-bit control command line. When received, control is performed to convert from 64 bits to 32 bits. When the timing control unit 22 receives the Frame signal and the Ack signal from the same direction, it indicates that the master side and the slave side have the same data width, so the data conversion unit 3 performs conversion. Don't do it. As described above, when the conversion is unnecessary, the data conversion unit 3 is not operated, so that the power consumption can be reduced.

In response to the end of the output of the read data, the bus slave control circuit 44 inactivates the Dvalid64 signal and inactivates the Frame 64. However, in this embodiment, since the number of data is known in advance, the Frame 64 is inactivated one clock earlier than the Dvalid 64 signal in order to improve the usage efficiency of the bus 1. The bus master control circuit 34 outputs a write permission signal to the bus read data buffer 33 because the DID comparison circuit 37 outputs a match signal and the Dvalid 32 signal is active. In response to the write permission signal, the bus read data buffer 33 sequentially fetches 32-bit read data on the bus read data line of the bus 2 and supplies it to the CPU 30 as read data.

The timing control unit 22 of the data conversion unit 3 activates the Dvalid32 signal for a period corresponding to the number of data and inactivates the Frame32 signal corresponding to the last data. However, in this embodiment, in order to improve the usage efficiency of the bus 2, the Frame 32 is made inactive one clock earlier than the Dvalid 32 signal. In this way, a read command for the memory 40 having a 64-bit data width is executed from the CPU 30 having a 32-bit data width.

Next, when a read command is executed from an external master unit having a 64-bit data width connected to the bus master unit 4 to an external slave unit having a 32-bit data width connected to the bus slave unit 10, FIG. This will be described with reference to FIG. After the external master unit outputs the address data ADD, the command data CMD, and the transfer request signal Mreq to the bus master unit 4 having a 64-bit data width, the bus slave unit 10 having a 32-bit data width becomes the bus master unit. The operation of sending CMD and DID to 4 and the bus master unit 4 outputting the Ack signal is substantially the same as the timing described in FIG.

The bus slave control circuit 44 that has received the Ack signal output from the bus master unit 4 on the bus 1 via the common control command bus and the bus 2 outputs a read permission signal and indicates that the data is valid Dvalid 32 Activate the signal. The multiplexer 45 sequentially outputs the read data RD0 to RD7 written in the bus read data buffer 43 to the 32-bit bus read data line in response to the read permission signal.

The data conversion unit 3 receives the read data RD0 to RD7 having a 32-bit width via the 32-bit data line, and writes it into the data buffer 21 via the multiplexers 23 and 24. At this time, since the multiplexers 23 and 24 are alternately activated in response to the write selection signal from the timing control unit 22, the 32-bit read data is converted into the upper 32 bits and the lower 32 bits of the data buffer 21. The data is written alternately (whether the upper bit or lower bit of the data buffer is written in order can be changed according to the design). The written 32-bit read data is read as 64-bit read data corresponding to the 64-bit output selection signal from the timing control unit 22. At this time, the timing control unit 22 outputs a 64-bit output selection signal in response to receiving more than half of the 32-bit read data RD0 to RD7, that is, in response to receiving RD3, and 64 The Dvalid64 signal indicating that the bit data RD0 to RD3 are valid is activated.

In response to the end of the output of the read data, the bus slave control circuit 44 inactivates the Dvalid32 signal and inactivates the Frame32 signal. However, in this embodiment, since the number of data is known in advance, the Frame 64 is inactivated one clock earlier than the Dvalid 64 signal in order to improve the usage efficiency of the bus 1. The bus master control circuit 34 outputs a write permission signal to the bus read data buffer 33 because the DID comparison circuit 37 outputs a match signal and the Dvalid 64 signal is active. In response to the write permission signal, the bus read data buffer 33 sequentially fetches 64-bit read data on the bus read data line of the bus 2 and supplies it to the CPU 30 as read data.

The timing control unit 22 of the data conversion unit 3 activates the Dvalid64 signal for a period corresponding to the number of data and inactivates the Frame64 signal corresponding to the last data. However, in this embodiment, the Frame 64 is made inactive one clock earlier than the Dvalid 64 signal in order to improve the usage efficiency of the bus 1. In this way, a read command is executed from an external master unit having a data width of 64 bits to an external slave unit having a data width of 32 bits.

Next, a write command from an external master unit (not shown) having a data width of 64 bits connected to the bus master unit 4 to an external slave unit (not shown) having a data width of 32 bits connected to the bus slave unit 10 Will be described with reference to FIG.

When a write command is executed, write data Data 64, address data ADD, and command data CMD are sent from the external master unit to the bus master unit 4. At this time, the bus master unit 4 outputs the address data ADD, command data CMD, and DID data to the bus slave unit 10, and the operation until the bus slave unit 10 returns the Devsel and Ack signals is read command. Since the timing is substantially the same as the timing of FIG. 6 and FIG. Therefore, the description will be made from the point where the bus slave unit 10 returns the Ack signal.

When the bus master control circuit 34 of the bus master unit 4 receives the Ack signal output from the bus slave unit 10 via the bus control line, the bus master control circuit 34 outputs a read selection signal to the multiplexer 36. In response to the read selection signal, the multiplexer 36 outputs 64-bit write data WD0 to WD3 held in the bus write data buffer 32 to the bus write data line, and Dvalid64 indicating that these data are valid. The signal is output to the 64-bit data valid line. Further, the bus master control circuit 34 inactivates the Frame 64 signal and the Master signal in response to the completion of the data transfer. However, in this example, in order to improve the usage efficiency of the bus 1, the Frame 64 and Master signals are made inactive one clock earlier than the Dvalid 64 signal.

The write data WD0 to WD3 and the Dvalid64 signal are supplied to the data conversion unit 3 via the bus 1. The 64-bit write data WD0 to WD3 are supplied to the multiplexers 23 and 24 via the 64-bit data line, and are written in the data buffer 21 in response to the write selection signal of the timing control unit 22. This write operation is executed by the timing control unit 22 and the multiplexers 23 and 24 in the same manner as when 64-bit data is written to the data buffer by executing a read command. Further, in order to output the write data WD0 to WD3 written in the data buffer 21 to the bus 2, the timing control unit 22 outputs a 32-bit output selection signal to the multiplexer 26 in response to the Dvalid64 signal and outputs the 32-bit data. The 32-bit write data WD0 to WD7 are sequentially output to the data line, and the Dvalid32 signal is output to the 32-bit data valid signal line.

Since it is known that the bus slave control circuit 44 of the bus slave unit 10 is selected by the address data ADD, a write permission signal and a transfer start signal are sent to the bus write data buffer 42 in response to the Dvalid32 signal. Is output. The bus write data buffer 42 holds the write data WD0 to WD7 on the bus write data line in response to the write permission signal. The bus slave control circuit 44 inactivates the Dvalid32 signal and the Frame32 signal in response to receiving all the write data WD0 to WD7. However, in this embodiment, in order to improve the usage efficiency of the bus 2, the Frame 32 is made inactive one clock earlier than the Dvalid 32 signal.

On the other hand, the timing control circuit 47 that has received the transfer start signal outputs a transfer request to the external slave unit. In response to the transfer request, the external slave unit receives command data CMD, address data ADD, DID data, and write data WD0 to WD7, and executes writing based on the command data CMD. In this way, a write command is executed from an external master unit having a data width of 64 bits to an external slave unit having a data width of 32 bits.

In contrast to the case where the write command is executed from the external master unit having the data width of 64 bits to the external slave unit having the data width of 32 bits, 64 bits from the external master unit having the data width of 32 bits is executed. When a write command to an external slave unit having a data width of 64 bits is executed, as shown in FIG. 9, 64-bit write data is received until more than half of 32-bit write data WD0 to WD7 is received from the bus master unit. The above-described write command is executed except that the output of WD0 to WD3 and the output of Dvalid64 are waited and the timing control unit 22 of the data conversion unit 3 controls the data conversion to be reversed. The description is omitted for the same reason. The data conversion method is already described when the above-described read command is executed, and thus the description thereof is omitted.

As described above, in the bus connection circuit of this embodiment, the read data bus and the write data bus are common, and when split transfer is performed, arbitration of the bus right between buses is unnecessary, and the data Therefore, the number of clock cycles in read access and write access can be reduced.

Further, in response to receiving the Ack signal from the transmission destination (for example, memory), the transmission source (for example, CPU) releases the bus right of the bus to which the transmission source is connected. Therefore, data transfer from the transmission source to the transmission destination is performed within the same bus cycle. For this reason, even when a data transfer error occurs, data is not lost because data is stored at the transmission source until the bus cycle is completed. When a data transfer error to the transmission destination occurs, a data transfer error to the transmission source occurs when the transmission destination sends a NACK signal between the bus 1 and the bus 2 via the common control command bus. Can be notified.

Furthermore, it is only necessary to prepare the hardware that performs data conversion by extracting the conditions that require data conversion, and it is not necessary to analyze the control commands completely, so the circuit configuration is simplified and the necessary hardware is The amount can be reduced. In the bus control circuit of this example, the delay is reduced because the number of bus arbitrations is small. Therefore, the period of occupying the bus is shortened, and as a result, the throughput of the bus can be improved. Although the DID comparison circuit is included in the bus master unit, it may be provided outside the bus master unit.

As described above, in the first embodiment, the case of performing split transfer has been described. Hereinafter, the case of performing non-split transfer will be described.

Second Embodiment FIG. 10 is a block diagram showing the configuration of a bus system according to the second embodiment of the present invention, and FIG. 11 shows a read access from a 32-bit bus master to a 64-bit slave unit in this embodiment. FIG. 12 is a timing chart showing the data transfer operation. FIG. 12 is a diagram showing an outline of commands in this embodiment.

As a second embodiment of the present invention, a bus system for non-split transfer will be described with reference to FIG. In non-split transfer, the bus master unit occupies the bus until the bus slave unit performs processing and returns data to the bus master unit after the command is output from the bus master unit, so the bus master unit does not require DID data. No arbitration is required. Therefore, the bus slave unit and the arbitration circuit of the second embodiment are different from those of the first embodiment in that they do not have an arbitration request line and an arbitration grant line for connecting them. Constituent elements that are the same as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

Hereinafter, an operation when an external master unit having a 32-bit data width connected to the bus master unit 8 outputs a read command to an external slave unit having a 64-bit data width connected to the bus slave unit 6A. This will be described with reference to FIGS. 10 and 11. The external master unit outputs address data ADD, command data CMD, and transfer request signal Mreq to the bus master unit having a 32-bit data width, and then the bus slave unit 6A having a 64-bit data width is used as the bus master unit. The operations until the Devsel signal and the Ack signal are output to the unit 8 are substantially the same as the timing in FIG. Further, the bus slave unit of FIG. 10 is substantially the same as the bus slave unit of FIG. 5 except that the bus DID buffer 41C and the bus slave control circuit 44 do not perform operations related to acquiring the bus right with respect to the arbitration circuit 12. Therefore, description will be made with reference to FIG.

The bus slave control circuit 44 of the bus slave unit 6A outputs a transfer start signal together with the Devsel signal and the Ack signal. The external slave unit executes processing in response to the transfer start signal, address data ADD, and command data CMD, and outputs read data RD0 to RD3 to the bus slave unit 6A. The bus slave unit 6A that has received the read data RD0 to RD3 outputs the read data RD0 to RD3 to the data conversion unit 3 via the bus read data line in the bus 2 and outputs a Dvalid64 signal to the bus control line. Further, the bus slave unit 6A makes the Dvalid64 signal inactive when the output of the read data is completed.

The data conversion unit 3 receives the Dvalid64 signal and the read data RD0 to RD3, outputs a Dvalid32 signal in response to the Dvalid64 signal, and converts the 64-bit read data RD0 to RD3 into 32-bit read data RD0 to RD. Output. At this time, the timing control unit 22 of the data conversion unit 3 inactivates the Dvalid32 signal in response to the end of the output of the 32-bit read data RD0 to RD7. The bus master control circuit 34 of the bus master unit 8 that has received the 32-bit read data RD0 to RD7 inactivates the Frame signal in response to the completion of the reception of the read data RD0 to RD7, and releases the bus 1. However, in this embodiment, since the data size is known in advance, the Frame signal is made inactive and the bus is released one clock before reception ends.

The operation in each unit is the same as the description at the time of executing the read command by the split transfer described in the first embodiment except for the operation unique to the split transfer. When non-split transfer is executed between buses having different bus widths as described above, one arbitration circuit is provided for two buses, and both bus rights can be obtained by a single arbitration request from the bus master unit.

Thus, in the bus connection circuit of the present embodiment, the read data bus and the write data bus are common, and when performing non-split transfer, arbitration of the bus right when crossing between buses is unnecessary, Since only data conversion needs to be performed, the number of clock cycles in read access and write access can be reduced. In this embodiment as well, data loss does not occur at the transmission source when a data transfer error occurs, and a data transfer error occurrence notification to the transmission source is possible as in the case of the first embodiment.

Furthermore, it is not necessary to control the command control signal in detail as in the conventional bus master control circuit and bus slave control circuit, and only hardware that extracts the conditions that require data conversion and performs data conversion is prepared. Since it is good, the circuit configuration is simplified, and the amount of necessary hardware can be reduced. The bus connection circuit of this example has a smaller amount of hardware on the slave side than the split transfer method, but the period of occupying the bus becomes longer, so the throughput is lower than that of the first embodiment. . However, the throughput is improved as compared with the case of non-split transfer using a bus bridge circuit as in the conventional example.

◇ Explanation of Flowchart FIG. 13 is a flowchart showing a flow of processing from bus right arbitration to bus use in the bus connection circuit of this embodiment, and FIG. 14 is data at the time of split transfer in the bus system of this embodiment. FIG. 15 is a flowchart for explaining the processing procedure of the data conversion unit at the time of split transfer in the bus system of the present embodiment. FIG. 16 is a flowchart for explaining the processing procedure of the conversion unit. FIG. 17 is a flowchart showing the processing of the bus master unit including the bus arbitration operation in the bus system according to the present embodiment. FIG. 18 is the flowchart showing the processing of the bus master unit including the arbitration operation of the right. Of bus slave units, including bus arbitration Flowchart showing a sense, FIG. 19, in the bus system of the present embodiment includes an arbitration operation of the bus right is a flowchart showing the processing of the bus slave units.

Next, with reference to the flowchart shown in FIG. 13, the flow of processing from arbitration of the bus right to use of the bus in the bus connection circuit of this example will be described. As shown in the system configuration diagram of FIG. 2, an arbitration request line and an arbitration grant line are connected from the arbitration circuit 12 to all bus master units and bus slave units. The arbitration request line is used when the bus master unit wants to start transfer. The arbitration grant line is output by the arbitration circuit when bus arbitration is established, and only one of the plurality of arbitration grant lines is activated. When a plurality of arbitration request lines are activated at the same time, arbitration is performed in consideration of the priority. Therefore, only the arbitration grant line for any one bus master unit is activated.

When a transfer request is generated from an external circuit (external master unit) and a transfer start signal is output to the bus master control circuit (bus master unit) (step S11), the arbitration grant connected to the bus master control circuit It is checked whether or not the line is in an active state (step S12). When the arbitration grant line is not in the active state, the arbitration request line is activated (step S13) and waits for the corresponding arbitration grant line to be in the active state.

When the arbitration grant line becomes active, it is checked whether the bus frame signal (Frame 64 or Frame 32) is active on the bus (step S14). When the arbitration grant line is active, the bus is in use. Wait until the signal becomes inactive (step S15). When the bus frame signal becomes inactive, transfer is started because the bus is available (step S16). At the end of transfer, the bus right is made inactive and the bus frame signal is made inactive. It is opened (step S17) and returns to the initial state.

Next, the processing procedure of the data conversion unit 3 during split transfer in the bus connection circuit of FIG. 1 will be described with reference to the flowcharts shown in FIGS.

(1) Frame32 output from the bus master unit to the 32-bit bus is activated in the state where the bus right is granted as a result of arbitration during read access from the 32-bit bus master unit to the 64-bit bus slave unit. (Step S111), it is a transfer from the bus master unit to the bus slave unit (Step S112), and at the time of read access (Step S113), the data conversion unit does not need to process data in the read command transmission. Frame 32 is made inactive and waits until the bus cycle is completed (step S110).

When Frame 64 output from the bus slave unit to the 64-bit bus is activated due to the read data being prepared in the bus slave unit (step S101), the valid period of the read data from the bus slave unit is indicated. Wait until Dvalid 64 is activated (step S105), and receive Data 64 from the bus slave unit while Dvalid 64 is active (step S106).

Then, while receiving 64-bit data from the bus slave unit, Dvalid 32 to the 32-bit bus is activated, and the received Data 64 is output to the 32-bit bus as Data 32 in half (step S107). After that, even when the data transfer from the bus slave unit is completed and Frame 64 is made inactive on the 64-bit side bus, Frame 32 is kept active on the 32-bit side bus (step S108). Finally, the bus slave unit When there is no more data received from, Frame 32 is made inactive and the bus cycle is terminated (step S109).

(2) Frame64 output from the bus master unit to the 64-bit bus is activated in the state where the bus right is granted as a result of arbitration during read access from the 64-bit bus master unit to the 32-bit bus slave unit. If this is the case (step S101), it is a transfer from the bus master unit to the bus slave unit (step S102), and in the case of read access (step S103), the data conversion unit does not need to process data, so Frame 64 Is made inactive and waits until the bus cycle is completed (step S110).

When Frame 32 output from the bus slave unit to the 32-bit bus is activated (step S111) because the read data is ready in the bus slave unit, the valid period of the read data from the bus slave unit is increased. Wait until the Dvalid 32 shown is activated (step S115), and receive the Data32 from the bus slave unit while the Dvalid32 is active (step S116).

Then, it waits until data of half or more of the transfer size is received (step S117), activates Dvalid64 to the 64-bit side bus, combines Data32 data twice, and sends it as Data64 to the 64-bit side bus. Output (step S118). At this time, which of the two times of data is higher in the 64-bit data depends on the addressing mode determined by the system, which is the higher or lower of the 64-bit data counted as a higher address. Thereafter, even if the data transfer from the bus slave unit is completed and Frame 32 is made inactive on the 32-bit bus, Frame 64 is kept active on the 64-bit bus (step S119). Finally, the bus slave unit When there is no more data received from, Frame 64 is made inactive and the bus cycle is terminated (step S120).

(3) Frame32 is activated on the 32-bit side bus from the bus master unit in the state where the bus right is granted as a result of arbitration during write access from the 32-bit bus master unit to the 64-bit bus slave unit ( In step S111), when the transfer is from the bus master unit to the bus slave unit (step S112) and not a read access (step S113), Devsel output from the 64-bit bus slave unit is activated, and 64 When the bit side ACK is active (step S114), the data conversion unit waits for the Dvalid32 output from the bus master unit to become active (step S115).

Then, while Dvalid32 is active, the data conversion unit receives Data32 from the bus master unit (step S116) and waits until data of more than half the transfer size is received (step S117). Thereafter, Dvalid 64 is activated on the 64-bit bus, the data 32 is combined twice, and is output as Data 64 to the bus slave unit (step S118). Even if Frame 32 is inactivated in the 32-bit bus, Frame 64 is kept active in the 64-bit bus (step S119). Finally, when there is no received data, Frame 64 is inactivated. The bus cycle is terminated (step S120).

(4) Frame64 output from the bus master unit to the 64-bit bus is activated in the state where the bus right is granted as a result of arbitration during write access from the 64-bit bus master unit to the 32-bit bus slave unit. When it is a transfer from the bus master unit to the bus slave unit (step S102) and not a read access (step S103), Devsel output from the 32-bit bus slave unit becomes active. When the 32-bit ACK is active (step S104), the data conversion unit waits for the Dvalid 64 output from the bus master unit to become active (step S105).

While Dvalid64 is active, the data conversion unit receives Data64 from the bus master unit (step S106), activates Dvalid32 output to the 32-bit side bus, and divides the data of Data64 by half. To the bus slave unit (step S107). After that, even if Frame 64 output on the 64-bit side bus is made inactive, Frame 32 is kept active on the 32-bit side bus (step S108). Finally, when there is no received data, Frame 32 is made inactive. Then, the bus cycle is finished (step S109).

Next, the flow of processing of the bus master unit and the bus slave unit including arbitration of the bus right in the bus connection circuit of FIG. 1 will be described with reference to the flowcharts of FIGS. Note that these flowcharts show processing during split transfer operation.

16 and 17 are flowcharts showing the processing of the bus master unit including the bus right arbitration operation.
(1) Bus master unit command and write data transfer operation When a transfer request is generated from the external master unit, the command and address are received, and in the case of write access, the write data is also received and stored in the buffer ( Step S201). Next, when a transfer start signal is output to the bus master control circuit (step S202), the bus master control circuit requests arbitration of the bus right from the arbitration circuit to acquire the bus right, and the bus becomes unused. The bus command is output (step S203).

Then, it is checked whether Devsel is returned from the bus slave unit (step S204). If it is not returned, it is a bus error, so the processing is terminated and the process returns to the initial state (step S205). On the other hand, when Devsel is returned, it is checked whether or not an ACK indicating permission to transmit data has been returned (step S206). If not returned, a bus error has occurred, so the processing is terminated and the initial state is restored (step S205). ).

When ACK is returned, it is checked whether or not the access is a write access (step S207). When the access is not a write access, the bus cycle is completed, and the bus is released to return to the initial state (step S208). If it is a write access, the write data is output to the bus (step S209), a transfer completion signal is output to the external master unit that has made the transfer request (step S210), and the bus cycle is completed. Open and return to the initial state (step S208).

(2) Receiving operation of read data of the bus master unit In the case of read access, when the DID is the same as the DID of the bus master unit in the access issued by the bus slave unit on the bus (step S211), After the read data is received and passed to the requesting external master unit (step S212), a transfer completion signal is output to the external master unit (step S213), and the initial state is restored (step S214). )

FIG. 18 and FIG. 19 are flowcharts showing the processing of the bus slave unit including the bus right arbitration operation.
(1) Bus slave unit command and write data reception operation When an address falls within the address range of the bus slave unit in an access issued by the bus master unit on the bus (step S301), the bus slave unit is on the bus. Is received and Devsel is output to the bus (step S302).

Then, it is checked whether or not the command can be received (step S303). If the command is not received, a NACK indicating that transmission is impossible is output on the bus and the process returns to the initial state (step S304). On the other hand, when the command can be received, it is checked whether or not the command is acceptable (step S305). When the command is not acceptable, NACK is output on the bus and the initial state is returned (step S304). ). If the command is acceptable, ACK indicating transmission permission is output on the bus (step S306), a transfer request signal is output to the external slave unit to which write data is to be output, and the command, address, DID is output. Etc. are transferred (step S307).

Next, it is checked whether or not it is a write access (step S308). If it is not a write access, it returns to the initial state (step S309). If it is a write access, the write data is received (step S310). When the data is transferred to the unit and the transfer is completed, a transfer completion signal is output to the external slave unit (step S311), and the process returns to the initial state (step S312).

(2) Read data transfer operation of the bus slave unit When a read data transfer request is generated from the external slave unit and a command and DID are received (step S313), a transfer start signal is output to the bus slave control circuit ( Step S314). The bus slave control circuit requests the bus right from the arbitration circuit and acquires the bus right. When the bus becomes unused, the bus slave control circuit outputs a DID, a command, and read data (step S315), and also to the external slave unit. Outputs a transfer completion signal (step S316) and returns to the initial state (step S317).

FIG. 20 is a diagram illustrating a bus configuration using a multiplexer, and FIG. 21 illustrates a multiplexer-type bus configuration when transmitting signals output from both the bus master unit and the bus slave unit. FIG. 22 is a diagram for explaining a configuration of a multiplexer-type bus when a signal output only from the bus master unit is transmitted, and FIG. 23 is a multiplexer-type bus when a signal output only from the bus slave unit is transmitted. FIG. 24 is a diagram illustrating the configuration of a bus using a three-state buffer, and FIG. 25 is a configuration of a three-state buffer bus when both the bus master unit and the bus slave unit output signals. FIG. 26 is a diagram for explaining only the bus master unit. FIG, 27 illustrating the third bus state buffer format structure in the case of force is a diagram illustrating a third bus state buffer format structure in the case where only the bus slave unit outputs a signal.

Next, the case of a bus using a multiplexer will be described as an example of the bus configuration in the bus connection circuit shown in FIG. As shown in FIG. 20, the bus using the multiplexer in the bus connection circuit of FIG. 1 includes a data conversion unit 3, 64-bit bus master units 4, 5, 64-bit bus slave units 6, 7, A configuration in which the bus 1 is formed via the multiplexers 51 to 54 and the bus 2 is formed via the multiplexers 55 to 58 between the 32-bit bus master units 8 and 9 and the 32-bit bus slave units 10 and 11 have.

The multiplexer 51 switches the 64-bit width signal from the bus master units 4 and 5 and connects it to the multiplexer 54 and the data conversion unit 3. The multiplexer 52 switches the 64-bit width signals from the multiplexer 53 and the data conversion unit 3 and connects them to the bus master units 4 and 5. The multiplexer 53 switches the 64-bit width signal from the bus slave units 6 and 7 and connects it to the multiplexer 52 and the data conversion unit 3. The multiplexer 54 switches the 64-bit width signals from the multiplexer 51 and the data conversion unit 3 and connects them to the bus slave units 6 and 7.

The multiplexer 55 switches the 32-bit width signal from the bus slave units 8 and 9 and connects it to the multiplexer 58 and the data conversion unit 3. The multiplexer 56 switches the 32-bit width signals from the multiplexer 57 and the data conversion unit 3 and connects them to the bus master units 8 and 9. The multiplexer 57 switches the 32-bit width signal from the bus slave units 10 and 11 and connects it to the multiplexer 56 and the data conversion unit 3. The multiplexer 58 switches the 32-bit width signals from the multiplexer 55 and the data conversion unit 3 and connects them to the bus slave units 10 and 11.

All the signals shown in FIG. 20 are omitted as signals output from either the bus master unit or the bus slave unit. The specific configuration of the multiplexer when both the bus master unit / bus slave unit, only the bus master unit, or only the bus slave unit outputs signals will be described below with reference to FIGS. Note that the bus 1 and the bus 2 are configured by a combination of these three types of multiplexer structures.

With reference to FIG. 21, a description will be given of the configuration of the bus in the case where a signal that is commonly output by the bus master unit and the bus slave unit, for example, a Frame signal, is transmitted. The bus 1101 for transmitting such a signal can be configured by multiplexers X1 and X2 and an OR circuit O1. Note that the multiplexers 51 and 53 in FIG. 20 correspond to the multiplexer X1, and the multiplexers 52 and 54 correspond to the multiplexer X2. The operation will be described below.

When the bus master units M1 and M2 and the bus slave units S1 and S2 output the Frame 64_O signal as a frame signal in response to the grant signal from the arbitration circuit, they simultaneously output an enable signal (Frame 64_OE signal). Here, the Frame 64_OE signal is a signal indicating a period during which the corresponding Frame 64_O signal is valid. As a result, the 4: 1 multiplexer X1 selects and outputs only one of the valid Frame 64_O signals. This Frame 64_O signal is connected to the data conversion unit as a Frame 64_I signal indicating the input of the frame signal.

Further, when a frame signal is supplied from the outside of the bus 1101 (for example, when a frame signal is supplied from the data conversion unit), in the 2: 1 multiplexer X2, if the Frame64_OE signal is active HI, the OR circuit O1 The frame 64_O signal selected by the multiplexer X1 and the frame 64_O selected from the data conversion unit by the signal obtained by taking the OR of the frame 64_OE signal of the bus master units M1 and M2 and the bus slave units S1 and S2 and the frame 64_OE signal from the data conversion unit. The selected frame 64_O signal as a frame 64_I signal indicating the input of the frame signal and commonly connected to the bus master units M1 and M2 and the bus slave units S1 and S2. That.

Therefore, when any of the bus master units M1 and M2, the bus slave units S1 and S2, and the data conversion unit outputs the Frame 64_O signal, the input of all the bus master units / bus slave units is performed as the Frame 64_I signal indicating the input of the frame signal. Connected to terminal and data conversion unit.

With reference to FIG. 22, a description will be given of the configuration of the bus in the case of transmitting a signal output from only the bus master unit, for example, an address signal, in the bus 1. The bus 1102 for transmitting such a signal includes multiplexers X3 and X4 and an OR circuit O2. The operation will be described below. For example, when each of the bus master units M1 and M2 outputs an Addr_O signal as an address signal, it simultaneously outputs an Addr_OE signal indicating its valid period. As a result, the 2: 1 multiplexer X3 selects and outputs only one of the enabled Addr_O signals. The selected Addr_O signal is output to the common control command bus together with a signal obtained by ORing the Addr_OE signals of the bus master units M1 and M2 in the OR circuit O2.

Further, when Addr_O and Addr_OE are supplied from the outside of the bus 1102 (when supplied from the bus master unit on the bus 2 side), in the 2: 1 multiplexer X4, the OR circuit O2 performs an OR of the Addr_OE signal of the bus master units M1 and M2. The Addr_O signal selected by the multiplexer X3 and the Addr_O signal from the common control command bus are selected by the signal obtained from the common control command bus and the Addr_O signal from the common control command bus, and the selected Addr_O signal is input as an address. Are commonly connected to the bus slave units S1 and S2.

Therefore, when any of the bus master units M1 and M2 and the common control command bus outputs the Addr_O signal, it is connected to the input terminals of all the bus slave units and the common control command bus as the Addr_I signal indicating the input of the address signal. Is done.

Next, the configuration of the bus in the case where the bus 1 transmits a signal output only by the bus slave unit, for example, an Ack signal will be described with reference to FIG. The bus 1103 for transmitting such a signal includes multiplexers X5 and X6 and an OR circuit O3. The operation will be described below. For example, when each of the bus slave units S1 and S2 outputs an ACK_O signal as a transmission permission signal, each outputs an ACK_OE signal indicating the valid period thereof. As a result, the 2: 1 multiplexer X5 selects and outputs only one of the valid ACK_O signals. The selected ACK_O signal is output to the common control command bus together with the signal obtained by taking the ACK_OE signal of the bus slave units S1 and S2 in the OR circuit O3, and further connected to the data conversion unit as an ACK_I signal indicating the input of ACK Is done.

Further, when Ack_O and Ack_OE are supplied from the outside of the bus 1103 (when supplied from the bus 2), in the 2: 1 multiplexer X6, the OR circuit O3 performs an OR of the ACK_OE signal of the bus slave units S1 and S2. The ACK_OE signal selected by the multiplexer X3 and the ACK_O signal from the common control command bus are selected based on the signal obtained from the common control command bus and the ACK_OE signal from the common control command bus. As the ACK_I signal shown, it is commonly connected to the bus master units M1 and M2.

Therefore, when either of the bus slave units S1 and S2 and the common control command bus outputs the ACK_O signal, it is connected to the input terminals of all the bus master units and the common control command bus as the ACK_I signal indicating the input of the ACK signal. Is done.

The bus configuration by the multiplexer only needs to control the wiring that becomes the data transfer path delimited by the multiplexer, and it is not necessary to control long wires collectively as in the bus configuration by the three-state buffer, so the wiring capacity is reduced. Therefore, there is an advantage that a repeater (driving buffer: not shown) for amplifying the signal can be easily inserted because the signal can be operated at a high frequency and all the signals are unidirectional. An advantage for the data conversion unit is that the 32-bit side signal line and the 64-bit side signal line are not the same. For this reason, even if the ACK signals indicate the same transmission permission, for example, the 32-bit side signal and the 64-bit side signal are different signals for the data conversion unit. be able to.

In the bus connection circuit of FIG. 1, a 3-state buffer can be used as a bus configuration instead of a multiplexer. In the following, the bus configuration in this case will be described.

As shown in FIG. 24, the bus using the 3-state buffer includes a data conversion unit 3, 64-bit bus master units 4 and 5, 64-bit bus slave units 6 and 7, and a 32-bit bus master unit 8. , 9 and the 32-bit bus slave units 10 and 11, the bus 1 is formed via the three-state buffers 61 to 68, and the bus 2 is formed via the three-state buffers 69 to 76. Have

When the 3-state buffer 61 is controlled to be turned on by the bus master unit 4, the output of the 64-bit bus master unit 4 is connected to the bus 1, and the buffer 62 connects the input from the bus 1 to the bus master unit 4. The relationship between the 3-state buffer 63, the buffer 64, and the 64-bit bus master unit 5 is the same. When the three-state buffer 65 is controlled to be turned on by the bus slave unit 6, the output of the 64-bit bus slave unit 6 is connected to the bus 1 and the input from the buffer 66 bus 1 is output to the bus slave unit 6. The relationship between the 3-state buffers 67 and 68 and the 64-bit bus slave unit 7 is the same.

When the 3-state buffer 69 is controlled to be turned on by the bus master unit 8, the output of the 32-bit bus master unit 8 is connected to the bus 2, and the buffer 70 is connected to the input from the bus 2 to the bus master unit 8. The relationship between the 3-state buffer 71, the buffer 72, and the 32-bit bus master unit 9 is the same. When the 3-state buffer 73 is controlled to turn on the bus slave unit 10, the output of the 32-bit bus slave unit 10 is connected to the bus 2, and the buffer 76 outputs the input from the bus 2 to the bus slave unit 10. . The relationship between the 3-state buffers 75 and 76 and the 32-bit bus slave unit 11 is the same.

In FIG. 24, the signal lines are displayed as signals that are input / output by all bus master units and bus slave units. However, in reality, there are cases in which signals are only input or output only. The specific configuration of the bus in the case where both the bus master unit / bus slave unit, only the bus master unit, or only the bus slave unit outputs signals will be described below with reference to FIGS.

In FIG. 25, the configuration of the bus for transmitting signals output from both the bus master unit and the bus slave unit, for example, the Frame signal, as in the bus configured by the multiplexer, will be described.

Such a bus 1201 includes three-state buffers B11, B12, B13, B14, and B15 and buffers B21, B22, B23, B24, and B25. The bus master units M11 and M12, the bus slave units S11 and S12, and the data conversion unit output the Frame64_OE signal simultaneously with the Frame64_O signal. The 3-state buffers B11, B12, B13, B14, and B15 output the Frame64_O signal from the corresponding unit only when the Frame64_OE signal becomes valid.

The Frame 64 signal is connected to the bus master units M11 and M12, the bus slave units S11 and S12, and the data conversion unit in common as a Frame 64_I signal indicating the input of the frame output through the buffers B21, B22, B23, B24, and B25, respectively. Is done. Therefore, when any of the bus master units M1 and M2, the bus slave units S1 and S2, and the data conversion unit outputs the Frame 64_O signal, all the bus master units / bus slave units and the frame 64_I signal indicating the input of the frame signal are displayed. Connected to the input terminal of the data conversion unit.

In FIG. 26, a configuration of a bus for transmitting a signal output only by the bus master unit, for example, an address signal will be described. The bus 1202 for transmitting such a signal is composed of 3-state buffers B31 to B34. Each of the bus master units M11 and M12 outputs an Addr_O signal and an Addr_OE signal as address signals. The 3-state buffers B31 and B32 output the Addr_O signal from the corresponding unit only when the Addr_OE signal becomes valid.

The Addr signal is output to the bus slave units S11 and S12 through the buffers B33 and B34 as an Addr_I signal indicating an address input, and also to the common control command bus. Therefore, when either of the bus master units M1 and M2 outputs the Addr_O signal, the Addr signal indicating the address is connected to the input terminals of all the bus slave units and also output to the common control command bus.

FIG. 27 illustrates a configuration of a bus that transmits a signal output only by the bus slave unit, for example, an Ack signal. The bus 1203 for transmitting such a signal includes buffers 41, 42, and 45 and 3-state buffers B43 and B44.

The bus slave units S11 and S12 output an ACK64_O signal and an ACK64_OE signal indicating transmission permission. Thus, the 3-state buffers B43 and B44 output the ACK64_O signal from the corresponding unit only when the ACK64_OE signal becomes valid. The ACK64 signal is output to the bus master units M11 and M12 as the ACK64_I signal indicating the input of ACK through the buffers B41 and B42, and is also output to the data conversion unit through the buffer B45. Therefore, when any of the bus slave units S11 and S12 outputs the ACK64_O signal, the ACK64 signal indicating transmission permission is connected to the input terminals of all the bus master units and the data conversion units.

In a bus configuration with a three-state buffer, it is difficult to insert a repeater because the signal direction of the wiring is bidirectional, and the capacitance of the three-state buffer connected to the wiring of the data transfer path is added, resulting in a large wiring capacity. Therefore, the operating frequency is generally low. A characteristic for the data conversion unit in the case of the 3-state buffer format is that a 32-bit side signal and a 64-bit side signal cannot be distinguished. For example, if the ACK signal is common to the 32-bit side and the 64-bit side, even if the 32-bit side outputs, for example, unlike the bus by the multiplexer, the ACK signal is also output to the 64-bit side. It cannot be distinguished whether it was output on the 32-bit side or on the 64-bit side. Therefore, it is necessary to distinguish between the 32-bit ACK signal and the 64-bit ACK signal. Such a signal that needs to be handled separately cannot be shared as a control command signal in a bus configuration with a three-state buffer.

FIG. 28 is a block diagram showing a configuration of a bus system according to a third embodiment of the present invention. FIG. 29 is a diagram showing a system configuration including a common control command bus of the bus system of this embodiment. FIG. 30 is a timing chart showing a data transfer operation when a write access is performed after a read access to a 64-bit bus slave unit from a 32-bit bus master unit in this embodiment. Hereinafter, in the third embodiment, a bus system in which the read bus and the write bus are separate and in the case of split transfer will be described.

In the bus system of this example, as shown in FIG. 28, a write to a first write bus 1W, a first read bus 1R, a second write bus 2W, and a second read bus 2R is performed. Data conversion unit 3W, read data conversion unit 3R, first write bus 1W, bus master units 4, 5 and bus slave units 6, 7 connected to first read bus 1R, and second write bus 2W And bus master units 8 and 9 and bus slave units 10 and 11 connected to the second read bus 2R, and arbitration circuits 12A and 12B.

The first write bus 1W has a data width of 64 bits, the second write bus 2W has a data width of 32 bits, and various write controls are mutually performed via a write control command bus. Commands can be transferred. The write data conversion unit 3W is connected between the first write bus 1W and the second write bus 2W, and converts the bit width between the 64-bit width data and the 32-bit width data. I do. The first read bus 1R has a data width of 64 bits, the second read bus 2R has a data width of 32 bits, and various read controls are mutually performed via a read control command bus. Commands can be transferred. The read data conversion unit 3R is connected between the first read bus 1R and the second read bus 2R, and performs mutual bit width conversion between 64-bit width data and 32-bit width data. Do.

The bus master units 4 and 5 are connected to the first write bus 1W by a write control command line and a 64-bit write data line, and are connected to the first read bus 1R by a read control command line and a 64-bit read data line. A function for interfacing commands and write data or read data between an external master unit such as a CPU or a DMA controller and the first write bus 1W or the first read bus 1R by adjusting the timing. have. The bus slave units 6 and 7 are connected to the first write bus 1W by a write control command line and a 64-bit write data line, and are connected to the first read bus 1R by a read control command line and a 64-bit read data line. The interface between the command and write data or read data is adjusted between the first write bus 1W or the first read bus 1R and an external slave unit such as I / O or memory by adjusting the timing. It has a function to take.

The bus master units 8 and 9 are connected to the second write bus 2W by a write control command line and a 32-bit write data line, and are connected to the second read bus 2R by a read control command line and a 32-bit read data line. A function for adjusting a timing and interfacing a command and write data or read data between an external master unit such as a CPU or a DMA controller and the second write bus 2W or the second read bus 2R. have. The bus slave units 10 and 11 are connected to the second write bus 2W by a write control command line and a 32-bit write data line, and connected to the second read bus 2R by a read control command line and a 32-bit read data line. The interface between the command and write data or read data is adjusted between the second write bus 2W or the second read bus 2R and an external slave unit such as I / O or memory by adjusting the timing. It has a function to take.

The arbitration circuit 12A arbitrates the bus right between the first write bus 1W and the second write bus 2W according to the arbitration request signal between the bus master units 4, 5 and 8, 9. When the bus right is established, it has a function of notifying the requesting bus master unit of the acquisition of the bus right by an arbitration grant signal. The arbitration circuit 12B performs arbitration of the bus right between the first read bus 1R and the second read bus 2R according to the arbitration request signal between the bus slave units 6, 7 and 10, 11. When the bus right is established, it has a function of notifying the requesting bus slave unit of the acquisition of the bus right by an arbitration grant signal.

As a bus configuration in the bus connection circuit of this example, a multiplexer type bus or a three-state buffer type bus can be used as in the case of the first embodiment shown in FIG. 5 to FIG. 8 or FIG. 22 to FIG. It is the same. In the bus connection circuit of this example, the processing flow from bus right arbitration to bus use is the same as in the first embodiment shown in FIG. The processing procedure of the write data conversion unit 3W or the read data conversion unit 3R at the time of read access or write access in the bus connection circuit of this example is the case of the first embodiment shown in FIGS. However, it differs from the first embodiment in that the operations of read access and write access can be executed independently.

The system configuration including the common control command bus of the bus connection circuit of this example is as shown in FIG. In FIG. 29, the same components as those in FIG. 28 are denoted by the same numbers, and (1) to (21) represent the signals of each control command line and each common control command bus, and (1) represents WFframe 64, ( 2) Address, (3) Cmd, (4) DID, (5) WData64, (6) WDvalid64, (7) ACK, (8) NACK, (9) Devsel, (10) Is RFframe64, (11) is RCmd, (12) is RDID, (13) is RACK, (14) is RData64, (15) is RDvalid64, (16) is WFframe32, (17) is WData32, (18) is WDvalid32 , (19) represents RFframe 32, (20) represents RData32, and (21) represents RDvalid32. Among these, those for write access are indicated with W, and those for read access are indicated with R.

Various commands used in the system configuration shown in FIG. 29 have almost the same contents as those shown in FIG. However, as compared with the case of the first embodiment, some control signals (for example, Master) are missing. Also, when the read data bus and the write data bus are separate, compared to the case where the buses are common, the read data transfer Frame signal, Data signal, Dvalid signal, Cmd signal, and DID signal during read data transfer Is different in that it is necessary.

Here, WFrame64 is information indicating occupation of a 64-bit bus by write access, Address is information for specifying a bus slave unit, Cmd is command information, DID is information for specifying a bus master unit, and WData64 Is the transfer data on the 64-bit width bus by write access, WDvalid64 is the information indicating the valid period of the data on the 64-bit width bus in write access, ACK is the operation requested by the selected unit NACK is information indicating that the selected unit is not in the requested operable state, Devsel is information indicating that the unit is selected, and RFframe 64 is read access. Indicates the occupation of a 64-bit wide bus by , RCmd is command information in read access, RDID is information for specifying the bus master unit in read access, RACK is information indicating that the unit selected in read access is requested, and RData64 is Transfer data on a 64-bit bus by read access and RDvalid64 indicate information indicating a period during which the data on the 64-bit bus is valid in read access.

Also, WFframe32 is information indicating occupation of a 32-bit bus by write access, WData32 is information indicating transfer data on a 32-bit bus by write access, and WDvalid32 is information on a 32-bit bus by write access. Information indicating the period during which data is valid, RFframe32 is information indicating occupation of a 32-bit bus by read access, RData32 is transfer data on a 32-bit bus by read access, and RDvalid32 is 32 bits in read access Each of the pieces of information indicates a period during which data on the width bus is valid.

Next, referring to FIG. 28 to FIG. 30, in the bus connection circuit of this example, read data is exchanged by split transfer, and an operation example when write data is exchanged at the same time is shown as a 32-bit bus master. A case will be described in which a write access is performed after performing a read access to a 64-bit bus slave unit from the unit. In the timing chart of FIG. 30, the details of the arbitration operation are omitted.

First, in response to an arbitration request from the bus master unit, arbitration of the bus right for the write buses 1W and 2W is performed. As a result, when the bus right is granted, the WF frame 32 is set in the write bus 2W on the 32-bit side from the bus master unit. Activated. Further, the WFframe 64 is activated in the write bus 1W on the 64-bit side from the write data conversion unit 3W. At the same time, an address specifying the bus slave unit, Cmd indicating the data size, and DID specifying the bus master unit are output as commands from the bus master unit. As a result, the designated bus slave unit returns Devsel, and further outputs ACK indicating that the instruction of Cmd has been accepted to the write bus 1W on the 64-bit side. Thereafter, the bus master unit once inactivates the WFframe 32, and thereby the WFframe 64 is also inactivated.

Next, in the bus slave unit, when read data is ready, the arbitration request is made to arbitrate the bus right for the read buses 1R and 2R. As a result, when the bus right is granted, 64 The RF frame 64 is activated in the read bus 1R on the bit side, whereby the RF frame 32 is activated in the read bus 2R on the 32 bit side from the read data conversion unit 3R. At the same time, RCmd indicating the data size and RDID specifying the bus master unit are output as commands from the bus slave unit. As a result, the bus slave unit activates RDvalid 64 in the 64-bit read bus 1R and outputs RData 64. When the output of RData 64 ends, the bus slave unit inactivates RDvalid 64 and inactivates RF frame 64. At this time, ACK from the bus master unit is not required.

When the RData 64 is received, the read data conversion unit 3R activates the RDvalid 32 in the 32-bit read bus 2R, converts the received RData 64 into the RData 32, and sends it to the bus master unit. At the end of transmission, the read data conversion unit 3R inactivates the RDvalid 32 and inactivates the RF frame 32.

On the other hand, in response to the arbitration request from the bus master unit again, arbitration of the bus right for the write buses 1W and 2W is performed. As a result, when the bus right is granted, the WFframe32 in the write bus 2W on the 32-bit side from the bus master unit. Is activated, and WFframe 64 is activated on the write bus 1W on the 64-bit side from the write data conversion unit 3W. At the same time, Address, Cmd, and DID are output as commands from the bus master unit. As a result, the designated bus slave unit returns Devsel and outputs ACK indicating that the instruction of Cmd has been accepted to the 64-bit write bus 1W.

Next, the bus master unit activates WDvalid 32 output to the write bus 2W on the 32-bit side, outputs WData 32, and when finished, deactivates WDvalid 32 and deactivates WF frame 32. When the write data conversion unit 3W receives WDData32, it converts it to WData64, activates WDvalid64 on the 64-bit write bus 1W, outputs WDData64 to the bus slave unit, and when finished, installs WDvalid64. At the same time, the WFframe 64 is made inactive.

The split transfer read access and write access from the 64-bit bus master unit to the 32-bit bus slave unit can be performed in the same manner as combinations of operations in the first embodiment shown in FIGS. it can.

As described above, in the bus connection circuit of this example, when the read data bus and the write data bus are separate, the split transfer read access and write access can be performed separately. The number of clock cycles in write access can be reduced. At this time, data loss does not occur at the transmission source when a data transfer error occurs, and a data transfer error occurrence notification to the transmission source is possible as in the case of the first embodiment.

Furthermore, it is not necessary to control the command control signal in detail as in the conventional bus master control circuit and bus slave control circuit, and only hardware that extracts the conditions that require data conversion and performs data conversion is prepared. Since it is good, the circuit configuration is simplified, and the amount of necessary hardware can be reduced. In the bus control circuit of this example, the number of bus arbitrations is small, and therefore the delay is small. Therefore, the period of occupying the bus is shortened, and as a result, the bus throughput can be improved.

FIG. 31 is a block diagram showing the configuration of a bus system in the case of performing bus width conversion in two stages using two data conversion units according to a fourth embodiment of the present invention. is there. Hereinafter, as a fourth embodiment, two data conversion units are used to connect two types of buses to each other when three types of buses having different bus widths and having a common read data bus and write data bus are used. Next, the bus system when the bus width is converted will be described.

As shown in FIG. 31, the bus system of this example has a 128-bit connection connected to the first bus 101 with respect to the first bus 101, the second bus 102, and the third bus 103. A bus master unit 104, a 128-bit bus slave unit 105 connected to the first bus 101, a 64-bit bus master unit 106 connected to the second bus 102, and a 64-bit connected to the second bus 102. A bit bus slave unit 107, a 32-bit bus master unit 108 connected to the third bus 103, a 32-bit bus slave unit 109 connected to the third bus 103, and a first data conversion unit 110. And a second data conversion unit 111 and an arbitration circuit 112.

The first bus 101 has a data width of 128 bits, the second bus 102 has a data width of 64 bits, the third bus 103 has a data width of 32 bits, The address bus and control bus signals can be transferred between the first bus 101 and the second bus 102 and between the second bus 102 and the third bus 103 via the common control command bus, respectively. It has become. The bus master unit 104 interfaces a command, read data, and write data between a 128-bit external master unit (not shown) and the first bus 101, and the bus slave unit 105 is a 128-bit external slave unit. A command, read data, and write data are interfaced between (not shown) and the first bus 101.

A bus master unit 106 interfaces a command, read data, and write data between a 64-bit external master unit (not shown) and the second bus 102, and a bus slave unit 107 is a 64-bit external slave unit. A command, read data, and write data are interfaced between (not shown) and the second bus 102. The bus master unit 108 interfaces a command, read data, and write data between a 32-bit external master unit (not shown) and the third bus 103, and the bus slave unit 109 is a 32-bit external slave unit. A command, read data, and write data are interfaced between (not shown) and the third bus 103.

The first data conversion unit 110 performs mutual bit width conversion between the 128-bit width data and the 64-bit width data between the first bus 101 and the second bus 102, and The second data conversion unit 111 performs mutual bit width conversion between the 64-bit width data and the 32-bit width data between the second bus 102 and the third bus 103. The arbitration circuit 112 receives the first bus 101 and the second bus in response to respective arbitration request signals from the bus master unit 104, the bus slave unit 105, the bus master unit 106, the bus slave unit 107, the bus master unit 108, and the bus slave unit 109. Arbitration of the bus right in the second bus 102 and the third bus 103 is performed, and an arbitration grant signal is output to the bus master unit or bus slave unit that has obtained the bus right.

The bus connection between the first bus 101 and the second bus 102 or the bus connection between the second bus 102 and the third bus 103 in the bus connection circuit shown in FIG. This is performed in the same manner as in the first embodiment. In addition, the bus connection between the first bus 101 and the third bus 103 includes the bus connection between the first bus 101 and the second bus 102, and between the second bus 102 and the third bus 103. The buses can be connected to each other sequentially. Therefore, according to the bus connection circuit shown in FIG. 31, three types of buses having different bit widths, that is, a 128-bit width bus, a 64-bit width bus, and a 32-bit width bus, are mutually connected. can do.

In this way, according to the bus connection circuit of this example, the bus width conversion is performed in two stages using two data conversion units, so that three types of common read data bus and write data bus can be obtained. Buses with different bus widths can be connected to each other to perform split transfer read access and write access, and at this time, arbitration when crossing between buses is unnecessary, and only data conversion is performed. Therefore, the number of clock cycles in read access and write access can be reduced. Therefore, data transfer from the transmission source to the transmission destination can be performed within the same bus cycle, so that no data loss occurs at the transmission source when a data transfer error occurs, and a data transfer error notification to the transmission source is possible. This is the same as in the first embodiment.

Furthermore, it is not necessary to control the command control signal in detail as in the conventional bus master control circuit and bus slave control circuit, and only hardware that extracts the conditions that require data conversion and performs data conversion is prepared. Since it is good, the circuit configuration is simplified, and the amount of necessary hardware can be reduced. In the bus control circuit of this example, the number of bus arbitrations is small, and therefore the delay is small. Therefore, the period of occupying the bus is shortened, and as a result, the bus throughput can be improved.

FIG. 32 is a block diagram showing a configuration of a bus system in the case where three types of buses having different bit widths are connected using one data conversion unit according to a fifth embodiment of the present invention. FIG. 33 is a block diagram showing a configuration example of the data conversion unit in the bus system of the present embodiment, and FIG. 34 transmits signals output from both the bus master unit and the bus slave unit in the bus system of the present embodiment. FIG. 35 is a diagram for explaining the bus configuration in this case, FIG. 35 is a diagram for explaining the bus configuration in the case of transmitting a signal output only by the bus master unit in the bus system of this embodiment, and FIG. It is a figure explaining the structure of a bus | bath in the case of transmitting the signal which only a bus slave unit side outputs in a system. In the following, as a fifth embodiment, a bus system will be described in which one data conversion unit is used to mutually convert bus widths when three types of buses having different bus widths are connected. .

As shown in FIG. 32, the bus system of this example has a 128-bit connection connected to the first bus 201 with respect to the first bus 201, the second bus 202, and the third bus 203. A bus master unit 204, a 128-bit bus slave unit 205 connected to the first bus 201, a 64-bit bus master unit 206 connected to the second bus 202, and a 64-bit connected to the second bus 202. Bit bus slave unit 207, 32-bit bus master unit 208 connected to the third bus 203, 32-bit bus slave unit 209 connected to the third bus 203, data conversion unit 210, arbitration The circuit 211 has a schematic configuration.

The first bus 201 has a data width of 128 bits, the second bus 202 has a data width of 64 bits, the third bus 203 has a data width of 32 bits, Address bus between the second bus 202 and the second bus 202, between the second bus 202 and the third bus 203, and between the first bus 201 and the third bus 203, respectively, via a common control command bus. And control bus signals can be transferred to each other. A bus master unit 204 interfaces a command, read data, and write data between a 128-bit external master unit (not shown) and the first bus 201, and a bus slave unit 205 is a 128-bit external slave unit. A command, read data, and write data are interfaced between (not shown) and the first bus 201.

A bus master unit 206 interfaces a command, read data, and write data between a 64-bit external master unit (not shown) and the second bus 202, and a bus slave unit 207 is a 64-bit external slave unit. A command, read data, and write data are interfaced between (not shown) and the second bus 202. The bus master unit 208 interfaces a command, read data, and write data between a 32-bit external master unit (not shown) and the third bus 103, and the bus slave unit 209 is a 32-bit external slave unit. A command, read data, and write data are interfaced between (not shown) and the third bus 203.

The data conversion unit 210 is connected between the first bus 201, the second bus 202, and the third bus 203 between 128-bit data, 64-bit data, and 32-bit data. Convert the bit width of. The arbitration circuit 211 receives the first bus 201 and the second bus in response to respective arbitration request signals from the bus master unit 204, the bus slave unit 205, the bus master unit 206, the bus slave unit 207, the bus master unit 208, and the bus slave unit 209. Arbitration of the bus right in the bus 202 and the third bus 203 is performed, and an arbitration grant signal is output to the bus master unit or bus slave unit that has obtained the bus right.

FIG. 33 shows a configuration example of the data conversion unit in the bus connection circuit of FIG. As shown in FIG. 33, the data conversion unit 210 is roughly configured by a data buffer 211, a timing control unit 212, and multiplexers 213, 214, 215, 216, 217, 218, and 219.

The data buffer 211 is composed of, for example, a FIFO memory that performs mutual bit width conversion among 128-bit data, 64-bit data, and 32-bit data. In other words, the data buffer 211 writes data of 128-bit width and reads the data in 64 bits twice to read the data into 64-bit width, or reads the data in 32 bits in four times. Thus, the data is converted into 32-bit width data, and the 64-bit width data is written, and the data is converted into 32-bit width data by reading the data in 32 bits twice.

Further, conversely, conversion of data of 32 bits width from the upper order to the lower order or from the lower order to the upper order is performed by combining and reading data written in two times to convert the data into 64-bit width data. In addition, by combining and reading 32-bit width data from the upper order to the lower order, or from the lower order to the upper order, and writing the data divided into four times, or the 64-bit width data The data written in two portions is combined and read from the upper order to the lower order or from the lower order to the upper order, thereby converting the data into 128-bit width data.

The timing control unit 212 controls the multiplexers 213, 214, 215, and 216 by the write selection signal when writing 128-bit data in accordance with the 128-bit control command signal, 64-bit control command signal, or 32-bit control command signal. Then, the data of the 128-bit data line is input to the data buffer 211, and when the 64-bit data is written, the multiplexer 213, 214 or 215, 216 is controlled by the write selection signal, and the data of the 64-bit data line is When writing to 32-bit data and writing 32-bit data, one of the multiplexers 213, 214, 215, and 216 is controlled by a write selection signal, and control is performed so that 32-bit data line data is input to the data buffer 21. And 128 bits When reading data, the multiplexer 217 is controlled by the 128-bit output selection signal to output 128-bit data to the 128-bit data line. When reading 64-bit data, the multiplexer 218 is controlled by the 64-bit output selection signal. The 64-bit data is output to the 64-bit data line, and when reading the 32-bit data, the multiplexer 219 is controlled by the 32-bit output selection signal to control the 32-bit data to be output to the 32-bit data line.

Further, when outputting the 128-bit data signal, the timing controller 212 outputs a 128-bit data valid signal indicating a period in which the 128-bit data is valid and a 128-bit frame signal indicating that the 128-bit data line is activated. When a 64-bit data signal is output, a 64-bit data valid signal indicating a period in which the 64-bit data is valid and a 64-bit frame signal indicating that the 64-bit data line is activated are output. At the time of output, a 32-bit data valid signal indicating a period in which 32-bit data is valid and a 32-bit frame signal indicating that the 32-bit data line is activated are output.

FIG. 34 shows a configuration of a bus that transmits signals output from both the bus master unit and the bus slave, for example, a frame signal, among a plurality of buses constituting the bus 203 in the bus connection circuit shown in FIG. Is. A bus 1301 for transmitting such a signal includes multiplexers X17, X18, and X19, and OR circuits O15 and O16.

The 4: 1 multiplexer X17 receives Frame32_O and Frame32_OE from the master units M21 and M22 and the slave units S21 and S22, and selects and outputs the Frame32_O signal based on the Frame32_OE. The 2: 1 multiplexer X19 selects and outputs a frame signal from the outside of the bus 1301 (a frame signal from the bus 201 or the bus 202). The 2: 1 multiplexer X18 supplies either the output of the multiplexer X17 or the output of the multiplexer X19 to the master units M21 and M22 and the slave units S21 and S22 based on the outputs of the OR circuit O15 and the OR circuit O16.

FIG. 35 shows a configuration of a bus for transmitting a signal output only from the bus master unit, for example, an address signal, among a plurality of buses constituting the bus 203 in the bus connection circuit shown in FIG. The bus 1302 for transmitting such a signal includes multiplexers X11, X12, and X13, and OR circuits O11 and O12.

For example, the 32-bit bus master units M21 and M22 output an Addr32_O signal as an address signal and an Addr32_OE signal indicating its validity. As a result, the multiplexer X11 selects and outputs only one of the enabled Addr32_O signals. The Addr32_O signal is output to the common control command bus together with the signal obtained by taking the Addr32_OE signal from the bus master units M21 and M22 in the OR circuit O11.

Further, the multiplexer X13 selects the Addr128_O signal from the 128-bit bus and the Addr64_O signal from the 64-bit bus, the signal selected by the Addr128_OE signal from the 128-bit bus and the Addr64_OE signal from the 64-bit bus, and the multiplexer X11. In the multiplexer X12, the signal Addr32_O is selected by the signal from the OR circuit O11 and the signal obtained by ORing the Addr128_OE signal from the 128-bit bus and the Addr64_OE signal from the 64-bit bus in the OR circuit O12. The selected signal is commonly connected to the 32-bit bus slave units S21 and S22 as an Addr_I signal indicating an address input.

Furthermore, by making such a connection between a 64-bit bus master unit and a 128-bit bus master unit and a 32-bit bus master unit, and between a 128-bit bus master unit, a 32-bit bus master unit and a 64-bit bus master unit, Control commands can be shared among a bus, a 64-bit bus, and a 128-bit bus.

FIG. 36 shows a configuration of a bus that transmits a signal output from only a bus slave unit, for example, an Ack signal, among a plurality of buses constituting the bus 203 in the bus connection circuit shown in FIG. . The bus 1303 for transmitting such a signal includes multiplexers X14, X15, and X16 and OR circuits O13 and O14.

For example, when each of the 32-bit bus slave units S21 and S22 outputs an ACK32_O signal indicating transmission permission, each outputs an ACK32_OE signal indicating its validity. As a result, the multiplexer X14 selects and outputs only one of the valid ACK32_O signals. The ACK32_O signal is output to the common control command bus together with a signal obtained by taking the ACK32_OE signal from the bus slave units S21 and S22 in the OR circuit O13.

Further, in the multiplexer X16, the ACK128_O signal from the 128-bit bus and the ACK64_O signal from the 64-bit bus are selected by the multiplexer X14 and the signal selected by the ACK128_OE signal from the 128-bit bus and the ACK64_OE signal from the 64-bit bus. The received ACK32_O signal is selected in the multiplexer X15 by the signal from the OR circuit O13 and the OR circuit O14 which is ORed with the ACK128_OE signal from the 128-bit bus and the ACK64_OE signal from the 64-bit bus. The selected signal is commonly connected to the bus master units M21 and M22 as an ACK_I signal indicating the input of ACK.

Furthermore, by making such a connection between a 64-bit bus master unit and a 128-bit bus master unit and a 32-bit bus master unit, and between a 128-bit bus master unit, a 32-bit bus master unit and a 64-bit bus master unit, Control commands can be shared among a bus, a 64-bit bus, and a 128-bit bus.

As described above, according to the bus connection circuit of this example, by using the single data conversion unit to mutually convert the bus width, each of the three types of common read data bus and write data bus is provided. Buses with different bus widths can be connected to each other to perform split transfer read access and write access. At this time, no bus arbitration is required between buses, and only data conversion is performed. Therefore, the number of clock cycles in read access and write access can be reduced. Therefore, since data transfer from the transmission source to the transmission destination can be performed within the same bus cycle, no data loss occurs even when a data transfer error occurs, and a data transfer error from the transmission destination to the transmission source. The occurrence can be notified as in the case of the first embodiment.

Furthermore, it is not necessary to control the command control signal in detail as in the conventional bus master control circuit and bus slave control circuit, and only hardware that extracts the conditions that require data conversion and performs data conversion is prepared. Since it is good, the circuit configuration is simplified, and the amount of necessary hardware can be reduced. In the bus control circuit of this example, the number of bus arbitrations is small, and therefore the delay is small. Therefore, the period of occupying the bus is shortened, and as a result, the bus throughput can be improved.

Application Example Next, an example of an information processing system to which the above-described bus system of the present invention is applied and an information processing system including a chip to which the bus system of the present invention is applied will be described with reference to FIGS. And explain briefly. Since the components using the same reference numbers as those of the embodiments have already been described, the description thereof will be omitted.

FIG. 37 shows an example of an information processing system to which the bus conversion unit of the present invention is applied. The bus conversion unit 370 of the present invention includes a bus 1, a bus 2, a data conversion unit 3, a bus master unit 4, 5, 8, 9, a bus slave unit 6, 7, 10, 11, an arbitration circuit 12, a common control command bus 372. , And a control command conversion circuit 371. A line between the arbitration circuit, the bus master unit, and the bus slave unit is omitted. External master units 301, 302, 303, and 304 and external slave units 401, 402, 403, and 404 are connected to the bus conversion unit 370 to configure an information processing system.

When the command formats on the control command lines of the bus 1 and the bus 2 are different, the control command conversion circuit 371 is sandwiched between the common control command buses 372, and the command format is controlled by the control command conversion circuit 371. Can absorb the difference. When the bus conversion unit 370 is considered as one macro, the external master unit and the external slave unit need only consider the interface with the bus master unit and the bus slave unit, and need not be aware of the internal circuit configuration.

Further, the information processing system described in FIG. 37 may be configured on one chip. Thus, when the information processing system is configured on one chip, the following information processing system can be constructed. As an example of the information processing system, a configuration including a chip 380, an external bus 382, an external memory 383, and a chip 384 is shown in FIG.

The chip 380 including the bus conversion unit 370 includes an I / O interface 381 connected to a bus slave unit in the bus conversion unit 370. (In FIG. 38, it is considered that the external slave unit 401 is replaced with the I / O interface 381.) The I / O interface 381 is connected to the external memory 383 and another chip 384 via the external bus 382.

In this example, the bus master unit connected to the bus conversion unit 370 can access the external memory 383 and the chip 384 via the bus slave unit 6. At this time, since the bus conversion unit 370 has low latency, the chip 384 can be accessed as the external memory 383 and the external slave unit at high speed. Further, by using a bus master unit instead of the bus slave unit 6, it is possible to connect to an external master unit provided outside the chip. For example, the memory on the chip 380 can be accessed using the chip 384 as an external master unit. At this time, the chip 384 can access the memory on the chip 380 at high speed because the latency of the bus conversion unit is small.

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and even if there is a design change or the like without departing from the gist of the present invention. Included in the invention. For example, in the embodiment of the present invention, it is assumed that the logic configured using the OR circuit is active HI. In the case of active LOW, an AND circuit can be used. In the embodiment, the bus slave unit including the address comparison circuit is described. However, the address comparison circuit may be provided outside the bus slave unit.

Further, in the embodiment, the timing control unit 22 performs bit conversion control corresponding to which bus the Frame signal and the Ack signal are sent for read data transfer from the slave. However, if the master that outputs the Ack signal is in a state where data can be received without fail, the Ack signal from the master side becomes unnecessary. However, the timing control unit 22 always performs bit conversion because the direction of bit conversion is not known when the Ack signal disappears. In this case, since it is not necessary to wait for the Ack signal, the speed is increased, but the power consumption is increased. Conversely, when the master side outputs the Ack signal, the speed is reduced by waiting for the Ack signal. However, when bit conversion is unnecessary, power consumption can be reduced.

In the embodiments, the data transfer bus between two or three different bit width buses has been described. However, the present invention is not limited to this, and the bit between two or more different bit width buses is not limited thereto. It can also be applied during width conversion. The present invention can also be applied by connecting a control command conversion circuit to a common control command bus when connecting buses in which different control commands are defined.

Further, in this embodiment, the circuit configuration relating to the bus system has been specifically exemplified, but electronic data representing this circuit structure is generated for the bus system and the chip 380 including the bus system, and the computer apparatus is used. It can also be stored in an information storage medium as readable software (not shown). Further, a computer program that causes the computer processing device to simulate the operation of the bus system and the chip 380 including the bus system is described in a programming language such as C language, a hardware description language such as Verilog-HDL, and the like on an information storage medium. It is also possible to store (not shown), and it is also possible to form a computer device in which this computer program and the above-mentioned electronic data are stored in an information storage medium.

The electronic data of the circuit structure referred to in the present invention may be software that can specify the logical structure of the circuit structure. For example, operation description data, RTL (Register Transfer Level) data, gate level data, transistor level data, etc. It is possible to make a net list of circuit devices consisting of The information storage medium referred to in the present invention may be hardware in which a computer program for causing a computer device to execute various processes is stored in advance. For example, a ROM (Read Only Memory) fixed to the computer device. ), HDD (Hard Disc Drive), CD (Compact Disc) -ROM, FD (Flexible Disc-Cartridge), and the like that are exchangeably loaded into the computer apparatus.

An LSI to which the present invention is applied can be applied to various different real systems. As an advantage in this case,
1. In the actual system to which the present invention is applied, the latency (number of clock cycles) can be reduced even in the case of access to the outside of the chip, based on the low latency access which is a unique effect of the bus conversion unit of the present invention.
2. Only the interface between the bus master unit and bus slave unit data needs to be performed, and there is no need to design in consideration of the situation of the data transfer destination, so even if the LSI is replaced with a bus of a larger bit width in the future, The chip can continue to be used in the same system.

Furthermore, by providing the bus connection circuit of the present invention, it is possible to configure an information processing system that performs arbitrary information processing using data of a plurality of buses having different bit widths. Also, the bus connection circuit of the present invention or the information processing system described above can be formed as an integrated circuit on a semiconductor substrate, and these circuit / system information can be recorded as electronic data in a storage medium.

1 is a block diagram showing a configuration of a bus system according to a first embodiment of the present invention. It is a figure which shows the system configuration | structure containing the common control command bus | bath of the bus system of a present Example. It is a figure which shows the structure of the bus master unit in a present Example. It is a figure which shows the structure of the data conversion unit in a present Example. It is a figure which shows the structure of the bus slave unit in a present Example. 4 is a timing chart showing a data transfer operation during read access from a 32-bit bus master unit to a 64-bit bus slave unit in the present embodiment. 6 is a timing chart showing a data transfer operation during read access from a 64-bit bus master unit to a 32-bit bus slave unit in the present embodiment. 6 is a timing chart showing a data transfer operation during a write access from a 64-bit bus master unit to a 32-bit bus slave unit in the embodiment. 6 is a timing chart showing a data transfer operation during a write access from a 32-bit bus master unit to a 64-bit bus slave unit in the present embodiment. It is a block diagram which shows the structure of the bus system which is 2nd Example of this invention. 4 is a timing chart showing a data transfer operation at the time of read access from a 32-bit bus master to a 64-bit slave unit in this embodiment. It is a figure which shows the outline | summary of the command in a present Example. It is a flowchart which shows the flow of a process from the arbitration of a bus right to use of a bus in the bus connection circuit of a present Example. It is a flowchart explaining the process sequence of the data conversion unit at the time of split transfer in the bus system of a present Example. It is a flowchart explaining the process sequence of the data conversion unit at the time of split transfer in the bus system of a present Example. It is a flowchart which shows the process of a bus master unit including the arbitration operation | movement of a bus right in the bus system of a present Example. It is a flowchart which shows the process of a bus master unit including the arbitration operation | movement of a bus right in the bus system of a present Example. It is a flowchart which shows the process of a bus slave unit including the arbitration operation | movement of a bus right in the bus system of a present Example. It is a flowchart which shows the process of a bus slave unit including the arbitration operation | movement of a bus right in the bus system of a present Example. It is a figure which shows the structure of the bus | bath using a multiplexer. It is a figure explaining the structure of the bus | bath of a multiplexer type in the case of transmitting the signal which both a bus master unit and a bus slave unit output. It is a figure explaining the structure of the bus | bath of a multiplexer form in the case of transmitting the signal which only a bus master unit outputs. It is a figure explaining the structure of the bus | bath of a multiplexer form in the case of transmitting the signal which only a bus slave unit outputs. It is a figure which shows the structure of the bus | bath using a 3 state buffer. It is a figure explaining the structure of a 3 state buffer type bus | bath in case a bus master unit and a bus slave unit output a signal together. It is a figure explaining the structure of a 3 state buffer type bus | bath in case only a bus master unit outputs a signal. It is a figure explaining the structure of a 3 state buffer type bus | bath in case only a bus slave unit outputs a signal. It is a block diagram which shows the structure of the bus system which is 3rd Example of this invention. It is a figure which shows the system configuration | structure containing the common control command bus | bath of the bus system of a present Example. 4 is a timing chart illustrating a data transfer operation when a write access is performed after a read access from a 32-bit bus master unit to a 64-bit bus slave unit in the present embodiment. It is a block diagram which shows the structure of the bus system in the case of performing conversion of a bus width into two steps using two data conversion units which are 4th Example of this invention. It is a block diagram which shows the structure of the bus system in the case of connecting the bus | bath of three different bit widths using one data conversion unit which is 5th Example of this invention. It is a block diagram which shows the structural example of the data conversion unit in the bus system of a present Example. In the bus system of a present Example, it is a figure explaining the bus structure in the case of transmitting the signal which a bus master unit and a bus slave unit output together. In the bus system of a present Example, it is a figure explaining the bus structure in the case of transmitting the signal which only a bus master unit outputs. It is a figure explaining the structure of a bus | bath in the case of transmitting the signal which only the bus slave unit side outputs in the bus system of a present Example. It is a block diagram of an information processing system to which a bus conversion unit of the present invention is applied. It is a block diagram of an information processing system including a chip to which the bus conversion unit of the present invention is applied. It is a block diagram which shows the structural example of the bus connection circuit of the conventional bridge system.

Explanation of symbols

1, 1W, 1R bus 2, 2W, 2R bus 3, 3W, 3R Data conversion unit (data conversion means)
4 Bus master unit (master side interface means)
5 Bus master unit (interface on the master side)
6,6A bus slave unit (interface means on the slave side)
7,7A Bus slave unit (slave side interface means)
8 Bus master unit (master side interface means)
9 Bus master unit (master side interface means)
10, 10A bus slave unit (interface means on the slave side)
11, 11A Bus slave unit (interface means on the slave side)
12, 12A, 12B Arbitration circuit (arbitration means)
50 Common control command bus 101, 102, 103, 201, 202, 203 Bus 104, 106, 108, 204, 206, 208 Bus master unit (master side interface means)
105, 107, 109, 205, 207, 209 Bus slave unit (interface means on the slave side)
110, 111, 210 Data conversion unit (data conversion means)
112, 211 arbitration circuit (arbitration means)

Claims (12)

A first output signal and a first enable signal output from a first unit having a first data bit width, and a second output output from a second unit having the first data bit width A first selection circuit that receives the signal and the second enable signal and selectively outputs the first or second output signal in response to the first or second enable signal becoming active;
A third output signal and a third enable signal output from a third unit having a second data bit width different from the first data bit width, the first output signal being supplied via a conversion unit. 3 output signal, the third enable signal, the output of the first selection circuit, and a signal based on the first and second enable signals, and the first or second enable signal is active Supplies the output of the first selection circuit to the first and second units, and supplies the third output signal to the first and second units when the third enable signal is active. A bus connection circuit comprising: a second selection circuit. 2. The circuit according to claim 1, further comprising a gate circuit that receives the first and second enable signals and outputs an enable signal to the conversion unit when the first or second enable signal becomes active. Bus connection circuit. 2. The bus connection circuit according to claim 1, wherein the first unit is a bus master unit, and the second unit is a bus slave unit. A first output signal and a first enable signal output from the first bus master unit having the first data bit width, and a second output output from the second bus master unit having the first data bit width. A first selection circuit that receives the signal and the second enable signal and selectively outputs the first or second output signal in response to the activation of the first or second enable signal; A third output signal and a third enable signal output from a third bus master unit having a second data bit width different from the first data bit width, and supplied via a conversion unit; Receiving a third output signal, the third enable signal, an output of the first selection circuit, and a signal based on the first and second enable signals, and receiving the first or second enable signal; When the bull signal is active, the output of the first selection circuit is supplied to the bus slave unit having the first data bit width, and when the third enable signal is active, the third output signal is supplied. And a second selection circuit for supplying the bus slave unit. 5. The apparatus according to claim 4, further comprising a gate circuit that receives the first and second enable signals and outputs an enable signal to the conversion unit when the first or second enable signal becomes active. Bus connection circuit. The first output signal and the first enable signal output from the first bus slave unit having the first data bit width, and the second output signal output from the second bus slave unit having the first data bit width. The first selection circuit receives the output signal and the second enable signal and selectively outputs the first or second output signal in response to the activation of the first or second enable signal. When,
A third output signal and a third enable signal output from a third bus master unit having a second data bit width different from the first data bit width, and supplied via a conversion unit; In response to a third output signal, the third enable signal, an output of the first selection circuit, and a signal based on the first and second enable signals, the first or second enable signal is active. When the output of the first selection circuit is supplied to the bus master unit having the first data bit width, the third output signal is supplied to the bus master unit when the third enable signal is active. And a second selection circuit for supplying the bus connection circuit. A semiconductor integrated circuit comprising the bus connection circuit according to any one of claims 1 to 6 integrated on a semiconductor substrate. A storage medium storing the connection information of the bus system, the information processing system, the bus connection circuit, or the semiconductor integrated circuit according to any one of claims 1 to 7. A computer processing apparatus for executing various data processing in a semiconductor integrated circuit, comprising the semiconductor integrated circuit according to claim 7. 7. Software readable by a computer device, comprising software data of the bus system circuit structure or the bus connection circuit circuit structure according to any one of claims 1 to 6. 11. An information storage medium storing software readable by a computer device, wherein the electronic data or software according to claim 10 is stored. A computer apparatus in which software is stored in an information storage medium, comprising the information storage medium according to claim 11.

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