JP4250464B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit including a data output circuit that outputs data from the semiconductor integrated circuit.
[Prior art]
When the output data of the semiconductor integrated circuit changes from the previous signal level to a new signal level, current is consumed in the output I / O buffer according to the change. As the number of output I / Os increases, the current that flows during operation of the output I / O buffer increases as a whole. Further, when the operation of the semiconductor integrated circuit becomes faster, the instantaneously flowing current value di / dt increases. As a result, if the power supply potential or ground potential of the I / O buffer fluctuates greatly, the semiconductor integrated circuit may malfunction. In particular, when the degree of integration of the semiconductor integrated circuit is increased and the circuit structure becomes finer, it becomes more susceptible to potential fluctuations, and thus the problem of malfunction described above becomes obvious.
[0002]
This potential fluctuation depends on the magnitude of the parasitic inductance between the package on which the semiconductor integrated circuit is mounted and the semiconductor integrated circuit. Therefore, by reducing the parasitic inductance value, potential fluctuation noise can be reduced. However, packages with low inductance generally tend to be expensive and are not a desirable solution from a cost standpoint.
[0003]
Another solution is to shift the data output timing. Since a synchronous semiconductor integrated circuit outputs data in synchronization with a clock, the output I / O buffer also operates at the same timing. However, in general, the operating frequency of I / O is lower than the operating frequency inside the semiconductor integrated circuit, and the timing margin is often wide. Therefore, it is possible to design the output timing from the output I / O buffer to be shifted within a range of about 1/10 of the output clock cycle time. Thereby, the peak value of current due to simultaneous switching can be reduced. However, since the timing of each output I / O buffer is adjusted at the time of design, there is a problem that the design becomes complicated. Further, when the number of I / O buffers increases, it becomes impossible to cope with timing adjustment alone.
[0004]
As another solution, there is a method of encoding output data (Non-Patent Document 1 and Non-Patent Document 2). If the previous output data and the new output data are the same, the output I / O buffer is not switched and no current flows. Therefore, if the number of output I / O buffers that are appropriately encoded and switched simultaneously is reduced, the amount of flowing current can be reduced and potential fluctuation noise can be reduced.
[0005]
[Patent Document 1]
JP-A-8-316840
[0006]
[Patent Document 2]
JP 2000-295088 A
[0007]
[Patent Document 3]
JP 2002-259940 A
[0008]
[Non-Patent Document 1]
MR Stan et al. Et al., “Bus-Inverted Coding for Low Power I / O”, (US), I Triple E Transaction on Belly Large Scale Integration Systems (IEEE Transaction on Very Large Scale Integration Systems), March 1995, Volume 3 (Vol. 3), Issue 1 (No. 1), pp 49-58
[0009]
[Non-Patent Document 2]
S. Komatsu et al., “Bus Data Encoding with Coupling-driven Adaptive Code-book Method for Low Power Data Transmission” (Austria), 27th European Solid-State Circuits Conference Proceeding, September 2001
[Problems to be solved by the invention]
In the method of encoding the output data, the value of the output data is changed by the encoding. Therefore, a circuit for decoding the data is required on the semiconductor integrated circuit side that receives the data. Therefore, it is not possible to exchange data with each other regardless of the other party's configuration, and it is not a general-purpose technique that can be used in a general system.
[0010]
In view of the above, the present invention provides a semiconductor integrated circuit that reduces potential fluctuations by reducing the number of output I / O buffers that are simultaneously switched to a predetermined number or less without requiring a special circuit on the receiving side. With the goal.
[Means for Solving the Problems]
The semiconductor integrated circuit according to the present invention includes an output I / O buffer for outputting output data supplied from a data supply source to the outside of the semiconductor integrated circuit, and a first output output from the output I / O buffer in the first cycle. According to the judgment whether or not the register holding the data, the output data to be newly output from the output I / O buffer, and the first output data held in the register differ by more than a predetermined reference , Second output data supplied from the data supplier in a second cycle following the first cycle, third output data supplied from the data supplier before the second cycle, and the A control circuit that controls to output any one of the first output data from the output I / O buffer in the second cycle; In response to the determination that the difference between the second output data and the first output data is equal to or less than a predetermined number of bits, the control circuit outputs the second cycle from the output I / O buffer. Output the second output data in step S3, and if the difference is not less than the predetermined number of bits, the difference between the third output data and the first output data is less than the predetermined number of bits. In response to the determination, the third output data is output from the output I / O buffer in the second cycle, and when the second or third output data is not output, the output I / O buffer Outputting the first output data in the second cycle It is characterized by that.
[0011]
In the semiconductor integrated circuit, it is determined how much the output data to be newly output from the output I / O buffer is different from the first output data held in the register, and the new output data is newly determined according to the determination result. It controls whether to actually output the output data to be output or to keep the output data unchanged. If the second output data supplied in the current cycle is not so different from the first output data that is the output data of the previous cycle, the second output data may be output. In this case, the current consumption is small because the number of output I / O buffers that are simultaneously switched is small. Similarly, if the third output data supplied in the previous cycle is not so different from the first output data that is the output data of the previous cycle, the third output data may be output. In this case, the current consumption is small because the number of output I / O buffers that are simultaneously switched is small. When both the second output data and the third output data are greatly different from the first output data, the same first data as in the previous cycle is output. In this case, current consumption can be eliminated by making the output unchanged.
[0012]
As described above, the present invention can provide a semiconductor integrated circuit in which the potential fluctuation is reduced by setting the number of output I / O buffers to be simultaneously switched to a predetermined number or less without incorporating a special circuit on the receiving side. .
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0013]
In order to reduce the number of output I / O buffers to be switched in a certain output cycle, the signal level changes between the output data of the previous cycle and the output data of the current cycle (data to be newly output). The number of I / O pins may be reduced. The number of I / O pins that change is represented by the Hamming distance between the code of the previous cycle and the code of the current cycle. The Hamming distance is a different number of bits between two codes. For example, in a 4-bit code, (0011) and (0000) are different in the last two bits, so the Hamming distance is 2. In the present invention, the Hamming distance between the output data of the previous cycle and the output data of the current cycle is calculated, and when the calculated distance is equal to or greater than a predetermined distance, dummy data is output without outputting the current cycle data. To do. The data of the current cycle that has not been output is stored in the memory, and is output at an appropriate opportunity later.
[0014]
FIG. 1 is a block diagram showing the configuration of an output data control circuit according to the present invention.
[0015]
The output data control circuit 10 of FIG. 1 includes an output I / O buffer 11, a register 12, a distance detector 13, a comparison circuit 14, a selector 15, a RAM 16, a controller 17, a distance detector 18, a comparison circuit 19, and N cycle mode data. A generation circuit 20 and a valid instruction signal output buffer 21 are included. The output data control circuit 10 shown in FIG. 1 is used to receive data and an address from the CPU as internal output data, for example, and supply this as external output data to the RAM. In the following, data output from the CPU will be described as an example, but the present invention is not limited to this example and can be applied to various data transfers.
[0016]
The output I / O buffer 11 outputs data supplied from the CPU as internal output data (for example, an address and data if a RAM or the like is a target) to a supply destination semiconductor integrated circuit. Here, for convenience of illustration, only one output I / O buffer 11 is shown, but the output data includes a plurality of bits, and the plurality of output I / O buffers are configured to output the respective bits. The valid instruction signal output buffer 21 outputs a valid instruction signal indicating whether or not the output data from the output I / O buffer 11 is valid. When the validity instruction signal indicates validity, the receiving-side semiconductor integrated circuit receives data from the output data control circuit 10. The use of such an effective instruction signal is a communication control technique normally found in a general system, and is not special to the present invention.
[0017]
The register 12 stores and stores the data sent in the previous cycle. The data stored in the register 12 is sent to the distance detector 13 in the next cycle. The distance detector 13 calculates the Hamming distance between the data stored in the register 12 and the internal output data newly supplied from the CPU. The calculated Hamming distance is supplied from the distance detector 13 to one input of the comparison circuit 14. The other input of the comparison circuit 14 receives a predetermined reference value preset in the controller 17. This reference value is the number of bits of I / O data allowed to change during one cycle, and can be set in advance by the user. The comparison circuit 14 compares the calculated Hamming distance with a reference value and supplies the comparison result to the controller 17.
[0018]
The controller 17 controls the selector 15 based on the comparison result from the comparison circuit 14. Specifically, when the hamming distance is smaller than the reference value, that is, when the number of bits to be simultaneously switched in the output I / O buffer 11 is smaller than the reference value, the controller 17 controls the selector 15 to determine the current cycle value. Are output from the output I / O buffer 11 as they are. On the contrary, when the Hamming distance is larger than the reference value, if the current cycle data is output, a large potential fluctuation noise is generated. Therefore, the controller 17 controls the selector 15 to select the previous cycle data from the register 12. The output data remains unchanged. Further, the controller 17 supplies an R / W control signal and a write address to the RAM 16 so that the data of the current cycle that has not been output is written to the RAM 16.
[0019]
The RAM 16 is provided to temporarily store data whose output has been suspended, and is a 1R / 1W type multi-port memory capable of simultaneously executing reading and writing with respect to different addresses. If there is data previously held and stored in the RAM 16, the controller 17 reads one of the stored data from the RAM 16 at the same time as writing the data of the current cycle in the RAM 16. The distance detector 18 calculates the Hamming distance between the output pending data read from the RAM 16 and the previous cycle data stored in the register 12. The comparison circuit 19 compares the distance calculated by the distance detector 18 with a preset reference value and supplies the comparison result to the controller 17.
[0020]
The controller 17 controls the selector 15 based on the comparison result of the comparison circuit 19. Thereby, when the Hamming distance is smaller than the reference value, the data read from the RAM 16 is selected by the selector 15 and output to the outside via the output I / O buffer 11. As can be seen from FIG. 1, the output data at this time passes through the N cycle mode data generation circuit 20. That is, in this case, the N cycle mode data generation circuit 20 passes the input side data as it is to the output side based on the control from the controller 17. When the Hamming distance is larger than the reference value, the selector 15 is controlled to select the previous cycle data from the register 12, and the output I / O buffer 11 outputs the same data as the previous time. Therefore, no current flows through the output I / O buffer 11. In this case, a dummy cycle occurs, and the output data is not received by the receiving semiconductor integrated circuit.
[0021]
The above operation is executed in each cycle. Therefore, in some cases, the number of data stored in the RAM 16 increases, and the storage capacity of the RAM 16 may be exceeded. In order to deal with this, when data whose output has been suspended is written in a number equal to or greater than a certain percentage of the storage capacity of the RAM 16, the controller 17 sends this data to the previous circuit (in this case, the CPU). A WAIT signal indicating that the above output data cannot be received is output. Thereafter, the controller 17 enters an operation mode in which data currently stored in the RAM 16 is output.
[0022]
When this operation mode is entered, the controller 17 sequentially reads the output pending data from the RAM 16 and outputs it to the outside via the N cycle mode data generation circuit 20, the selector 15, and the output I / O buffer 11. At this time, the N cycle mode data generation circuit 20 generates dummy data and outputs it so that the number of simultaneous switching of the output I / O buffer 11 does not exceed a predetermined number between a certain output data and the next output data. Insert between data. At this time, in order to output one output data from the output I / O buffer 11, the N cycle mode data generation circuit 20 uses a predetermined number of cycles of two cycles or more. In the following, for the sake of simplicity, a case where one data is output over two cycles will be described as an example.
[0023]
FIG. 2 is a diagram for explaining an example of the operation of the N cycle mode data generation circuit 20.
[0024]
FIG. 2 shows a case where one dummy data is inserted between the previous cycle data and the current cycle data, and the current cycle data is output after spending two cycles. As shown in the figure, the data of the previous cycle (data stored in the register 12) is considered divided into upper half data 30a and lower half data 30b. The data of the current cycle is assumed to consist of upper half data 31a and lower half data 31b. At this time, as dummy data, data is created in which the upper half is the upper half data 31a of the current cycle and the lower half is the lower half data 30b of the previous cycle. When the N cycle mode data generation circuit 20 outputs the data of the previous cycle, the N cycle mode data generation circuit 20 outputs the dummy data and then outputs the data of the current cycle. By performing such an operation of the N cycle mode data generation circuit 20, if the data length is n bits, data can be output so that only n / 2 bits change at the maximum. In the example shown in the figure, dummy data is created by changing the upper half from the data of the previous cycle. Alternatively, dummy data may be created by changing the lower half.
[0025]
In order to output data so that only n / 3 bits change at the same time, two dummy data are used so that data changes from the previous cycle to the current cycle by n / 3 bits over 3 cycles. It only has to be generated. Similarly, data may be output using a cycle number of 4 cycles or more.
[0026]
FIG. 3 is a diagram for explaining another example of the operation of the N cycle mode data generation circuit 20.
[0027]
In FIG. 3, the data of the previous cycle and the current cycle are compared for each bit, and the bit value of the bit having the same value is used as dummy data. For bits having different values, dummy cycle data is configured by alternately selecting the value of the previous cycle and the value of the current cycle in order from the upper bit or the lower bit. Also by this method, dummy data can be generated so that the data changes only by a maximum of n / 2 bits as a whole. Instead of selecting them alternately, the data of the previous cycle and the data of the current cycle may be selected separately for the upper half and the lower half of the bits having different values.
[0028]
Further, by changing the bits having different values by 1/3 and changing the data from the previous cycle to the current cycle over 3 cycles, the data output method can be extended to 3 cycles. Similarly, data may be output using a cycle number of 4 cycles or more.
[0029]
FIG. 4 is a circuit diagram showing an example of the configuration of the N cycle mode data generation circuit 20.
[0030]
The N cycle mode data generation circuit 20 of FIG. 4 is configured to output one data over two cycles, and includes selectors 41 and 42. The selectors 41 and 42 are controlled by control signals DMYU and DMYL from the controller 17, and select and output one of the two inputs. The output data of the current cycle is output data supplied from the RAM 16, and consists of an upper half RAMU and a lower half RAML. Also, the output data of the previous cycle is stored in the register 12, and consists of an upper half REGU and a lower half REGL. On the output side, OUTU is the upper bit side and OUTL is the lower bit side, and both are supplied to the selector 15.
[0031]
In the normal mode other than the N cycle mode, since the output of the RAM 16 is output as it is, the control signals DMYU and DMYL are set to 1, and OUTU = RAMU and OUTL = RAML. When the N cycle mode is entered, dummy data with OUTU = RAMU and OUTL = REGL is output by setting DMYL = 0 and DMYU = 1 in the first cycle, for example. Since the output of the RAM 16 may be output as it is in the second cycle, DMYL = DMYU = 1 may be set. When the upper bit side is the current register value and the lower bit side is the output value of the RAM 16 in the first cycle, DMYL = 1 and DMYU = 0 may be set contrary to the above.
[0032]
FIG. 5 is a circuit diagram showing another example of the configuration of N cycle mode data generation circuit 20.
[0033]
The N cycle mode data generation circuit 20 shown in FIG. 5 is configured to output one data over three cycles, and includes selectors 51 and 53. The selectors 51 to 53 are controlled by control signals DMYU, DMYM, and DMYL from the controller 17, respectively, and select and output one of the two inputs. The operation principle is the same as in FIG.
[0034]
FIG. 6 is a circuit diagram showing still another example of the configuration of the N cycle mode data generation circuit 20.
[0035]
The configuration of FIG. 4 is based on the premise that the same data is continuously read from the same address in the RAM 16 in two cycles, the first cycle and the second cycle. When data is read from the RAM 16 only in the first cycle, as shown in FIG. 6, in addition to the configuration of FIG. 4, selectors 43 and 44 and a flip-flop 45 for temporarily storing data are provided. Provide.
[0036]
In the first cycle, both the selector control signals FFU and FFL are set to 0, and the data read from the RAM 16 is stored in the flip-flop 45. At the same time, the selector control signals DMYU and DMYL are set to 1 and 0, respectively, the lower bit side outputs the current register value REGL, and the upper bit side outputs the RAM read data RAMU. In the second cycle, in order to output data from the RAM 16, FFU = FFL = 1 is set, and the data from the flip-flop 45 is selected by the selectors 43 and 44, and DMYU = DMYL = 1 is set to the data (RAMU and RAML) is output.
[0037]
FIG. 7 is a flowchart showing an example of an algorithm for RAM control and selector control by the controller 17.
[0038]
The controller 17 is activated when a data output request is received from the CPU side (Yes in step ST1) or when data to be output remains in the RAM 16 (Yes in step ST2). When a data output request is received (Yes in step ST1), based on the comparison by the comparison circuit 14, it is determined whether the Hamming distance between the output data of the current cycle and the output data of the previous cycle is a certain value or less. (Step ST4). If the Hamming distance is equal to or smaller than a certain value (Yes in step ST4), the selector 15 is controlled so that the internal output data is output to the outside (step ST5). At this time, the valid instruction signal is validated.
[0039]
When the comparison by the comparison circuit 14 indicates that the Hamming distance between the output data of the current cycle and the output data of the previous cycle is not less than a certain value (No in step ST4), the write pointer is written simultaneously with writing the current data to the RAM 16. Is increased by 1 (step ST6). Here, a read pointer and a write pointer are prepared for the RAM 16, and a range between the two pointers is an effective data range. When new data is written to the RAM 16, the write pointer is incremented by 1, and when one data is output, the read pointer is incremented by one. Thus, a FIFO (First in First Out) buffer is realized.
[0040]
When it is determined that the Hamming distance between the data read from the RAM 16 and the data of the previous cycle is equal to or less than the set value based on the comparison by the comparison circuit 19 (Yes in step ST7), the data of the RAM 16 is output I / O. The selector 15 is controlled so as to be output to the outside via the buffer 11. At this time, the valid instruction signal is validated. Further, by incrementing the read pointer by 1, the pending data in the RAM 16 is decreased by 1, and the data to be read next is indicated.
[0041]
If the comparison by the comparison circuit 19 indicates a Hamming distance that is equal to or greater than the set value (No in step ST7), data from the RAM 16 cannot be output, so the data of the previous cycle is output to the outside via the output I / O buffer 11. The selector 15 is controlled so as to do this (step ST9). At this time, the valid instruction signal is invalidated. Thereafter, it is checked whether or not the RAM 16 has overflowed (step ST10). If the RAM 16 has overflowed, a WAIT signal is sent to the CPU and the N cycle mode is entered (step ST11). When all the output pending data are output and the N cycle mode is completed, the controller 17 transmits an output success signal to the CPU.
[0042]
In the example of FIG. 7, even when there is no data output request (No in step ST1) and data remains in the RAM (Yes in step ST2), the N cycle mode is activated. This is a process necessary to prevent the data pending output from remaining in the RAM 16 indefinitely.
[0043]
If there is no data output request (No in step ST1) and no data remains in the RAM (No in step ST2), the data of the previous cycle is output to the outside via the output I / O buffer 11. The selector 15 is controlled (step ST3). At this time, the valid instruction signal is invalidated.
[0044]
FIG. 8 is a diagram showing a configuration in the case where the output data control circuit 10 according to the present invention is applied to an access operation portion from the CPU to the RAM.
[0045]
In FIG. 8, the output data control circuit 10 receives an address (n bits), data (m bits), and an output request from the CPU 51, and supplies an address & data and a valid instruction signal to the RAM 53. The input unit 52 is used when the CPU 51 reads data (m bits) from the RAM 53. Here, the CPU 51, the output data control circuit 10, and the input unit 52 are mounted on one semiconductor integrated circuit chip, and the RAM 53 is mounted on another semiconductor integrated circuit chip.
[0046]
Current noise due to switching of the I / O buffer becomes a problem only when driving an external load, and does not become a problem when switching the I / O buffer of the input circuit. Therefore, the data control circuit 10 according to the present invention is applied only to the output circuit side, and not applied to the input circuit side (input unit 52).
[0047]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
[0048]
The present invention includes the following contents.
(Supplementary note 1) an output I / O buffer for outputting output data supplied from a data supply source to the outside of the semiconductor integrated circuit;
A register for holding first output data output from the output I / O buffer in a first cycle;
Depending on the judgment whether or not the output data to be newly output from the output I / O buffer and the first output data held in the register differ by more than a predetermined reference, the first cycle is executed. Any of the second output data supplied from the data supply source in the subsequent second cycle, the third output data supplied from the data supply source before the second cycle, and the first output data Control circuit for controlling one of the output I / O buffers to output in the second cycle
A semiconductor integrated circuit comprising:
(Supplementary Note 2) In response to the determination that the difference between the second output data and the first output data is equal to or less than a predetermined number of bits, the control circuit receives the second output data from the output I / O buffer. When the second output data is output in the cycle, and the difference is not less than the predetermined number of bits, the difference between the third output data and the first output data is less than the predetermined number of bits. The third output data is output from the output I / O buffer in the second cycle in response to the determination of the output I / O buffer, and the output I / O buffer is output when the second or third output data is not output. The semiconductor integrated circuit according to appendix 1, wherein the first output data is output in the second cycle.
(Supplementary Note 3) A distance detector that calculates a Hamming distance between the output data to be newly output and the first output data held in the register;
A comparison circuit for comparing the distance calculated by the distance detector with a predetermined value;
A selector that selects any one of the first output data, the second output data, and the third output data and supplies the selected data to the output I / O buffer
The semiconductor integrated circuit according to appendix 1, wherein the control circuit controls the selector based on a comparison result of the comparison circuit.
(Supplementary Note 4) Further including a storage circuit, and when the control circuit does not output the second output data from the output I / O buffer in the second cycle, the second output data is stored in the storage circuit. The semiconductor integrated circuit according to appendix 1, wherein:
(Supplementary Note 5) The third output data is output data supplied from the data supply source and stored in the storage circuit by the control circuit in a cycle before the second cycle. The semiconductor integrated circuit as described.
(Supplementary note 6) Receive a plurality of output data continuously read from the storage circuit, generate dummy data inserted between the plurality of output data, and output the plurality of output data into which the dummy data is inserted The semiconductor integrated circuit according to appendix 1, further comprising a data generation circuit that supplies the I / O buffer.
(Supplementary Note 7) The data generation circuit generates dummy data in which one of two consecutive output data of the plurality of output data is the same as the upper half and the other and the lower half are the same, and the two output data 8. The semiconductor integrated circuit according to appendix 6, wherein the semiconductor integrated circuit is inserted between them.
(Supplementary Note 8) The data generation circuit includes a bit having the same bit value between two consecutive output data of the plurality of output data as it is, and a bit whose bit value is not the same between the two output data Is characterized in that dummy data in which half is identical to one of the two output data and the remaining half is identical to the other of the two output data is generated and inserted between the two output data. The semiconductor integrated circuit according to appendix 6.
(Supplementary Note 9) The data generation circuit generates a plurality of dummy data to be inserted between two consecutive output data of the plurality of output data, and starts the dummy data starting from one of the two output data. 7. The semiconductor integrated circuit according to appendix 6, wherein a series of data reaching the other of the two output data has a difference between two adjacent data equal to or less than a predetermined reference value.
【The invention's effect】
In the above semiconductor integrated circuit, it is determined how much the output data to be newly output from the output I / O buffer differs from the output data of the previous cycle held in the register, and the new data is determined according to the determination result. It controls whether the output data to be output is actually output or whether the output data is kept unchanged. As a result, the number of output I / O buffers that are simultaneously switched can be reduced, and current consumption can be reduced. In this way, the present invention provides a semiconductor integrated circuit that reduces potential fluctuations by reducing the number of output I / O buffers that are simultaneously switched to a predetermined number or less without requiring a special circuit on the receiving side. it can.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a configuration of an output data control circuit according to the present invention.
FIG. 2 is a diagram for explaining an example of an operation of an N cycle mode data generation circuit.
FIG. 3 is a diagram for explaining another example of the operation of the N cycle mode data generation circuit.
FIG. 4 is a circuit diagram showing an example of a configuration of an N cycle mode data generation circuit.
FIG. 5 is a circuit diagram showing another example of a configuration of an N cycle mode data generation circuit.
FIG. 6 is a circuit diagram showing still another example of the configuration of the N cycle mode data generation circuit.
FIG. 7 is a flowchart illustrating an example of an algorithm for RAM control and selector control by a controller.
FIG. 8 is a diagram showing a configuration when an output data control circuit according to the present invention is applied to an access operation portion from a CPU to a RAM.
[Explanation of symbols]
10 Output data control circuit
11 Output I / O buffer
12 registers
13 Distance detector
14 Comparison circuit
15 selector
16 RAM
17 Controller
18 Distance detector
19 Comparison circuit
20 N cycle mode data generation circuit
21 Valid indication signal output buffer

Claims (4)

An output I / O buffer for outputting output data supplied from a data supply source to the outside of the semiconductor integrated circuit;
A register for holding first output data output from the output I / O buffer in a first cycle;
Depending on the judgment whether or not the output data to be newly output from the output I / O buffer and the first output data held in the register differ by a predetermined reference or more, the first cycle is executed. Any of second output data supplied from the data supply source in the subsequent second cycle, third output data supplied from the data supply source before the second cycle, and the first output data look including one from the output I / O buffer control circuit for controlling to output in the second cycle or,
The control circuit responds to the determination that the difference between the second output data and the first output data is less than a predetermined number of bits from the output I / O buffer in the second cycle. Output second output data,
The output I / O buffer in response to a determination that the difference between the third output data and the first output data is less than the predetermined number of bits when the difference is not less than the predetermined number of bits. To output the third output data in the second cycle from
The semiconductor integrated circuit, wherein when the second or third output data is not output, the first output data is output from the output I / O buffer in the second cycle .   And further comprising a storage circuit, wherein the control circuit stores the second output data in the storage circuit when the second output data is not output in the second cycle from the output I / O buffer. The semiconductor integrated circuit according to claim 1. 3. The semiconductor according to claim 2, wherein the third output data is output data supplied from the data supply source and stored in the storage circuit by the control circuit in a cycle before the second cycle. Integrated circuit.   Receiving a plurality of output data continuously read from the memory circuit, generating dummy data to be inserted between the plurality of output data, and outputting the plurality of output data into which the dummy data has been inserted to the output I / O buffer 2. The semiconductor integrated circuit according to claim 1, further comprising a data generation circuit for supplying to the semiconductor integrated circuit.

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