JP4253473B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device such as a nonvolatile memory element having a quantum dot serving as an information charge storage portion in a gate insulating film of a floating gate portion and a manufacturing method thereof.
[0002]
[Prior art]
There is a “quantum dot” as a mechanism for expressing a quantum effect by confining an electron wave function in a three-dimensional minute space. By utilizing the quantum effect peculiar to such a quantum dot, it becomes possible to realize various new semiconductor devices different from the conventional one, and a memory can be given as an example.
[0003]
For example, an electrically erasable and writable memory (hereinafter referred to as “nonvolatile memory”) has a feature that it can retain information even when the power is turned off by accumulating electric charge. Since there are no such driving parts and is small and light, a low voltage drive and a large capacity are desired as a storage medium for portable information devices and the like. The inventor has already invented an application of quantum dots to this nonvolatile memory.
[0004]
FIG. 22 is a schematic diagram showing the floating gate structure of the floating gate type memory device already invented by the present inventors.
[0005]
That is, in this memory device, as shown in FIG. 6A, a tunnel oxide film 102 is formed on the surface of a silicon substrate 101, and a lower Si (silicon) quantum dot 103 and an upper tunnel oxide film 104 are formed thereon. The upper Si dot 105, the control oxide film 106, and the gate electrode 107 are laminated in this order. Further, source / drain regions 108 are formed on both sides of the laminated structure.
[0006]
The tunnel oxide film 102 can be formed by thermally oxidizing the substrate 101 and can have a thickness tox = about 3 nm. The lower Si quantum dots 103 are formed of silicon particles having a diameter of about 5 nm. On the other hand, the upper Si dot 105 is formed of silicon particles having a diameter of about 10 nm. The film thickness Tox of the control oxide film 106 can be about 30 nm.
[0007]
The arrangement relationship of the quantum dots provided in this floating gate type Si dot memory is as shown in FIG. 22B. The upper Si dot 105 is formed immediately above the lower Si quantum dot 103 and the upper tunnel oxide film 104 is formed. Are piled up.
[0008]
This floating gate type memory has a Si oxide via a double tunnel junction sandwiching a lower Si dot 103 that satisfies “Coulomb blockade condition (charge energy of one electron is larger than thermal fluctuation)” in a gate oxide film. Information electrons can be input / output between the surface of the substrate 101 and the upper Si dots 105.
[0009]
Therefore, in the memory retention state, an energy barrier is formed between the upper Si dot 105 and the Si substrate 101 by the Coulomb blockade effect and the quantum confinement effect in the lower Si dot 103, and information electrons can easily enter and exit. Disappears and memory retention time increases. If the energy barrier is raised by reducing the particle size of the lower Si dot 103, the tunnel probability decreases exponentially, so that the holding characteristics can be improved extremely efficiently.
[0010]
On the other hand, the writing and erasing of information electrons can be performed directly at the speed of the tunnel by making the gate voltage applied to the gate electrode 107 larger than 2ΔE (ΔE is an energy barrier at the lower dot) over the entire tunnel film. Is possible. However, if the energy barrier ΔE is increased in order to improve the holding time, the write / erase speed is gradually decreased.
[0011]
[Problems to be solved by the invention]
That is, in the element structure illustrated in FIG. 22, if the energy barrier ΔE is increased by reducing the size of the lower Si dot 103 in order to increase the memory retention time, the write / erase speed is further decreased. There was room for.
[0012]
The present invention has been made on the basis of recognition of such a problem, and an object of the present invention is to provide a semiconductor device using Si quantum dots that can efficiently improve the storage retention time without deteriorating the writing / erasing speed. And a manufacturing method thereof.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor, a first tunnel insulating film provided on the surface of the semiconductor, and a plurality of lower portions provided on the first tunnel insulating film. A quantum dot; a second tunnel insulating film provided on the lower quantum dot; and an upper quantum dot provided on the second tunnel insulating film and having a size larger than that of the lower quantum dot. A plurality of the lower quantum dots are selectively disposed under the upper quantum dots so as to overlap the upper quantum dots, A gap between a plurality of lower quantum dots is filled with an insulator, information charges are accumulated in the upper quantum dots, and writing and erasing of the information charges from the semiconductor to the upper quantum dots via the lower quantum dots. Done Between the upper quantum dot and the semiconductor; Information charge transfer path Is limited to those passing through the lower quantum dot overlapped with the upper quantum dot.
[0014]
According to the above configuration, since there are a plurality (N) of information charge injection / discharge paths between the upper dots and the channels in parallel, the write / erase speed is not deteriorated as compared with the case of one path. The energy barrier within the dots can be increased, and thus the memory retention time can be improved more efficiently.
[0015]
Here, at least two or more lower quantum dots may be included in a space in which the upper quantum dots are projected onto the surface of the semiconductor or conductor.
[0016]
By arranging a plurality of lower quantum dots so as to “overlap” with respect to the upper quantum dots in this way, the plurality of lower quantum dots can be reliably combined with one upper quantum dot, and the information charge It is possible to reliably secure a plurality of paths as the injection / discharge paths.
[0017]
The gap between the plurality of lower quantum dots is filled with an insulator, and charge transfer between the upper quantum dot and the semiconductor or conductor is limited to that passing through the lower quantum dot. For example, it is possible to reliably prevent the movement of information charges that leak in the space between the lower quantum dots.
In addition, if information charges are accumulated in the upper quantum dots and the information charges are written to and erased from the semiconductor or conductor via the lower quantum dots, the so-called “floating gate” is used. Can be formed.
[0018]
The upper quantum dots may be 1 × 10 6 on the second tunnel insulating film. ¹¹ cm ^-2 If it is provided with the above surface density, the average distance between the upper dots can be made equal to or less than the Coulomb shielding length, and the memory effect can be reliably obtained by reducing the channel current by Coulomb shielding.
[0019]
The upper quantum dots have a particle size of 30 nm or less. The “quantum dot” used in the present specification is a fine particle dot made of, for example, a conductor or a semiconductor, and a potential difference q / Cdot (q is an elementary charge and Cdot is a capacity of the dot) corresponding to an elementary charge is 25 meV at room temperature. It is desirable to be larger than that.
[0020]
Since the potential difference q / Cdot is about 25 meV when the particle size of the quantum dots is 30 nm, it is desirable to use a quantum dot particle size of 30 nm or less in the present invention.
[0021]
On the other hand, when the present invention is applied to a memory, the surface density of quantum dots required for a suitable memory operation is 1 × 10. ¹¹ cm ^-2 ~ (30nm) ^-2 As described above, this cannot be realized unless one or more dots enter an area of 30 nm square. If the particle size of the upper quantum dot is 30 nm or less, 1 × 10 ¹¹ cm ^-2 In view of obtaining the above surface density, the particle size is desirably 30 nm or less.
[0022]
On the other hand, a manufacturing method of a semiconductor device of the present invention is a manufacturing method of manufacturing any one of the above semiconductor devices, Forming an insulating film serving as the first tunnel insulating film on the surface of the semiconductor; forming an amorphous silicon thin film on the insulating film serving as the first tunnel insulating film; Forming an insulating film to be the second tunnel insulating film on the amorphous silicon thin film; an insulating film to be the first tunnel insulating film; and an insulating film to be the second tunnel insulating film When Sandwiched between Above Forming the plurality of lower quantum dots by heat-treating the amorphous silicon thin film; And forming a semiconductor dot to be the upper quantum dot on the insulating film to be the second tunnel insulating film, and the lower portion below the gap between the semiconductor dots to be the upper quantum dot Removing the dots by oxidation or etching; and It is provided with.
[0023]
According to this method, a large number of fine lower quantum dots arranged in substantially the same plane can be reliably and easily formed.
[0029]
In the present specification, the “tunnel insulating film” refers to a thin insulating film capable of fast electron transmission even at a low voltage by direct tunneling. For example, SiO ₂ In the case where is used as a main component, it is desirable that the film thickness is 0.5 nm or more and 3.5 nm or less. Also, SiO with a thickness of 3.5 nm or less ₂ If it is an insulating film having the same tunnel probability as the film, SiO ₂ What consists of materials other than these can also be used.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0031]
(First embodiment)
First, as a first embodiment of the present invention, a semiconductor device in which more than one lower quantum dot is provided below one upper quantum dot will be described.
[0032]
FIG. 1 illustrates a floating gate structure of a floating gate type memory device according to a first embodiment of the present invention.
[0033]
In the memory device of the present embodiment, a tunnel oxide film 12 is formed on the surface of a silicon substrate 11, and a plurality of lower Si (silicon) quantum dots 13, an upper tunnel oxide film 14, upper Si dots 15, and controlled oxidation are formed thereon. The film 16 and the gate electrode 17 are laminated in this order. Further, source / drain regions 18 are formed on both sides of the laminated structure.
[0034]
The tunnel oxide film 12 can be formed by thermally oxidizing the substrate 11 and can have a thickness tox = 3 nm. The lower Si quantum dots 13 are formed of silicon particles having a diameter of about 5 nm. On the other hand, the upper Si dot 15 is formed of silicon particles having a diameter of about 10 nm. The film thickness Tox of the control oxide film 16 can be about 30 nm.
[0035]
The arrangement relationship of the quantum dots provided in the floating gate type Si dot memory is as shown in FIG. 1B. One upper Si dot 15 is formed on the upper tunnel oxide on the plurality of lower Si quantum dots 13. They are stacked via the membrane 14.
[0036]
Also in this floating gate type memory, the surface of the Si substrate 11 and the upper Si dot 15 are connected via a double tunnel junction in which a plurality of lower Si dots 13 satisfying the “Coulomb blockade condition” are sandwiched in the gate oxide film. It has a structure that allows information electrons to enter and exit between.
[0037]
Here, “coulomb blockade condition is satisfied” means that the electrostatic energy of one electron (coulomb blockade energy: given as q / 2Cdot, where q is the elementary charge and Cdot is the capacitance of the quantum dot) is fluctuated. Than that. For example, when the quantum dot is a silicon nanocrystal having a particle size of about 5 nm, the capacitance Cdot is about 1 aF, and the Coulomb blockade energy ΔE is as follows.
ΔE = q / 2Cdot = 80meV
Since the thermal energy at room temperature is about 25 meV, in this case, the Coulomb blockade condition is satisfied.
[0038]
In the quantum dot structure of the present invention, since a plurality of (N) lower dots 13 are provided for one upper dot 15, compared with a case where only one lower dot 13 is provided. When the energy barriers ΔE of the lower dots 13 are all the same, N injection / discharge paths are provided, and a write / erase speed that is N times faster can be obtained. In other words, at the same write / erase speed, the present invention in which N lower dots 13 are provided can increase the energy barrier ΔE compared to the case of one illustrated in FIG. At this time, since the memory retention time increases exponentially with respect to ΔE, it increases very efficiently. That is, by increasing the number of paths N times, the energy barrier ΔE can be increased without changing the write / erase speed at all, so that the memory retention time can be improved exponentially.
[0039]
As described above, in the quantum dot floating gate type memory device of the present invention, a quantum dot structure in which one upper Si dot 15 is stacked on a plurality of lower Si dots 13 is used as a floating gate. Charging / discharging to a certain upper dot is performed via a double tunnel junction sandwiching Si nanoparticles satisfying the Coulomb blockade condition.
[0040]
In order to show that the memory element of the present invention is superior in storage retention characteristics at the same write / erase speed as compared with the prior art, first, the operation and effect obtained in the structure of FIG. 22 will be described.
[0041]
FIG. 23 is a schematic diagram of a semiconductor device as a comparative example for the structure shown in FIG. In this figure, the same elements as those described above with reference to FIG. That is, FIG. 23 shows a dot memory having only one tunnel oxide film 102.
[0042]
In the structure illustrated in FIG. 22, unlike the dot memory having only one tunnel oxide film illustrated in FIG. 23, electrons enter and exit by the energy barrier ΔE at the lower Si dot 103 sandwiched between the double tunnel junctions. Is suppressed and the memory retention time is improved.
[0043]
FIG. 2 is a schematic diagram showing energy bands in the vicinity of the quantum dots in the structure of FIG. 23 and the structure of FIG. 2A shows the energy band in the structure of the comparative example (FIG. 23), and FIG. 2B shows the energy band in the structure shown in FIG.
[0044]
It can be seen that the energy barrier ΔE is obtained in the double quantum dot structure shown in FIG. This energy barrier ΔE is due to the quantum confinement effect and the Coulomb blockade effect at the lower dot 103.
[0045]
FIG. 3 is a schematic diagram showing an energy band in the vicinity of a quantum dot at the time of writing / erasing. 3A shows an energy band in the structure of the comparative example (FIG. 23), and FIG. 3B shows an energy band in the structure shown in FIG.
[0046]
In the case of the double dot structure, when writing and erasing, as shown in FIG. 3B, if an area where the voltage Veff between the upper dot 15 and the channel is larger than 2ΔE is used, Since there is no energy barrier, fast writing / erasing can be performed.
[0047]
The most common orthodox theory for calculating the tunnel current of a double junction shows that the tunnel probability suppressed by ΔE of the double dot memory and the tunnel probability when only one thin oxide film of the single dot memory exists. The ratio is as shown in FIG. Here, the upper horizontal axis in FIG. 4 represents the particle diameter of the corresponding lower Si dot 13 (103).
[0048]
In the holding state (Veff to 0 V), the tunnel probability ratio P (single) / P (double) is given by the following equation.
P (single) / P (double) = (2 kT / ΔE) sinh (ΔE / kT)
Here, k is a Boltzmann constant, and T is room temperature (300K). By reducing the size of the lower dot 103 and increasing ΔE, the tunnel probability can be suppressed exponentially, so that the retention time can be dramatically improved.
[0049]
For example, when the diameter of the lower Si dot 13 is about 5 nm, ΔE is 80 meV energy due to Coulomb blockade and the energy due to quantum confinement effect is 0.12 eV, so that ΔE = 0.2 eV in total, and Veff = 0V tunnel From the probability ratio, it can be seen that the memory retention time is improved several hundred times.
[0050]
In the write / erase state (typical Veff = 1V> 2ΔE), the tunnel probability ratio P (single) / P (double) is given by the following equation.
P (single) / P (double)
= (Veff / Rt) / ([Veff-2ΔE] / 2Rt)
= 2 / (1-2ΔE)
That is, if the size of the lower dot 103 is reduced and ΔE is increased, the tunnel probability is not as significant as in the holding state, but also decreases, so that the write / erase speed is decreased. For example, when the diameter of the lower dot 103 is made smaller than 4 nm, the write / erase speed is reduced by about 10 times.
[0051]
The structure of the present invention in which a plurality (N) of lower dots 13 are provided directly below the upper dots 15 as shown in FIG. Here, the problem is that, as shown in FIG. 22, when the number of the lower dots 103 is one, when N is the number of the present invention, which can improve the holding time better at the same write / erase speed? That's what it means.
[0052]
The same write / erase speed in one case (FIG. 22) and plural cases (FIG. 1) means that the tunnel probabilities are the same at the same voltage Veff = 1V (> 2ΔE). That is, the following equation is established.
P (N) / P (1) = N (1-2ΔE (N)) / (1-2ΔE)
= 1
Here, ΔE is an energy barrier when there is one lower dot 103 in the structure of FIG. ΔE (N) is an energy barrier when the number of lower dots 3 is N in the present invention. In the present invention, since the number of injection / release paths is N, the probability is simply N times, so the number of molecules on the right side of the above equation is N times. Thus, the following equation is established at the same writing / erasing speed.
ΔE (N) = (N−1 + 2ΔE) / (2N)
However,
ΔE (N) −ΔE = (1-2E) (1-1 / N) / 2
> 0
That is, it is important that ΔE (N) is larger than ΔE. This is because, in the present invention, as the probability increases by N times, there is a margin for increasing the energy barrier ΔE (N) with the same tunnel probability.
[0053]
FIG. 5 is a graph showing the dependence of ΔE on the number of lower dots 13. From the figure, it can be seen that as the number N of the lower dots 13 increases, the energy barrier ΔE at the same write / erase speed increases. Here, N = 1 corresponds to the structure illustrated in FIG. 22, and ΔE increases when N becomes a plurality of 2, 3, 4,... As in the present invention.
[0054]
Next, the improvement of the holding time will be described. As in the present invention, when N (plural) lower dots 13 are provided for one upper dot 15, the tunnel probability is equivalent to N times even in the holding state (Veff to 0V). . Therefore, the tunnel probability ratio P (single) / P (double) with the case where only one thin oxide film exists (FIG. 23) is given by the following equation.
P (single) / P (double)
= (1 / N) (2kT / ΔE (N)) sinh (ΔE (N) / kT)
The retention time is reduced to 1 / N times as long as N paths are provided. However, as shown in FIG. 5, since the energy barrier increases when the number of lower dots 13 is increased, the memory retention time is increased. Is improved exponentially, the memory retention time is expected to be better at the same write / erase speed in the present invention than in the prior art.
[0055]
FIG. 6 is a graph showing the dependence of the storage retention time on the number of lower dots when the writing / erasing speed is the same. As shown in FIG. 22, it can be seen that the memory retention time can be greatly improved when N is a plurality of 2, 3, 4,. That is, according to the present invention, a quantum dot structure in which one upper Si dot 15 is stacked on N (> 1) lower Si dots 13 is used as a floating gate rather than a case where N = 1. The memory retention time can be improved without degrading the erase speed.
[0056]
In order for the function and effect of the present invention to effectively contribute to actual memory characteristics, the structural unit (N lower dots 13 for one upper dot 15) illustrated in FIG. , It must exist with a certain surface density. The memory effect is manifested by a decrease in channel current due to Coulomb shielding by information charges of the upper dots 15. Accordingly, when the average interval between the upper dots 15 is larger than twice the Coulomb shielding length (approximately 15 nm), a portion not subjected to Coulomb shielding appears on the channel surface, and the memory effect is not sufficiently exhibited. Therefore, the structural unit (N lower dots 13 with respect to one upper dot 15) has an area density of 1 / (30 nm). ² ~ 1x10 ¹¹ cm ^-2 It is desirable to exist above. However, if the channel width is as narrow as the Coulomb shielding length, even at least one quantum dot structural unit in FIG. 1B can contribute to the memory effect.
[0057]
Further, since the effect of the present invention is caused by the N lower dots 13 increasing the tunnel probability by N times, it is desirable that the N lower dots 13 be provided so as to overlap the upper dots 15 as much as possible. . In addition, if a leak current flows in the gap between adjacent lower dots 13, the memory retention effect is weakened. Therefore, the gap between the lower dots is formed of an oxide film or a-Si (amorphous) as described later as a specific example. A high resistance material such as silicon) is desirable.
[0058]
The above description corresponds to the case where information charges enter and exit through the double tunnel junction sandwiching the lower dot 13 between the upper dot 15 and the semiconductor channel, but the information charge enters and exits through the multiple tunnel junction. The same applies to cases.
[0059]
7 and 8 are schematic views illustrating such a multiple tunnel junction. That is, FIG. 7 shows a structure in which multiple junctions are introduced in the configuration of FIG. 22, and one lower dot 13B and one lower dot 13A are provided in series immediately below one upper dot 15 to form a multiple tunnel. A junction is formed.
[0060]
On the other hand, FIG. 8 shows a structure in which multiple junctions are introduced in the configuration of FIG. 1, and a plurality of lower dots 13B and a plurality of lower dots 13A are provided in series immediately below one upper dot 15, A plurality of multiple tunnel junctions are formed.
[0061]
As illustrated in FIG. 8, the memory effect is improved by multiplying the number of information charge injection / discharge paths by several times with respect to one upper dot 15 as in the case described above. In short, if a plurality of injection / discharge paths are formed in parallel, the energy barrier on the way can be increased under the same write / erase speed conditions compared to when there is only one path, so that the holding time can be further improved. The same effect is obtained.
[0062]
FIG. 9 is a schematic diagram showing a cross-sectional structure of a memory having such a multiple tunnel junction. That is, in the memory shown in the figure, a plurality of lower dots 13B and a plurality of lower dots 13A are provided in series with respect to one upper dot 15, and a plurality of multiple tunnel junctions are formed.
[0063]
A memory having a floating gate having a structure as shown in FIG. 9 can be obtained, for example, by forming two Si (silicon) layers forming the lower dot 23 in the first embodiment described below.
[0064]
Further, as in the fourth embodiment described later, it is needless to say that the same effect can be obtained even in a structure in which the basic structure of FIG. In this case, an energy barrier in the middle lower dot 50 can be increased between the upper dot 55 and the middle lower dot 50 due to an N-fold tunneling probability difference, and between the middle lower dot 50 and the lower dot 53. Due to the N′-fold tunneling probability difference at, the energy barrier at the lower dot 53 can be increased, so that the memory retention characteristic can be improved more efficiently.
[0065]
Hereinafter, embodiments of the present invention will be described in more detail with reference to examples.
[0066]
(First embodiment)
First, as a first embodiment of the present invention, a floating gate type memory device having a quantum dot structure in which one upper Si dot is stacked on a plurality of lower Si dots will be described.
[0067]
FIG. 10 is a process cross-sectional view showing the main part manufacturing process of the semiconductor device according to the first example of the present invention. The main part will be described as follows.
[0068]
First, a thermal oxide film 22 having a thickness of tox = 2 nm is formed on a Si (silicon) substrate 21, and an amorphous silicon (a-Si) thin film is formed thereon with a thickness of about 4 nm by a CVD (Chemical Vapor Deposition) method. accumulate. Next, a 2 nm oxide film 24 is formed on the surface of the a-Si layer by dry oxidation at 700 ° C. for 3 minutes. As a result, the thickness of the a-Si layer is 3 nm, and a structure in which the upper and lower sides thereof are sandwiched between oxide films having a thickness of 2 nm is obtained. Further, when high-temperature annealing at 900 ° C. is performed in a nitrogen atmosphere, the a-Si layer becomes a silicon layer made of polysilicon grains 23 of about 3 nm, and the structure shown in FIG. 10A is obtained.
[0069]
Next, as shown in FIG. 10B, upper Si dots 25 having a particle diameter of about 8 nm are formed by LPCVD (Low Pressure Chemical Vapor Deposition).
[0070]
Next, as shown in FIG. 10C, a control oxide film 26 having a thickness of 10 nm is formed by LPCVD, and an n-thickness having a thickness of 200 nm, which becomes a gate electrode. ⁺ A polysilicon layer is deposited by CVD, and the gate electrode 27 is formed using the resist pattern as a mask. Furthermore, phosphorus (P) is dosed at 1 × 10 ¹⁵ cm ^-2 , By implantation at an incident energy of 15 KeV and annealing at 900 ° C. ⁺ Layer 28 is formed.
[0071]
In this manner, a floating gate type memory device having a quantum dot structure in which one upper Si dot 25 is stacked on a plurality of lower Si dots 23 can be formed.
[0072]
In the first embodiment described above, a-Si may remain between the lower Si dots 23 depending on the annealing time, but there are a plurality of Si microcrystalline dots below the upper dots 25. It is sufficient that many portions are made of Si microcrystals.
[0073]
In the present embodiment, the lower dot 23 exists between the adjacent upper dots 25, but a plurality of lower dots 23 exist immediately below the upper dot 25. Are the same, and even if there is a lower dot in the gap between the upper dots, the effect of the present invention is not lost.
[0074]
(Second embodiment)
Next, as a second embodiment of the present invention, a method of manufacturing a semiconductor device in which no lower dot is provided between adjacent upper dots will be described.
[0075]
FIG. 11 is a cross-sectional view of the main part showing the manufacturing method of this embodiment.
[0076]
First, a thermal oxide film 32 having a thickness of tox = 2 nm is formed on a Si substrate 31, and an amorphous silicon (a-Si) thin film is deposited thereon by 4 nm by a CVD method. Next, a 2 nm oxide film 34 is formed on the surface of the a-Si layer by dry oxidation at 700 ° C. for 3 minutes. As a result, the thickness of the a-Si layer is 3 nm, and a structure in which the upper and lower sides thereof are sandwiched between oxide films having a thickness of 2 nm is obtained. Furthermore, when high-temperature annealing at 900 ° C. is performed in a nitrogen atmosphere, the a-Si layer becomes a silicon layer made of polysilicon grains 33 of about 3 nm.
[0077]
Further, as shown in FIG. 11A, upper Si dots 35 having a particle diameter of 12 nm are formed by LPCVD.
[0078]
Next, when about 8 nm is oxidized by steam oxidation at 900 ° C., as shown in FIG. 11B, all of the lower Si dots 33 in portions other than directly below the upper Si dots disappear as oxide films.
[0079]
Thereafter, as shown in FIG. 11C, a control oxide film 36 having a thickness of 10 nm is formed by LPCVD, and an n-type film having a thickness of 200 nm to be a gate electrode. ⁺ A polysilicon layer is deposited by CVD, and the gate electrode 37 is formed using the resist pattern as a mask.
[0080]
Furthermore, phosphorus (P) is dosed at 1 × 10 ¹⁵ cm ^-2 , By implantation at an incident energy of 15 KeV and annealing at 900 ° C. to become a source / drain ⁺ Layer 38 is formed.
[0081]
In this manner, a floating gate type memory device having a quantum dot structure in which one upper Si dot 35 is stacked on a plurality of lower Si dots 33 can be formed.
[0082]
In the present embodiment, the lower dots in the gaps between the adjacent upper dots 35 are eliminated by oxidation, but the present invention is not limited to this. For example, as shown in FIG. Etching may be removed by a method such as RIE (Reactive Ion Etching).
[0083]
(Third embodiment)
Next, another method for manufacturing the semiconductor device of the present invention will be described as a third embodiment of the present invention.
[0084]
FIG. 12 is a process cross-sectional view illustrating the main part of the method for manufacturing a semiconductor device according to this embodiment.
[0085]
First, a thermal oxide film 42 having a thickness of tox = 2 nm is formed on a Si substrate 41, and an amorphous silicon (a-Si) thin film is deposited thereon by 4 nm by CVD.
[0086]
Next, a 2 nm oxide film 44 is formed on the surface of the a-Si layer by dry oxidation at 700 ° C. for 3 minutes. As a result, the thickness of the a-Si layer is about 3 nm, and a structure in which the upper and lower sides thereof are sandwiched between oxide films having a thickness of 2 nm is obtained. Further, when high-temperature annealing at 900 ° C. is performed in a nitrogen atmosphere, the a-Si layer becomes a silicon layer made of polysilicon grains (microcrystals) 43 of about 3 nm. At this time, assuming that the annealing time is short enough to leave a little a-Si 43a between the lower Si dots, the structure shown in FIG. 12A is obtained.
[0087]
Thereafter, when dry oxidation at 700 ° C. is performed, the microcrystal 43 is less likely to be oxidized due to surface stress. Therefore, as shown in FIG. 12B, only the a-Si 43a in the gap between the uncrystallized microcrystals is present. Oxidized.
[0088]
Next, as shown in FIG. 12C, upper Si dots 45 having a particle diameter of 8 nm are formed by LPCVD, and a control oxide film 46 having a thickness of 10 nm is formed thereon by LPCVD. Furthermore, n-thickness of 200 nm serving as a gate electrode ⁺ A polysilicon layer is deposited by the CVD method, and the gate electrode 47 is formed using the resist pattern as a mask. Also, phosphorus dose is 1 × 10 ¹⁵ cm ^-2 , By implantation at an incident energy of 15 KeV and annealing at 900 ° C., n serving as the source and drain ⁺ Layer 48 is formed.
[0089]
In this manner, a floating gate type memory device having a quantum dot structure in which one upper Si dot 45 is stacked on a plurality of lower Si dots 43 can be formed.
[0090]
Also in this embodiment, as described above with reference to the second embodiment, the lower dots 43 under the gap between the adjacent upper dots 45 can be eliminated by oxidation or etching. In this way, the structure shown in FIG. 12D is obtained.
[0091]
(Fourth embodiment)
Next, a semiconductor device having a structure in which quantum dots are stacked in a “nested shape” will be described as a fourth embodiment of the present invention.
[0092]
FIG. 13 is a cross-sectional view of the relevant part showing the method for manufacturing the semiconductor device of this example.
[0093]
Also in this embodiment, first, a thermal oxide film 52 having a thickness of tox = 2 nm is formed on a Si substrate 51, and an amorphous silicon (a-Si) thin film is deposited thereon by 4 nm by a CVD method.
[0094]
Next, a 2 nm oxide film 54 is formed on the surface of the a-Si layer by dry oxidation at 700 ° C. for 3 minutes. As a result, the thickness of the a-Si layer is 3 nm, and a structure is obtained in which the upper and lower sides are sandwiched between oxide films having a thickness of 2 nm. On top of that, an amorphous silicon (a-Si) thin film is deposited by 7 nm by CVD.
[0095]
Next, a 2 nm oxide film 59 is formed on the surface of the a-Si layer by dry oxidation at 700 ° C. for 3 minutes. As a result, as shown in FIG. 13A, the upper a-Si layer has a thickness of about 6 nm, and a structure in which the upper and lower sides are sandwiched between the oxide films having a thickness of 2 nm is obtained.
[0096]
Next, when high-temperature annealing at 900 ° C. is performed in a nitrogen atmosphere, as shown in FIG. 13B, the a-Si layer is composed of polysilicon grains 53 of about 3 nm and polysilicon grains 50 of about 6 nm. It becomes a silicon layer.
[0097]
Next, as shown in FIG. 13C, upper Si dots 55 having a particle diameter of 12 nm are formed by LPCVD. Further, a control oxide film 56 having a thickness of 10 nm is formed by LPCVD, and an n-type film having a thickness of 200 nm serving as a gate electrode is formed. ⁺ A polysilicon layer is deposited by CVD, and the gate electrode 57 is formed using the resist pattern as a mask. Furthermore, phosphorus dose 1 × 10 ¹⁵ cm ^-2 The n-type source / drain is implanted under the condition of an incident energy of 15 KeV and annealed at 900 ° C. ⁺ Layer 58 can be formed.
[0098]
In this way, as shown in FIG. 13C, the quantum dot structure in which one intermediate Si dot 50 is stacked on a plurality of lower Si dots 53 has a plurality of intermediate Si dots. A “nested” floating gate type memory device having a quantum dot structure in which one upper Si dot 55 was stacked on the dot 50 could be formed.
[0099]
Also in this embodiment, as described above with respect to the second embodiment, the intermediate dots 50 in the gap between the upper dots 55 and the lower dots 53 in the gap between the intermediate dots 50 may be eliminated by oxidation or etching. In this way, the structure shown in FIG. 13D is obtained.
[0100]
There may be a-Si remaining between the intermediate Si dots 50 depending on the annealing time, but as many Si microcrystal dots exist below the upper dots, many portions become Si microcrystals. It should be. As described above with reference to the third embodiment, the a-Si portion remaining in the gap between the intermediate dot 50 and the lower dot 53 may be oxidized by dry oxidation at 700 ° C.
[0101]
(Second Embodiment)
Next, a semiconductor device in which the “thickness” of the tunnel oxide films above and below the quantum dots is different will be described as a second embodiment of the present invention.
[0102]
FIG. 14 is a cross-sectional view showing the floating gate structure of the floating gate type memory device of this embodiment.
[0103]
That is, in the memory device of this embodiment, the lower tunnel oxide film 62 is formed on the surface of the silicon substrate 61, and the lower Si (silicon) quantum dots 63, the upper tunnel oxide film 64, and the upper Si quantum dots 65 are formed thereon. The control oxide film 66 and the gate electrode 67 are stacked in this order. Further, source / drain regions 68 are formed on both sides of the laminated structure.
[0104]
The floating gate type memory of this embodiment also has a double tunnel junction sandwiching the lower Si quantum dot 63 that satisfies the “Coulomb blockade condition (the charge energy of one electron is larger than the thermal fluctuation)” in the gate oxide film. Thus, information electrons can enter and exit between the surface of the Si substrate 61 and the upper Si quantum dots 65.
[0105]
In other words, in the memory retention state, an energy barrier is formed between the upper Si dot 65 and the Si substrate 61 by the Coulomb blockade effect and the quantum confinement effect at the lower Si dot 63, and information electrons can easily enter and exit. Disappears and memory retention time increases. If the energy barrier is raised by reducing the particle size of the lower Si dots 63, the tunnel probability decreases exponentially, so that the holding characteristics can be improved very efficiently.
[0106]
In the present embodiment, among the tunnel oxide films provided above and below the lower quantum dots 65, the lower tunnel oxide film 62 is formed to be thicker than the upper tunnel oxide film 64. .
[0107]
Specifically, for example, the thickness tox of the lower tunnel oxide film 62 provided on the surface of the silicon substrate 61 is set to 3.07 nm, and the lower Si quantum dots 63 having a diameter of about 5 nm are provided on the lower tunnel oxide film 62. An upper tunnel oxide film 64 having a thickness of 1.535 nm is provided. The diameter of the upper quantum dots 65 provided thereon can be, for example, about 10 nm.
[0108]
On this gate structure, n is formed via a control oxide film 66. ⁺ By providing a gate electrode 67 made of type polysilicon or the like and providing source / drain regions 68 on both sides of the substrate 61, a floating gate type Si dot memory device is obtained.
[0109]
In the quantum dot structure of this embodiment, unlike the comparative example illustrated in FIG. 22, the lower tunnel oxide film 62 provided closer to the channel side of the double tunnel oxide film is different from the upper tunnel oxide film. It is formed thicker than 64. For this reason, compared with the case where the thicknesses of the upper and lower tunnel oxide films are the same, in the charge retention state, carrier emission, which is the main cause of the deterioration of the memory retention characteristics in the Si quantum dots 62, is efficiently suppressed. Memory retention characteristics are improved. The sum of the tunnel resistances of the double tunnel junction in the present embodiment is the same as the case where the thicknesses of the upper and lower tunnel oxide films 102 and 104 are both 3 nm in the comparative example shown in FIG. Are the same.
[0110]
That is, according to the present embodiment, on the condition that the sum of the two upper and lower tunnel resistances is made substantially equal, the charge supply portion (channel) side of these tunnel oxide films is formed into a thick asymmetric double junction. The memory retention time can be improved without substantially changing the write / erase speed.
[0111]
In this embodiment, it is not always necessary to provide a plurality of lower quantum dots 62 below one upper quantum dot 65 as in the first embodiment, and one lower quantum dot 65 is provided below one upper quantum dot 65. Only the quantum dots 62 may be provided.
[0112]
Hereinafter, the operational effects obtained in the present embodiment will be described in more detail with specific examples. In the present embodiment, among the double tunnel oxide films of the floating gate type memory element, the thickness of the lower tunnel oxide film 62 on the channel side which is the charge supply unit is set to, for example, about 3.07 nm, while charge accumulation is performed. The thickness of the upper tunnel film 64 on the side (for example, the upper Si dot 65) side can be set to about 1.535 nm. In other words, the lower tunnel oxide film 62 is an asymmetric double tunnel junction that is twice as thick as the upper tunnel oxide film 64.
[0113]
First, memory retention in such an asymmetric double tunnel junction will be described. Carrier injection for floating gate memory storage using a very small charge storage part of nanometers, such as Si quantum dots and electron trapping levels due to defects in atomic bonds in SiN (dangling bonds) In this case, since the injection carrier existence probability directly under these minute charge storage portions is remarkably reduced in the subthreshold region, the injection rate is controlled, so that the carrier emission causes a larger memory retention deterioration.
[0114]
FIG. 15 is a graph illustrating carrier injection and emission characteristics in the Si dot memory. As can be seen from the figure, in the Si dot memory, the deterioration of the current ON / OFF ratio in the storage retention is generally more on the electron (carrier) emission side. Therefore, if the carrier emission can be suppressed more than the carrier injection, the memory retention characteristic can be improved more efficiently.
[0115]
FIG. 16 is a conceptual diagram illustrating carrier injection and emission leaks when the upper and lower tunnel film thicknesses are symmetric and asymmetric.
[0116]
As shown in FIG. 16, the effective energy barrier height in the memory retention state is equal to the energy difference ΔV that promotes the same information charge leakage, but in the symmetrical type (left side), both ΔE−ΔV during injection and emission. On the other hand, in the asymmetric double tunnel junction (right side) of the present invention, ΔE−ΔV / 3 at the time of emission is effectively higher than ΔE−2ΔV / 3 at the time of injection. That is, in the case where the upper and lower tunnel film thicknesses are symmetric, the memory retention for both injection and emission is exp [(ΔE−ΔV / 2) / kT] times (where k is a Boltzmann constant, T In the case of the asymmetric type of the present invention, the carrier injection is inferior to exp [(ΔE−2ΔV / 3) / kT] times, but the carrier release, which is the main cause of memory retention deterioration, is exp [(ΔE -ΔV / 3) / kT] times better. .
[0117]
FIG. 17 is a graph showing carrier injection / discharge characteristics in the symmetric type and the asymmetric type. That is, in the graph, the three characteristic lines extending upward in the horizontal direction represent carrier injection characteristics, and the three characteristic lines extending from the lower left to the upper right represent carrier emission characteristics. As can be seen from FIG. 17, according to the asymmetric structure of the present invention, the carrier emission time becomes longer and the memory retention characteristic is further improved.
[0118]
Next, the writing / erasing speed will be described. The dependence of the tunnel resistance on the tunnel oxide film thickness Tox can be approximated by the following equation.
exp [4π (2 mH) ^1/2 × Tox / h] = 10 Tox / (0.23 nm)
Here, m is an effective electron mass of 2.7 × 10 ^-31 About Kg, H is the barrier height of the oxide film of 3.1 eV, and h is the Planck's constant.
[0119]
Therefore, the tunnel resistance of the lower tunnel oxide film 62 having a thickness of 3.07 nm is twice that of the 3 nm oxide film, and the tunnel resistance of the upper oxide film 64 having a thickness of 1.535 nm is compared with that. Small enough to be ignored. As a result, the sum of the resistances of the double tunnel oxide films is the same for both the top and bottom of the present invention (asymmetric) and the prior art (symmetric), and the write / erase speed does not change substantially.
[0120]
In other words, under the condition that the sum of the tunnel resistances of the upper and lower two tunnel oxide films is equal, the channel side of the tunnel oxide film is a thick asymmetrical double junction without changing the write / erase speed at all. Memory retention time can be improved.
[0121]
As described above, the double dot memory of the present invention having an asymmetric tunnel film thickness can improve the storage retention without losing the write / erase speed as compared with the conventional symmetrical structure. it can.
[0122]
In order for the effect of the present invention to function effectively with memory characteristics, structural units such as the asymmetric double tunnel junction and the minute charge storage portion (upper Si dots 65) illustrated in FIG. It is desirable to exist at an areal density. The memory effect is manifested by a decrease in channel current due to Coulomb shielding by information charges of the upper dots 65. Therefore, when the average distance between the adjacent upper dots 65 is larger than twice the Coulomb shielding length (approximately 15 nm), a portion that is not subjected to Coulomb shielding appears on the channel surface, and the memory effect is not sufficiently exhibited. Become.
[0123]
In other words, the structural unit (asymmetric double tunnel junction + minute charge storage portion) is converted to surface density by 1 / (30 nm). ² ~ 1 × 1011cm ^-2 It is desirable to exist above. However, if the channel width is as narrow as the Coulomb shielding length, this is not the case because at least one structural unit can contribute to the memory effect.
[0124]
Hereinafter, according to a second embodiment of the present invention, a semiconductor memory device having an asymmetric double tunnel junction in which the tunnel oxide film thickness on the channel side is configured to be thicker than the tunnel oxide film thickness on the charge storage section side. Further details will be described with reference to the fifth to seventh embodiments.
[0125]
(Fifth embodiment)
FIG. 18 is a process cross-sectional view illustrating the main part of the semiconductor device manufacturing method according to the fifth embodiment of the present invention.
[0126]
In this embodiment, first, a thermal oxide film 72 having a thickness tox = 3.07 nm is formed on a Si substrate 71, and an amorphous silicon (a-Si) thin film 70 is deposited thereon by a CVD method by 6 nm. Next, an oxide film 74 having a thickness of 1.535 nm is formed on the surface of the a-Si layer 70 by dry oxidation at 700 ° C. for 1 minute. As a result, the thickness of the a-Si layer 70 becomes approximately 5 nm, and a structure is obtained in which oxide films 74 and 72 having thicknesses of 1.535 nm and 3.07 nm are provided above and below, respectively. Thereafter, the upper Si dots 75 having a particle diameter of about 15 nm are formed by LPCVD, whereby the structure shown in FIG. 18A is obtained.
[0127]
Next, when about 10 nm is oxidized by steam oxidation at 900 ° C., the lower Si dots 73 having a particle size of about 5 nm remain only under the upper Si dots 75, and the other a-Si thin films 70 are oxidized, and FIG. The structure shown in b) is obtained.
[0128]
Further, a control oxide film 76 having a thickness of 10 nm is formed by LPCVD. Then, an n-thickness of 200 nm serving as a gate electrode ⁺ A type polysilicon layer is deposited by CVD and patterned by using a resist pattern (not shown) as a mask to form a gate electrode 77. Furthermore, phosphorus (P) is, for example, a dose of 1 × 10 ¹⁵ cm ^-2 Then, by implanting under the condition of an incident energy of 15 KeV and annealing at 900 ° C., as shown in FIG. 18C, an n + -type region 78 to be a source / drain region can be formed.
[0129]
As described above, according to this embodiment, the thickness of the tunnel oxide film 72 on the channel side is about 3.07 nm and the thickness of the tunnel oxide film 74 on the charge storage section side is about 1.535 nm. A double quantum dot structure having a tunnel junction can be formed.
[0130]
In this embodiment, the upper quantum dots 75 may be regularly arranged in position, or may be of a single dot memory structure having only one upper dot 75 on the channel. In the specific example described above, the lower dots in the gaps between the upper dots 75 are eliminated by the oxidation process. Instead, the lower dots are removed by etching such as RIE using the upper dots 75 as a mask. It can be lost.
[0131]
Note that the area density of the quantum dots required for a suitable memory operation is 1 × 10 ¹¹ cm ^-2 ~ (30nm) ^-2 As described above, this cannot be realized unless one or more dots enter an area of 30 nm square. If the particle size of the upper quantum dots 75 is 30 nm or less, 1 × 10 ¹¹ cm ^-2 In view of obtaining the above surface density, the particle size is desirably 30 nm or less.
[0132]
(Sixth embodiment)
Next, a sixth embodiment of the present invention will be described.
[0133]
FIG. 19 is a process cross-sectional view illustrating the main part of the semiconductor device manufacturing method according to the sixth embodiment of the present invention.
[0134]
Also in this embodiment, first, a thermal oxide film 82 having a thickness tox = 3.07 nm is formed on a Si substrate 81, and an amorphous silicon (a-Si) thin film is deposited thereon by 4 nm by a CVD method. Next, an oxide film 84 having a thickness of 1.535 nm is formed on the surface of the a-Si layer by dry oxidation at 700 ° C. for 1 minute. As a result, the thickness of the a-Si layer is about 3 nm, and a structure is formed in which the upper and lower sides are sandwiched between oxide films having thicknesses of 1.535 nm and 3.07 nm, respectively.
[0135]
Next, when high temperature annealing at 900 ° C. is performed in a nitrogen atmosphere, the a-Si layer becomes a silicon layer made of polysilicon grains 83 of about 3 nm, and the structure shown in FIG. 19A is obtained.
[0136]
Thereafter, the upper Si dots 85 having a particle diameter of 8 nm are formed by LPCVD, whereby the structure shown in FIG. 19B is obtained.
[0137]
Further, a control oxide film 86 having a thickness of 10 nm is formed by LPCVD, and an n-thickness having a thickness of 200 nm to be a gate electrode is formed. ⁺ A type polysilicon layer is deposited by CVD, and a gate electrode 87 is formed by using a resist pattern (not shown) as a mask. Thereafter, phosphorus (P) is dosed, for example, at a dose of 1 × 10 ¹⁵ cm ^-2 , By implantation at an incident energy of 15 KeV and annealing at 900 ° C. ⁺ By forming the mold region 88, as shown in FIG. 19C, the semiconductor memory device having the asymmetric double quantum dot structure of the second embodiment of the present invention is formed.
[0138]
In the present embodiment, the lower dot 83 exists also below the gap between the adjacent upper dots 85, but the effect of this embodiment is not lost. Alternatively, as in the second embodiment described above with reference to FIG. 11, the lower dot group in the gap may be eliminated by oxidation or RIE.
[0139]
Although a-Si may remain between the lower Si dots 83 depending on the annealing time, there is no problem if many portions are Si microcrystals. Further, as in the third embodiment described above with reference to FIG. 12, the amorphous portion remaining between the lower Si dots can be eliminated by oxidation.
[0140]
Also in this embodiment, the upper quantum dots 85 may be regularly arranged in position, and a single dot memory structure having only one upper dot 85 on the channel is required for a suitable memory operation. The surface density of the quantum dots is 1 × 10 ¹¹ cm ^-2 ~ (30nm) ^-2 As described above, this cannot be realized unless one or more dots enter an area of 30 nm square. If the particle diameter of the upper quantum dot 85 is 30 nm or less, 1 × 10 ¹¹ cm ^-2 In view of obtaining the above surface density, the particle size is desirably 30 nm or less.
[0141]
(Seventh embodiment)
Next, a seventh embodiment of the present invention will be described.
[0142]
FIG. 20 is a process cross-sectional view showing the main part of the semiconductor device manufacturing method according to the seventh embodiment of the present invention.
[0143]
Also in this embodiment, first, a thermal oxide film 92 having a thickness tox = 3.07 nm is formed on a Si substrate 91, and an amorphous silicon (a-Si) thin film is deposited thereon by 4 nm by a CVD method. Next, an oxide film 94 of 1.535 nm is formed on the surface of the a-Si layer by dry oxidation at 700 ° C. for 1 minute. As a result, the thickness of the a-Si layer is about 3 nm, and a structure is formed in which the upper and lower sides are sandwiched between oxide films having thicknesses of 1.535 nm and 3.07 nm, respectively.
[0144]
Next, when high-temperature annealing at 900 ° C. is performed in a nitrogen atmosphere, the a-Si layer becomes a polysilicon grain (silicon layer made of 93) of about 3 nm, and the structure shown in FIG.
[0145]
Thereafter, as shown in FIG. 20B, a silicon nitride (SiN) film 95 having a thickness of 5 nm is deposited by LPCVD to form a floating electrode portion. As a result, a large number of interatomic bond defects (dangling bonds) are formed at the interface or inside of the SiN film 95, and the electron trapping levels formed by these defects can be used as the charge storage portion.
[0146]
A control oxide film 96 having a thickness of 5 nm is formed thereon by LPCVD. Furthermore, n-thickness of 200 nm serving as a gate electrode ⁺ A type polysilicon layer is deposited by CVD, and a gate electrode 97 is formed by using a resist pattern as a mask. Then, phosphorus (P) is changed to, for example, a dose amount of 1 × 10 ¹⁵ cm ^-2 The n-type source / drain regions are formed by implanting under the condition of an incident energy of 15 KeV and performing high-speed annealing at 1000 ° C. for about 10 seconds. ⁺ A mold region 98 is formed.
[0147]
In this way, as shown in FIG. 20C, a semiconductor having an asymmetric double tunnel junction in which the tunnel oxide film 92 on the channel side is formed thicker than the tunnel oxide film 94 on the charge storage section side. A memory device can be formed.
[0148]
In this embodiment, the control oxide film 96 may be omitted, and the gate electrode 97 may be directly stacked on the SiN film 95.
[0149]
Alternatively, the SiN film 95 does not have to be a continuous continuous film, and may be an aggregate of fine SiN particles 99 of about 10 nm as illustrated in FIG. At this time, as in the second embodiment or the fifth embodiment described above, a structure in which the lower Si dots 93 are provided only directly below the minute SiN particles 99 may be employed. Further, the fine SiN particles 99 may be regularly arranged in position, or may have a single dot structure.
[0150]
As described above, the first and second embodiments of the present invention have been described in detail with reference to specific examples. However, the present invention is not limited to these specific examples.
[0151]
For example, in the first to seventh embodiments described above, silicon is used as the semiconductor material. However, the present invention can be similarly implemented by using other semiconductor materials, such as germanium and various compound semiconductors. Can be used.
[0152]
In the first to seventh embodiments, silicon oxide is used as the tunnel insulating film. However, the present invention can be similarly implemented even when other insulating materials are used, and the same effects can be obtained. it can.
[0153]
In the first to seventh embodiments, the microparticles on the charge / discharge path sandwiched between the thin tunnel oxide films are Si nanocrystallites, but the same effect can be obtained even if other conductive materials are used. .
[0154]
Furthermore, in the first to seventh embodiments, the information charge supply source to the floating gate is a channel semiconductor, but the control gate electrode n ⁺ The same effect can be obtained by using silicon as a supply source.
[0155]
In the first to seventh embodiments, the floating gate memory based on the n-type MOSFET has been described as an example. However, the present invention can be similarly applied to a memory element based on the p-type MOSFET.
[0156]
Further, in the first to seventh embodiments, microcrystallization of the a-Si thin film by high-temperature annealing is used for forming the lower Si dots. You may make it by making many dots fall on a wafer. However, in that case, when upper Si dots several times larger in particle size are deposited on them, lower dots are formed as densely as there are a plurality of lower dots just below them as shown in FIG. Must.
[0157]
In the first to seventh embodiments, the formation positions of the upper quantum dots may be random or regularly arranged.
[0158]
Further, in the first to seventh embodiments, a single dot memory structure having only one upper dot on the channel is possible if the element size is reduced.
[0159]
Further, in the fifth to seventh embodiments, the case where the tunnel film thickness is asymmetric is exemplified by the case of the film thickness ratio of 2: 1. However, if the channel side is thicker, other ratios can be used accordingly. Similar effects can be obtained.
[0160]
Further, in the fifth to seventh embodiments, as means for forming the asymmetric structure of the upper and lower tunnel oxide films, not only the film thickness is adjusted, but also the upper and lower tunnel insulating films are selectively used by using different materials having different dielectric constants ε. May be formed. Even if it does in this way, the effect similar to having changed the effective oxide film thickness will be acquired.
[0161]
Further, in the fifth to seventh embodiments, the memory element charged and discharged through “a fine particle and a double tunnel junction sandwiching it” is exemplified, but as illustrated in FIG. Even in the structure of charging and discharging, the same effect can be obtained by making the channel-side tunnel film thicker.
[0162]
【The invention's effect】
As described in detail above, according to the first embodiment of the present invention, by providing a structure in which a plurality of lower dots are stacked on one upper dot, for example, when this is applied to a memory Since there are a plurality (N) of information electron injection / discharge paths between the upper dot and the channel in parallel, the write / erase speed is not deteriorated in the lower dot as compared with the case of one path. The energy barrier can be increased, and the memory retention time can be improved more efficiently.
[0163]
In addition, according to the second embodiment of the present invention, the charge retention characteristics are improved without degrading the write / erase speed by making the film thickness or dielectric constant of the upper and lower tunnel films sandwiching the quantum dots asymmetric. It becomes possible to make it.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a floating gate type memory device having a quantum dot structure in which one upper Si dot is stacked on a plurality of lower Si dots according to the present invention.
FIG. 2 is an energy band diagram in a memory retention state of a single-Si dot memory having only a single tunnel oxide film and a double-dot memory in which a lower Si dot and an upper Si dot are stacked.
FIG. 3 is an energy band diagram in a writing state of a single Si dot memory having only a single tunnel oxide film and a double dot memory in which a lower Si dot and an upper Si dot are stacked.
FIG. 4 is a graph showing retention time improvement and write / erase speed deterioration for a single-dot tunnel oxide-only single-Si dot memory in a double-dot memory with only one lower dot for one upper dot. It is.
FIG. 5 shows the number of lower dots at the same write / erase speed in a floating gate type memory having a quantum dot structure in which one upper Si dot is stacked on a plurality of lower Si dots according to the present invention. It is a graph showing the change of energy barrier height.
FIG. 6 shows the number of lower dots at the same write / erase speed in a floating gate type memory having a quantum dot structure in which one upper Si dot is stacked on a plurality of lower Si dots according to the present invention. It is a graph showing the change of holding time improvement.
FIG. 7 is a cross-sectional view of a multi-dot structure when there is one information charge injection / discharge path.
FIG. 8 is a cross-sectional view of a multi-dot structure when there are a plurality of injection / discharge paths according to the present invention.
FIG. 9 is a cross-sectional view of a semiconductor memory device having a multi-dot structure in a floating gate portion when there are a plurality of injection / discharge paths according to the present invention.
FIG. 10 is a cross-sectional view showing the main part of the manufacturing method of the semiconductor device according to the first example of this invention.
FIG. 11 is a cross-sectional view showing a main part of the manufacturing method of the semiconductor device according to the second example of the present invention.
FIG. 12 is a cross-sectional view showing a main part of the manufacturing method of the semiconductor device according to the third example of the present invention.
FIG. 13 is a cross-sectional view showing a main part of the manufacturing method of the semiconductor device according to the fourth example of the present invention.
FIG. 14 is a cross-sectional view illustrating a floating gate structure of a floating gate type memory device according to a second embodiment of the present invention.
FIG. 15 is a graph illustrating carrier injection and emission characteristics in a Si dot memory.
FIG. 16 is a conceptual diagram illustrating carrier injection and emission leaks when the upper and lower tunnel film thicknesses are symmetric and asymmetric.
FIG. 17 is a graph showing carrier injection / release characteristics in a symmetric type and an asymmetric type.
FIG. 18 is a process cross-sectional view illustrating the main part of the semiconductor device manufacturing method according to the fifth example of the present invention.
FIG. 19 is a process cross-sectional view illustrating the main part of the method of manufacturing a semiconductor device according to the sixth example of the present invention.
FIG. 20 is a process cross-sectional view illustrating the main part of the semiconductor device manufacturing method according to the seventh embodiment of the present invention.
FIG. 21 is a conceptual diagram showing a multiple tunnel junction.
FIG. 22 is a cross-sectional view of a double quantum dot structure having only one lower Si dot with respect to one upper Si dot and a semiconductor memory device having the same in a floating gate portion.
FIG. 23 is a cross-sectional view of a single Si dot memory device composed of only one tunnel oxide film.
[Explanation of symbols]
11, 21, 31, 41, 51 Si substrate
12, 22, 32, 42, 52 Tunnel oxide film
13, 23, 33, 43, 53 Lower Si quantum dot
14, 24, 34, 44, 54 Upper tunnel oxide film
15, 25, 35, 45, 55 Upper Si quantum dot
16, 26, 36, 46, 56 Controlled oxide film
17, 27, 37, 47, 57 Gate electrode
18, 28, 38, 48, 58 Source / drain
50 Intermediate Si quantum dots
59 Uppermost tunnel oxide film
61, 71, 81, 91, 101 Si substrate
62, 72, 82, 92, 102 Lower tunnel oxide film
63, 73, 83, 93, 103 Lower Si quantum dot
64, 74, 84, 94, 104 Upper tunnel oxide film
65, 75, 85, 95, 105 Upper Si quantum dot
66, 76, 86, 96, 106 Controlled oxide film
67, 77, 87, 97, 107 Gate electrode
68, 78, 88, 98, 108 Source / drain

Claims (6)

Semiconductors,
A first tunnel insulating film provided on the surface of the semiconductor;
A plurality of lower quantum dots provided on the first tunnel insulating film;
A second tunnel insulating film provided on the lower quantum dots;
An upper quantum dot provided on the second tunnel insulating film and having a size larger than that of the lower quantum dot;
With
A plurality of the lower quantum dots are selectively disposed under the upper quantum dots so as to overlap the upper quantum dots,
The gap between the plurality of lower quantum dots is filled with an insulator,
Accumulating information charges in the upper quantum dots,
The information charge is written to and erased from the semiconductor via the lower quantum dot and the information charge is transferred between the upper quantum dot and the semiconductor. The semiconductor device is limited to one that passes through the overlapped lower quantum dots.   The semiconductor device according to claim 1, wherein at least two or more lower quantum dots are included in a space in which the upper quantum dots are projected onto the surface of the semiconductor. 3. The semiconductor device according to claim 1, wherein the upper quantum dots are provided on the second tunnel insulating film with a surface density of 1 × 10 ¹¹ cm ⁻² or more. It said lower quantum dot semiconductor device according to any one of claims 1 to 3, characterized in that the Coulomb blockade satisfy size. The particle size of the upper quantum dot semiconductor device according to any one of claims 1 to 4, characterized in that at 30nm or less. A method of manufacturing a semiconductor device according to any one of claims 1 to 5,
Forming an insulating film to be the first tunnel insulating film on the surface of the semiconductor;
Forming an amorphous silicon thin film on the insulating film to be the first tunnel insulating film;
Forming an insulating film to be the second tunnel insulating film on the amorphous silicon thin film;
By heat treatment to the amorphous silicon thin film is sandwiched between the insulating film serving as the first tunnel insulating film and the insulating film serving as the second tunnel insulating film, forming a plurality of lower quantum dots Process ,
Forming a semiconductor dot to be the upper quantum dot on the insulating film to be the second tunnel insulating film;
Eliminating the lower dots under the gap between the semiconductor dots to be the upper quantum dots by oxidation or etching; and
A method for manufacturing a semiconductor device, comprising:

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