JP4254541B2 - Initialization circuit for semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit (mainly LSI), and more particularly, to an initialization circuit that reduces the waiting time of an external controller during initialization.

As is well known, the LSI needs to be initialized when the power is turned on. At the time of this initialization, not only initialization of the internal circuit but also initialization of an attached SDRAM (synchronous DRAM) or the like is necessary, and a predetermined time is required.
Conventionally, when an external CPU (central processing unit) accesses an LSI that is being initialized, a WAIT signal is returned from the LSI, and the CPU waits until the WAIT signal is released upon completion of initialization. Further, in order to prevent wasted time being wasted, the CPU previously holds the initialization time of the LSI in advance, and processing for accessing the LSI is performed after the time has elapsed.
As an initialization circuit for a conventional semiconductor integrated circuit, a circuit described in Patent Document 1 is known.
Japanese Patent Laid-Open No. 2002-9601

  The present invention has been made in consideration of the above circumstances, and the object thereof is to eliminate the need for special measures such as the external CPU holding the initialization time and to wait for the external CPU during the initialization process. An object of the present invention is to provide an initialization circuit for a semiconductor integrated circuit.

The present invention has been made to solve the above-described problems. The invention of the present application is an externally readable register in which one of the binary logic levels is set at the start of initialization, and the end of initialization. When a read request from the outside is received during initialization processing, a register in which the other of the binary logic levels is set is forcibly issued a predetermined signal indicating that initialization processing is in progress without issuing a wait signal And an initialization data output means for outputting to the semiconductor integrated circuit.

Further, the present invention is the initialization circuit of the semiconductor integrated circuit, a counter for counting the clock pulses supplied from the outside in the initialization processing, the internal clock generation circuit and the outer based on the count output of the counter And a means for initializing the attached memory circuit.

  According to the present invention, there is an advantage that it is not necessary to take special measures such as the external CPU holding the initialization time, and the external CPU does not have to wait during the initialization process.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an initialization circuit 1 according to an embodiment of the present invention. In this figure, 2 is an LSI incorporating the initialization circuit 1, 3 is an internal circuit of the LSI 2, 4 is an SDRAM attached to the LSI 2, and 5 is an external CPU. In the initialization circuit 1, 11 is an initialization control circuit, 12 is a 1-bit INIEND register, and 13 is a counter.

Next, the operation of the above circuit will be described with reference to the waveform diagram shown in FIG.
First, when the power supply voltage VDD rises (see FIG. 2 (a)), a clock pulse SYCK IN (FIG. 2 (c); time t1) and a reset signal RESET_N (FIG. 2 (b)) are supplied from an external circuit. The initialization control circuit 11 generates an internal clock pulse MCLK (FIG. 2G) synchronized with the clock pulse SYCK IN and outputs it to the internal circuit 3. At this time, the initialization control circuit 11 outputs an “L (low)” internal reset signal to the internal circuit 3, and also outputs an “L” PLL reset signal to the PLL 3 a of the internal circuit 3. 12 is set to “L” (FIG. 2 (H)). Here, the PLL 3 a is a circuit that generates an internal clock pulse used in the internal circuit 3.

  When about 1 μsec or more has elapsed from the time t1, the reset signal RESET_N rises to “H (high)”. When the reset signal RESET_N rises to “H”, the initialization control circuit 11 raises both the internal reset signal and the PLL reset signal to “H” to release the reset state (time t2). As a result, the PLL 3a starts preliminary oscillation (see FIG. 2F). When a predetermined time (PLL stabilization time) elapses from time t2 and time t3 is reached, frequency data is set in the PLL 3a, initialization of the PLL 3a is started, and the PLL 3a corresponds to the frequency data. It oscillates at the frequency that Thereafter, the output of the PLL 3a is supplied to each part of the internal circuit 3 as an internal clock pulse MCLK (see FIG. 2G).

  The initialization control circuit 11 outputs the clock pulse SYCK IN to the counter 13 at time t3, and thereafter the counter 13 counts up the clock pulse SYCK IN. Then, when the counter 13 counts 400,000 clock pulses SYCK IN (time t4), it is determined that the initialization of the PLL 3a is completed, and then the SDRAM 4 is initialized. Then, the initialization control circuit 11 determines that the initialization of the SDRAM 4 is completed when the counter 13 further counts 16384 pulses (time t5), and sets “H” in the register 12 (FIG. 2 (h)). ).

  The above is the operation of the initialization circuit 1 when the power is turned on. When the CPU 5 accesses during initialization (register 12 = “L”), the initialization control circuit 11 forcibly outputs All “0” in response to a read request, In this case, write processing is not performed on the register and the memory. Further, the wait state is immediately canceled by setting the WAIT signal to “H”. On the other hand, after the initialization is completed (register 12 = “H”), the CPU 5 is allowed to access the register and memory, and the WAIT signal is set to “L” depending on the internal state.

  When the external CPU 5 checks whether or not the initialization of the LSI 2 has been completed, it outputs a data request for the register 12 to the LSI 2. On the other hand, if the LSI 2 is being initialized, the WAIT signal is immediately canceled and data “0” is returned, so that the CPU 5 can know that the initialization is in progress without waiting time. If initialization is not in progress, data “H” in the register 12 is returned in response to a data request from the register 12, and the end of initialization can be known.

1 is a block diagram showing a configuration of an LSI including an initialization circuit 1 according to an embodiment of the present invention. FIG. 2 is a waveform diagram for explaining the operation of the initialization circuit 1 in FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Initialization circuit, 2 ... LSI, 3 ... Internal circuit, 3a ... PLL, 4 ... SDRAM, 5 ... CPU, 11 ... Initialization control circuit, 12 ... Register, 13 ... Counter.

Claims (3)

In an initialization circuit of a semiconductor integrated circuit accessed by an external control device,
Initialization control means for controlling initialization of the semiconductor integrated circuit;
A readable registers from the control unit of the external, the first level representing the in one in and initializing the binary logic level in the initialization beginning of the semiconductor integrated circuit is set, two in the initialization end A register in which a second level representing the completion of initialization, which is the other of the value logic levels, is set ,
When the initialization control means is in the process of initializing the semiconductor integrated circuit, when it receives a read request from the register, other register, or memory by an external control device, it does not issue a wait signal, and the register, An initialization circuit for a semiconductor integrated circuit , wherein the data constituted only by the first level is output to the external control device without accessing the other registers or the memory . When the initialization control means is in the process of initializing the semiconductor integrated circuit, if it receives a write request from the external control device to the register, other register, or memory, it sends a wait signal without performing a write process. 2. The initialization circuit for a semiconductor integrated circuit according to claim 1, wherein the initialization circuit is not issued .   When the initialization control means is after completion of initialization of the semiconductor integrated circuit, upon receipt of a read request from the register, other register, or memory by an external control device, the initialization control means depends on the state of the semiconductor integrated circuit. 3. The initialization circuit for a semiconductor integrated circuit according to claim 1, wherein a wait signal is issued and output to the external control device.

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