JP4255703B2 - Cascode power amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a cascode power amplifier that connects one drain of two transistors to the other source, and more particularly to a cascode power amplifier that amplifies a signal in a microwave band.
[0002]
[Prior art]
A high-frequency power amplifier using CMOS technology has a cascode connection between the drain of a grounded first transistor to which a high-frequency signal is input and the source of a second grounded transistor, and amplifies it from the drain of the second transistor. The high-frequency signal thus output is output. In a cascode power amplifier using an enhancement type transistor, the gate terminal of the second transistor is connected from the power supply terminal via an inductor and a resistor, and is the same as the power supply voltage (see, for example, Non-Patent Document 1).
[0003]
[Non-Patent Document 1]
2002 IT International International Solid State Conference Technical Paper Digest (2002 IEEE International Solid-State Circuits Digest of Technical Paper), February 6, 2002, Session 17 (Advanced RF Technology), 17.5
[0004]
[Problems to be solved by the invention]
When such a conventional enhancement-type cascode power amplifier is used under the condition that the output power is close to the saturation output power, the voltage applied to the gate of the second transistor is equal to the power supply voltage. Since the voltage is smaller than the drain-source voltage of the first transistor and the drain current of the second transistor is saturated first, there is a problem that the power amplifier cannot extract output power efficiently.
[0005]
Further, in order to achieve both high power gain and high output, when a high power gain transistor is used as the first transistor, the maximum applied voltage that can be applied between the drain and source is low in the high gain transistor. When connected, since the drain-source voltage of the first transistor exceeds the maximum applied voltage, the maximum output power is limited by the maximum applied voltage between the drain and source of the first transistor.
[0006]
An object of the present invention is to provide a cascode power amplifier capable of efficiently obtaining a high power output in a microwave band.
[0007]
Another object of the present invention is to provide a cascode power amplifier that achieves both high gain and high output and satisfies the drain-source breakdown voltage.
[0008]
[Means for Solving the Problems]
In the cascode power amplifier according to the present invention, the drain of the enhancement-type first transistor and the source of the enhancement-type second transistor are cascode-connected, a power supply voltage is applied to the drain of the second transistor, In a cascode power amplifier that applies an input to the gate of a transistor and obtains an output from the drain of the second transistor, the maximum applied voltage of the second transistor is greater than the maximum applied voltage of the first transistor, and the second transistor The voltage applied to the gate of the second transistor can be set from the outside of the cascode power amplifier, and the gate applied voltage of the second transistor is set lower than the power supply voltage.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
1 is a circuit diagram showing a configuration of a cascode power amplifier according to a first embodiment of the present invention. 2 shows a 1 dB compression output power (P1 dB) with respect to a gate applied voltage (VGS2) of the second transistor of the cascode power amplifier of FIG. 1, a drain-source voltage (Vds1) of the first transistor, and a second transistor. The drain-source voltage (Vds2) is shown.
[0010]
In the cascode power amplifier, the first transistor 1 and the second transistor 2 are cascode-connected to the drain 1D of the first transistor 1 and the source 2S of the second transistor 2. The first transistor 1 constitutes a common-source amplifier circuit, the second transistor 2 constitutes a common-base amplifier circuit, and these are connected in cascade. The first transistor 1 and the second transistor 2 are enhancement type, and the maximum applied voltage between the drain and the source is equal to 3.3V. The maximum applied voltage means the maximum applied voltage with little change over time even when always applied, and the maximum applied voltage is related to the definition of the semiconductor manufacturing process. For example, if it is a 0.35 μm tool, it is about 3.3 V, and if it is a 0.18 μm tool, it is about 1.8 V. However, this value is not a fixed value but an improved characteristic.
[0011]
Further, the cascode power amplifier receives a high frequency signal from the outside, and applies a voltage to apply a bias voltage from the outside to the input terminal 3 connected to the gate 1G of the first transistor 1 and the gate 2G of the second transistor 2. A terminal 4, a power supply terminal 5 for supplying the power of the cascode amplifier from the outside, an output terminal 6 connected to the drain 2D of the second transistor 2 and outputting a high-frequency signal to the outside, a power supply terminal 5 and a second transistor The inductor 7 inserted between the two drains 2D, and a ground terminal 9 connected to the ground 8 as a reference voltage of the cascode power amplifier and connected to the source 1S of the first transistor 1 are provided.
The high-frequency signal input from the input terminal 3 is input to the gate 1G of the first transistor 1, amplified by the first transistor 1 and the second transistor 2, and from the drain 2D of the second transistor 2 to the output terminal 6 Is output.
[0012]
A direct current of 3.3 V is applied to the power supply terminal 5 as a power supply voltage (Vcc). Each of the first transistor 1 and the second transistor 2 when the gate applied voltage VG2 applied to the gate 2G of the second transistor 2 is changed between the gate applied voltage VG1 of the first transistor and the power supply voltage Vcc. The changes in the drain-source voltages Vds1 and Vds2 are shown by broken lines 10 and 11 in FIG. The bias condition is that the gate applied voltage of the gate 1G of the first transistor 1 is such that the current value (Ids) of the drain-source current is 60 mA in the gate applied voltage VG2 applied to the gate 2G of the second transistor 2. Vg1 is adjusted. Vds2 of the second transistor 2 decreases as Vg2 increases, and becomes lower than the maximum applied voltage when Vg2 is 2.6 V or higher. On the other hand, Vds1 of the first transistor 1 increases as Vg2 increases, but is lower than the maximum applied voltage when Vg2 is in the range of 2.2V to 3.3V.
[0013]
2 shows the characteristic of 1 dB compression output power P1 dB at 5.6 GHz output from the output terminal 6 with respect to the gate applied voltage Vg2 to the gate 2G of the second transistor 2 in FIG. When the gate application voltage Vg2 of the second transistor 2 is 2.8 V, the 1 dB compression output power P1 dB is 16.9 dBm, which is the maximum value.
[0014]
Such a cascode power amplifier exhibits the maximum value of 1 dB compression output power by adjusting the gate application voltage of the second transistor between the power supply voltage Vcc and the gate application voltage of the first transistor from the outside, Can be taken out to the maximum.
[0015]
Embodiment 2. FIG.
FIG. 3 shows the 1 dB compression output power (P1 dB) with respect to the gate applied voltage (Vg2) of the second transistor of the cascode power amplifier according to the second embodiment of the present invention, and the drain-source voltage (Vds1) of the first transistor. And the drain-source voltage (Vds2) of the second transistor.
[0016]
The cascode power amplifier according to the second embodiment is different from FIG. 1 in that the first transistor having the maximum applied voltage lower than the maximum applied voltage of the second transistor 2 is used. The maximum applied voltage of the first transistor 1 is 2.6V, and the maximum applied voltage of the second transistor 2 is 3.3V.
A direct current of 3.3 V is applied to the power supply terminal 5 as a power supply voltage (Vcc). When the gate applied voltage Vg2 applied to the gate 2G of the second transistor 2 is changed between the gate applied voltage Vg1 of the first transistor 1 and the power supply voltage Vcc, the first transistor 1 and the second transistor 2 Changes in the respective drain-source voltages Vds1 and Vds2 are shown in FIG. 3 by broken lines 13 and 14, respectively. The bias condition is that the voltage Vg1 of the gate 1G of the first transistor 1 is adjusted such that the current value (Ids) of the drain-source current is 60 mA at the gate applied voltage Vg2 applied to the gate 2G of the second transistor. is doing. Vds2 of the second transistor decreases as Vg2 increases, and becomes lower than the maximum applied voltage when Vg2 is 2.4 V or higher. On the other hand, Vds1 of the first transistor increases as Vg2 increases. However, when Vg2 exceeds 3.1 V, the maximum applied voltage is exceeded.
[0017]
A broken line 15 in FIG. 3 shows the characteristic of 1 dB compression output power P1 dB output from the output terminal 6 with respect to the gate applied voltage Vg2 of the gate 2G of the second transistor 2 of the second embodiment. When the gate application voltage Vg2 of the second transistor 2 is 2.8 V, the 1 dB compression output power P1 dB is 16.8 dBm.
[0018]
Such a cascode power amplifier can obtain a high gain by using a transistor in which the maximum applied voltage of the first transistor is smaller than the maximum applied voltage of the second transistor, and the gate applied voltage of the second transistor is externally applied. To the power supply voltage Vcc and the gate application voltage of the first transistor, the maximum application voltage of the first transistor at 1 dB compression output power can be satisfied.
[0019]
Embodiment 3 FIG.
FIG. 4 shows the 1 dB compression output power (P1 dB) with respect to the gate applied voltage (Vg2) of the second transistor of the cascode power amplifier according to the third embodiment of the present invention, and the drain-source voltage (Vds1) of the first transistor. And the drain-source voltage (Vds2) of the second transistor.
[0020]
The cascode power amplifier according to the third embodiment is different from that shown in FIG. 1 in that the maximum applied voltage of the first transistor 1 is lower than that of the second embodiment. The maximum applied voltage of the first transistor 1 is 1.8V, and the maximum applied voltage of the second transistor 2 is 3.3V.
A direct current of 3.3 V is applied to the power supply terminal 5 as a power supply voltage (Vcc). When the gate applied voltage Vg2 applied to the gate 2G of the second transistor 2 is changed between the gate applied voltage Vg1 of the first transistor 1 and the power supply voltage Vcc, the first transistor 1 and the second transistor 2 Changes in the respective drain-source voltages Vds1 and Vds2 are shown in FIG. 4 by broken lines 16 and 17, respectively. The bias condition is that the voltage Vg1 of the gate 1G of the first transistor 1 is adjusted such that the current value (Ids) of the drain-source current is 60 mA at the gate applied voltage Vg2 applied to the gate 2G of the second transistor. is doing. Vds2 of the second transistor decreases as Vg2 increases, and becomes lower than the maximum applied voltage when Vg2 is 2.2 V or higher. On the other hand, Vds1 of the first transistor increases as Vg2 increases, but Vg2 is only 2.2 V and is lower than the maximum applied voltage. Therefore, the maximum applied voltage of the first transistor is satisfied when the gate applied voltage Vg2 of the second transistor 2 is 2.2V.
[0021]
4 shows the characteristic of 1 dB compression output power P1 dB output from the output terminal 6 with respect to the gate applied voltage Vg2 of the gate 2G of the second transistor 2 of the third embodiment. When the gate application voltage Vg2 of the second transistor 2 is 2.2 V, the 1 dB compression output power P1 dB is 15.1 dBm.
[0022]
Such a cascode power amplifier can obtain a high gain by using a transistor in which the maximum applied voltage of the first transistor is smaller than the maximum applied voltage of the second transistor, and the gate applied voltage of the second transistor is externally applied. To the power supply voltage Vcc and the gate application voltage of the first transistor, the maximum application voltage of the first transistor at 1 dB compression output power can be satisfied.
[0023]
Further, FIG. 5 shows the relationship between the maximum applied voltage (Vds max) of the first transistor and the linear power gain (Linear Gain). A cascode power amplifier using a transistor having a small maximum applied voltage as the first transistor can obtain a large linear power gain.
[0024]
Such a cascode power amplifier is suitable for the first transistor by adopting a higher definition tool than the second transistor, for example, the second transistor is a 0.35 μm tool and the first transistor is a 0.18 μm tool. A simple power amplifier can be obtained. An amplifier close to the output can be configured using a transistor with a high maximum applied voltage, and an amplifier close to an input can be configured using a transistor with a low maximum applied voltage.
[0025]
Embodiment 4 FIG.
6 is a circuit diagram showing a configuration of a cascode power amplifier according to a fourth embodiment of the present invention. FIG. 6 differs from FIG. 1 in that a capacitor is inserted between the gate and the ground terminal of the second transistor, and the description of the same is omitted.
[0026]
In FIG. 6, a capacitor 20 is inserted between the gate 2G of the second transistor 2 and the ground terminal 9 connected to the ground 8, and is connected to the ground in an alternating manner.
[0027]
Such a cascode power amplifier is grounded to ground, whereby the gate potential of the second transistor is fixed in an alternating manner, and the output power can be taken out efficiently.
[0028]
Embodiment 5 FIG.
FIG. 7 is a circuit diagram showing a configuration of a cascode power amplifier according to Embodiment 5 of the present invention. FIG. 7 includes two circuits of FIG. 6 symmetrically with respect to the power supply terminal 5 and the ground terminal 9.
In the cascode power amplifier, a pair of first transistors 1 a and 1 b are connected to a source 1 aS and 1 bS, and are connected from a ground terminal 9 to a ground 8. The sources 2aS and 2bS of the pair of second transistors 2a and 2b are cascode-connected to the drains 1aD and 1bD of the first transistors 1a and 1b, respectively. The drains 2aD and 2bD of the second transistors 2a and 2b are connected to the power supply terminal 5 via inductors 7a and 7b, respectively. The gates 1aG and 1bG of the first transistors 1a and 1b are connected to the input terminals 3a and 3b. The gates 2aG and 2bG of the second transistors 2a and 2b are connected to the gate voltage application terminals 4a and 4b, respectively, and a gate application voltage can be applied individually. Capacitors 20a and 20b are inserted between the gates 2aG and 2bG of the second transistors 2a and 2b and the ground terminal 9. The drains 2aD and 2bD of the second transistors 2a and 2b are connected to the output terminals 6a and 6b, respectively.
[0029]
The direct current condition of FIG. 7 is the same as that of the circuit of FIG. High-frequency signals having different phases are input to the input terminals 3a and 3b, amplified by the first and second transistors, and high-frequency signals having different phases are output from the output terminals 6a and 6b. On the other hand, in-phase noise components are amplified as in-phase signals, but the high-frequency signal is further amplified because the out-of-phase gain is larger than the in-phase gain.
[0030]
Such a cascode power amplifier can achieve high output of signal components by adopting a differential configuration.
[0031]
Embodiment 6 FIG.
FIG. 8 is a circuit diagram showing a configuration of a cascode power amplifier according to Embodiment 6 of the present invention. 8 shows that the gates 2aG and 2bG of the second transistors 2a and 2b of FIG. 7 are connected by a virtual ground point 21, the virtual ground point 21 and the gate voltage application terminal 22 are connected, and the virtual ground point 21. And a capacitor 20 is inserted between the ground terminal 9 and the ground terminal 9.
[0032]
In such a cascode power amplifier, the number of pads provided on a chip can be reduced and the size can be reduced by connecting the gates of two second transistors to one gate voltage application terminal.
[0033]
Further, by providing one capacitor between the virtual ground point and the ground terminal, the number of capacitors can be reduced, and the size can be reduced.
[0034]
Embodiment 7 FIG.
FIG. 9 is a circuit diagram showing a configuration of a cascode power amplifier according to Embodiment 7 of the present invention. FIG. 10 is an image diagram of the chip layout of the gate portion of the second transistor having the differential configuration shown in FIG.
FIG. 9 is different from FIG. 8 in that capacitors 20a and 20b are inserted between the gates 2aG and 2bG of the second transistors 2a and 2b of FIG. Since the others are the same, the description is omitted.
[0035]
In FIG. 10, capacitors 20a and 20b are provided near the gates 2aG and 2bG of the second transistors 2a and 2b. A wiring 23 is drawn out from the gates 2aG and 2bG and connected to the gate voltage application terminal 22.
[0036]
As shown in FIG. 10, by individually disposing a capacitor connected to the gate terminal of the second transistor having a differential configuration, the point grounded to the ground is close to the gate terminal, and the gate terminal is grounded in an AC manner. Inductance components due to the wiring layout can be reduced between the grounds, and the gate potential can be close to the ground potential.
[0037]
As a result, power loss due to the inductance component can be reduced, and the output of the power amplifier can be increased.
[0038]
Although an enhancement type field effect transistor such as a MOSFET has been described as a transistor, an enhancement type bipolar transistor such as a compound HBT containing SiBJT, SiGe BJT, or InGaP has the same effect.
[0039]
【The invention's effect】
The effect of the cascode power amplifier according to the present invention is that the drain of the enhancement type first transistor and the source of the enhancement type second transistor are cascode-connected, and a power supply voltage is applied to the drain of the second transistor, In a cascode power amplifier that applies an input to the gate of the first transistor and obtains an output from the drain of the second transistor, the maximum applied voltage of the second transistor is greater than the maximum applied voltage of the first transistor, The voltage applied to the gate of the second transistor can be set from the outside of the cascode power amplifier, and the gate applied voltage of the second transistor is set lower than the power supply voltage. Vcc and the gate applied voltage of the first transistor By matching the, the maximum value of 1dB compression output power can be taken out maximum output power.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a cascode power amplifier according to a first embodiment of the present invention.
2 shows a 1 dB compression output power (P1 dB) with respect to a gate applied voltage (Vg2) of a second transistor of the cascode power amplifier of FIG. 1; a drain-source voltage (Vds1) of the first transistor; The drain-source voltage (Vds2) of the transistor is shown.
FIG. 3 shows a 1 dB compression output power (P1 dB) with respect to a gate applied voltage (Vg2) of a second transistor of a cascode power amplifier according to a second embodiment of the present invention, and a drain-source voltage (Vds1) of the first transistor. And the drain-source voltage (Vds2) of the second transistor.
FIG. 4 shows a 1 dB compression output power (P1 dB) with respect to a gate applied voltage (Vg2) of a second transistor of a cascode power amplifier according to a third embodiment of the present invention, and a drain-source voltage (Vds1) of the first transistor. And the drain-source voltage (Vds2) of the second transistor.
FIG. 5 is a relationship diagram between a maximum applied voltage and a linear power gain of the second transistor of the present invention.
FIG. 6 is a circuit diagram showing a configuration of a cascode power amplifier according to a fourth embodiment of the present invention.
FIG. 7 is a circuit diagram showing a configuration of a cascode power amplifier according to a fifth embodiment of the present invention.
FIG. 8 is a circuit diagram showing a configuration of a cascode power amplifier according to a sixth embodiment of the present invention.
FIG. 9 is a circuit diagram showing a configuration of a cascode power amplifier according to a seventh embodiment of the present invention.
10 is an image view of the chip layout of the gate portion of the second transistor having the differential configuration of FIG. 9;
[Explanation of symbols]
1, 2 transistors, 3, 4 input terminals, 5 power supply terminals, 6 output terminals, 7 inductors, 8 grounds, 9 ground terminals, 10, 13, 16 second transistor drain-source voltages, 11, 14, 17 1 transistor drain-source voltage, 12, 15, 18 1 dB compression output, 19 linear power gain, 20 capacitor, 21 virtual ground point, 22 gate voltage application terminal, 23 wiring.

Claims (3)

The drain of the enhancement type first transistor and the source of the enhancement type second transistor are cascode-connected, a power supply voltage is applied to the drain of the second transistor, and an input is applied to the gate of the first transistor. In the cascode power amplifier that obtains output from the drain of the second transistor, the maximum applied voltage of the second transistor is larger than the maximum applied voltage of the first transistor, and is applied to the gate of the second transistor. A cascode power amplifier characterized in that the voltage can be set from the outside of the cascode power amplifier, and the gate application voltage of the second transistor is set lower than the power supply voltage. Two first transistors connected to each other at a source, and two second transistors connected to each of the two first transistors and having a drain connected to each other. In the differential cascode power amplifier that inputs a signal to the gate of the second transistor and outputs the signal from the drain of the second transistor, a ground terminal to which a capacitor connected to the gate of the second transistor is grounded is A cascode power amplifier characterized in that a common source terminal of one transistor is different from a ground terminal to be grounded . 3. The cascode power amplifier according to claim 2, wherein a capacitor connected to the gate of the second transistor having the differential configuration and a ground terminal are separately provided .

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