JP4257626B2 - Memory access device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory access device in which memory buffer control is applied to a virtual storage system.
[0002]
[Prior art]
A memory access device that accesses a ring in such a way that a device accesses a space between a start address and an end address in a memory space from the start address to the end address and repeatedly returns to the start address. It has been.
Such a method of using memory resources is often used as a ring buffer for temporarily holding data by data flow control or the like.
[0003]
By using such a ring buffer, memory resources can be used efficiently, and control of address translation is simplified.
In the computer architecture, there is a concept that a part of the main storage device is used and the program accesses the memory as a virtual continuous area. The virtual storage system is a system based on this concept, in which a device designates a logical address and refers to a predetermined address conversion table to convert the logical address into a physical address of the main storage device. A typical method is a paging method.
[0004]
This virtual storage method is generally performed by software control, but it can also be applied to ring buffer control by hardware control, and a ring buffer can be realized by dynamically rewriting the upper conversion table.
[0005]
[Problems to be solved by the invention]
By the way, in such a conventional memory access device, when two devices access the same memory space, it is considered that the memory space to be accessed is different between the input device for reading data and the output device for writing data. It is done. For this reason, it is necessary to provide a plurality of address conversion tables.
[0006]
In addition, when the address conversion table is configured with an F / F (flip-flop) circuit or the like for speeding up, it is necessary to rewrite the address conversion table, so that a plurality of devices commonly use the F / F circuit or the like. This is not possible and must be provided for each device. For this reason, the circuit scale becomes large.
Therefore, it is preferable to perform ring buffer control so that the circuit scale is not as large as possible.
[0007]
[Means for Solving the Problems]
The present invention adopts the following configuration in order to solve the above points.
<Configuration 1>
The memory access device according to the first aspect of the present invention virtualizes the memory space of the main storage device as a continuous area by converting continuous logical addresses into physical addresses of the memory space of the main storage device using an address conversion table. The virtual storage system is applied to a control system that accesses a predetermined memory space in the main storage device so as to circulate as a ring structure, and accesses the memory space of the main storage device. The address conversion table stores a plurality of addresses. And an indirect table for each device that requests access to the main storage device, and the indirect table specifies an address of the address conversion table. plural Address data is stored, and when the access from the corresponding device is completed, the address data stored in the specified table Table Updated to go around in size, The table size of the indirect table is smaller than the table size of the address conversion table, the total number of addresses of the plurality of address data in the indirect table is equal to the table size of the address conversion table, and the address data is The indirect table is updated to circulate in the total number of cycles. It is configured as follows.
[0008]
<Configuration 2>
In the memory access device according to the second aspect of the present invention, after the access of the device is completed, the indirect table update is performed so that the address data of the address conversion table stored in the indirect table circulates within a predetermined table size. Means.
[0009]
<Configuration 3>
In the memory access device according to the invention of claim 3, A virtual storage system that virtualizes the memory space of the main storage device as a continuous area by converting continuous logical addresses into physical addresses of the memory space of the main storage device using an address conversion table, and a predetermined memory in the main storage device In a memory access device for accessing the memory space of the main storage device by applying to a control method for accessing the space so as to circulate considering the space as a ring structure, an indirect table is provided for each device that requests access to the main storage device. The indirect table stores address data specifying the address of the address conversion table and is updated so that the stored address data circulates within the table size of the predetermined table when access from the corresponding device is completed. And after the end of access to the device, With an indirect table updating means for address data of the serial indirect table stored address conversion table to update the indirect table so as to surround in a predetermined table size, The indirect table updating means adds an indirect table table size to the address conversion table address data stored in the indirect table, and subtracts the addition data added by the addition means from the address conversion table table size. Subtracting means, and when the subtraction data is less than zero as a result of subtraction by the subtracting means, the address data in the stored address conversion table is rewritten to addition data, and when the subtraction data is zero, the stored address conversion Rewriting means for rewriting the address data of the table to zero.
[0010]
<Configuration 4>
In the memory access device according to the fourth aspect of the present invention, when the write request for writing data to the main storage device is from the write device and the read request for reading data from the main storage device is from the read device, the read request is sent to the main storage device. Access control means for controlling access to the writing device and the reading device so as to avoid access conflicts.
[0011]
<Configuration 5>
In the memory access device according to the invention of claim 5, the access control means compares the write address where the data is written by the write device with the read address where the data is read by the read device, and the main memory device Determining means for determining whether there is a writable area or readable data, and when the determining means determines that there is a writable area, a write request for permitting writing to the writing device A permission unit, and a read request permission unit that permits the read device to permit reading when it is determined by the determination unit that there is data that can be read and the write device does not request writing.
[0012]
<Configuration 6>
According to a sixth aspect of the present invention, there is provided a memory access device comprising a register table for previously calculating and storing data to be updated of address data stored in the indirect table.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described using specific examples.
<Specific example 1>
Specific Example 1 includes an indirect table for each device, and the device indirectly refers to the address conversion table, so that even when there are a plurality of devices having different access spaces, one address conversion table can be obtained. It is a thing.
[0014]
FIG. 1 is a block diagram illustrating a configuration of the first specific example.
The main storage device 100 is a memory having a real storage space for developing a program, for example.
[0015]
The upper address conversion table 200 is a table for converting a continuous logical address (virtual address) into a physical address (real address) of the main storage device 100 by a paging method, and includes a register that allows the CPU 500 to read and write data. Configured. In this register, the upper address of the usable area of the main storage device 100 is stored.
[0016]
The devices 300A and 300B are devices for reading from and writing to the main storage device 100, and each include a data transfer unit 301A.
In the first specific example, the device 300A is an input-only input device that captures data from the outside and writes it to the main storage device 100, and the device 300B is an output-only device that reads out the data written to the main storage device 100 and outputs it to the outside It will be described as an output device.
[0017]
The table reference unit 400 is a block that controls the devices 300A and 300B to refer to the upper address conversion table 200. The indirect tables 410A and B, the indirect table update units 420A and B, and the end address detection units 430A and B And an arbiter 440.
[0018]
The indirect tables 410A and 410B are tables that are provided so as to correspond to the devices 300A and 300B, respectively, and are configured by registers in which the CPU 500 can read and write data. The addresses of the upper address conversion table 200 are stored in the registers of the indirect tables 410A and 410B.
[0019]
The indirect table update units 420A and 420B are indirect table update means for updating the indirect tables 410A and B, respectively, and performing ring buffer processing.
Detailed configurations of the indirect tables 410A and 410B and the indirect table update units 420A and 420B will be described later.
[0020]
The arbiter 440 is a block for avoiding a memory access conflict of the devices 300A and 300B. The detailed configuration of the arbiter 440 will be described later.
The end address detection units 430A and 430B are blocks for detecting an end address indicating that the writing or reading of the devices 300A and 300B has ended, respectively, and detect the end address of the data output from the devices 300A and 300B. An end timing signal is output to the table updating units 420A and 420B.
[0021]
The CPU 500 is an arithmetic unit that controls the main storage device 100, the upper address conversion table 200, and the indirect tables 410A and B, and reads and writes data from and to the upper address conversion table 200 and the indirect tables 410A and B.
[0022]
Next, the configuration of the indirect table update units 420A and B and the indirect tables 410A and B will be described.
FIG. 2 is a block diagram showing the configuration of the indirect tables 410A and 410B and the indirect table update units 420A and 420B.
[0023]
Each of the indirect tables 410A and B of the first specific example includes four registers 411a to 411d. The addresses of the higher-order address conversion table are stored in the registers 411a to 411d, respectively.
The indirect table update units 420A and 420B include a write timing generation unit 421, a selector 422, and a calculation unit 423.
The write timing generation unit 421 receives the end timing signal from the end address detection unit 430A or B and creates a rewrite timing signal for rewriting the data in the indirect tables 410A and B, and outputs the rewrite timing signal to the registers 411a to 411d. To do.
[0024]
The selector 422 switches the output of the data of the registers 411a to 411d of the indirect tables 410A and B to the arithmetic unit 423.
The calculation unit 423 calculates update data.
[0025]
FIG. 3 is a block diagram illustrating a configuration of the calculation unit 423 of the first specific example.
The calculation unit 423 includes an adder 425, a subtracter 426, a comparator 427, and a selector 428.
[0026]
The adder 425 is an adding unit that inputs the data of the registers 411a to 411d and the indirect table length and adds the two data. The indirect table length is data indicating the sizes of the indirect tables 410A and B, and the indirect table length in the first specific example is “4”.
The subtractor 426 is subtracting means for subtracting the output data of the adder 425 from the upper address conversion table length in order to determine whether the output data of the adder 425 exceeds the upper address conversion table length. The upper address conversion table length is data indicating the size of the upper address conversion table 200.
[0027]
The selector 428 is controlled by the comparator 427 to selectively output one of the output data from the adder 425 and the output data from the subtractor 426.
The comparator 427 determines whether the addition data of the adder 425 is equal to the upper address conversion table length by comparing the subtraction data subtracted by the subtractor 426 with “0”, and the output data of the adder 425 is When it is not equal to the upper address conversion table length, the selector 428 is controlled so that the output data of the adder 425 is output from the selector 428, and when it is equal, the output data of the subtractor 426 is output.
The selector 428 and the comparator 427 correspond to rewriting means.
[0028]
Next, the configuration of the arbiter 440 will be described.
FIG. 4 is a block diagram illustrating a configuration of the arbiter 440 according to the first specific example.
The write address storage unit 441 is a block that holds an address obtained by adding 1 to the address written last in the indirect table 410A.
[0029]
The read address storage unit 442 is a block that holds an address obtained by adding 1 to the address read last from the indirect table 410B.
When a write request signal is input from the device 300A, the selector 443 selectively outputs one of the address from the device 300A that made the write request and the address held by the write address storage unit 441 as a write address. It is a block.
[0030]
When a read request signal is input from the device 300B, the selector 444 selects and outputs one of the address from the device 300B that made the read request and the address held by the write address storage unit 441 as a read address. It is a block.
[0031]
The address comparison unit 445 is a determination unit that determines whether there is a writable area or readable data by comparing the write address output from the selector 443 and the read address output from the selector 444, When it is determined that there is a writable area, a writable signal is output to the write request acceptance signal creation unit 446, and when it is determined that there is readable data, it can be read by the read request acceptance signal creation unit 447. Output a signal.
[0032]
The write request acceptance signal creation unit 446 outputs a write request permission that allows the device 300A to write data when a write request signal and a writable signal are input from the device 300A and the address comparison unit 445, respectively. Means. Also, the write request acceptance signal creation unit 446 outputs a writing in-progress signal to the read request acceptance signal creation unit 447 during data writing.
[0033]
When the read request reception signal creation unit 447 receives a read request signal and a read enable signal from the device 300B and the address comparison unit 445, respectively, and when the write request reception signal creation unit 446 does not output a writing signal, This is a read request permission means for outputting a read acceptance signal for permitting the device 300B to read data.
[0034]
<Operation>
In the paging method, when a program is expanded and operated on the main storage device 100, the program is divided into several pages having a certain length and arranged on the main storage device 100. Therefore, the area where the program is stored is usually discontinuous in order to secure memory resources.
Therefore, consecutive logical addresses are converted into physical addresses on the main storage device 100 using the upper address conversion table 200.
[0035]
FIG. 5 is an operation explanatory diagram of the first specific example.
In the specific example 1, for the sake of easy understanding, it is assumed that the program fits in a 256 × 4 size as shown in FIG.
Further, the main storage device 100 has a 32-bit address space, and one area is divided every 256 (8 bits), and an address space that can be used by the devices 300A and 300B is 10 bits. Are 7 areas of areas 0-6. Therefore, the upper address conversion table length is “7”. Here, the number of bits of one word is not particularly limited.
[0036]
In this case, since the address space of the program is 256 × 4, 8 + 2 = 10 bits. Since the lower 8 bits can be used as they are as the address of the main storage device 100, the upper 2 bits are converted.
[0037]
The upper 2-bit address of this program space becomes the address of the upper address conversion table 200. As for the size of the table, the number of bits per table address is the upper 24 bits of the main storage device 100, which is four (addresses). Further, the upper 24 bits of address data of areas 0 to 6 of the main storage device 100 are input to the registers 210 to 216 of the upper address conversion table 200, respectively.
[0038]
In this way, by converting the upper 2-bit address through the upper address conversion table 200 and using the lower address as it is, the program can be operated as if it was started from the address of area 0.
Specifically, in order to perform the address conversion, first, the upper addresses of the areas 0 to 6 of the main storage device 100 are stored in the registers 210 to 216 of the upper address conversion table 200, respectively. Areas 0 to 6 usable by the device are allocated to the registers 210 to 216 of the upper address conversion table 200. This is done by the program.
[0039]
After the assignment is performed in this manner, the indirect table 410A for the device 300A is initialized by the program.
In order to initialize the indirect table 410A, data “0” designating the register 210 of the higher-order address conversion table 200 is set in the register 411a of the indirect table 410A for the device 300A. Similarly, data “1” to “3” designating the registers 211 to 213 of the upper address conversion table 200 are set in the registers 411b to 411d of the indirect table 410A, respectively.
[0040]
The indirect table 410B for the device 300B is similarly initialized.
After initialization of the indirect table 410A, the device 300A is activated by a program to start an input operation.
When the device 300A starts an input operation and writes data to the main storage device 100, address conversion is performed.
[0041]
In the example of FIG. 5, for example, an address “0x2a5” (“0x” indicates hexa expression) is specified in hexa expression by the device 300A. At this time, since the upper 2 bits are “2”, the address of the indirect table 410A is “2”, and the data “2” of the register 411c is obtained. This data “2” becomes the address data of the upper address conversion table 200.
[0042]
Based on this address data “2”, data “0X000007” stored in the register of the higher-order address conversion table 200 is obtained.
Since this data “0X000007” is the upper 24 bits of address data of the main storage device 100, the address “0X000007a5” of the main storage 100 is based on this data “0X000007” and the lower 8 bits of data “0xa5” of the device 300B. Is obtained.
[0043]
Then, the data stored in the area 6 of the main storage device 100 is read by designating this address “0X000007a5”.
When the writing of data to the main storage device 100 is completed, the end timing of access is detected by the end address detector 430, and the end signal is input to the write timing generator 421 of the indirect table 410A.
[0044]
The indirect table updating unit 420A updates data in the indirect table 410A using this signal as a trigger.
The update is performed as follows.
First, the selector 422 is controlled, and the data in the register 411a of the indirect table 410A is input to the arithmetic unit 423.
[0045]
In the calculation unit 423, the indirect table length is added to this data by the adder 425.
For example, when the data stored in the register 411a is “0”, “4” is added to the data “0” to become “4”. At this time, the updated data “4” is stored in the register 411a.
[0046]
Similarly, the selector 422 is switched, and the data stored in the registers 411a to 411d of the indirect table 410A are sequentially updated.
When the data stored in the register of the indirect table 410A is “3”, the added value is “3” + “4” = “7”, which is equal to the upper address conversion table length. At this time, the selector 422 is switched by the comparator 427 and data “0” is output.
In this way, the indirect table 410A is updated so as not to exceed the area 6 of the main storage device 100.
[0047]
FIG. 6 is an explanatory diagram for explaining the transition of the indirect table 410A.
As shown in FIG. 6, in the state 1, the address data 0 to 3 of the higher-order address conversion table 200 are set in the registers 411a to 411d of the indirect table 410A, respectively. When the indirect table 410A is updated, the registers 411a to 411d of the indirect table 410A are rewritten to change the state 1 to the state 2. In this state 2, the indirect table 410A is further updated to the state 3 as shown in FIG. To change.
[0048]
When data is stored to such an extent that it can be read, the device 300B is activated next time. At this time, address conversion is performed in the same manner, and data is read out.
[0049]
When reading of data from the main storage device 100 by the device 300B is completed, the end timing of the read access is detected by the end address detecting unit 430 as in the case of the end of writing, and the end timing signal is written to the indirect table 410A. Input to the timing generator 421. This signal is used as a trigger to output a rewrite timing signal from the write timing generator 421, and the data in the indirect table 410A is updated.
[0050]
When a write request is made by the device 300A, or when a read request is made by the device 300B, memory access is controlled by the arbiter 440, and memory access contention is avoided.
[0051]
For example, when a write request signal is input from the device 300A to the arbiter 440 and a write request is made by the device 300A, the address comparison unit 445 compares the write address with the read address. When the write address is smaller than the read address, it is determined that there is a write area, and a write enable signal is output from the address comparison unit 445 to the write request acceptance signal creation unit 446.
[0052]
When this write enable signal is output to the write request acceptance signal creation unit 446, a write acceptance signal is output from the write request acceptance signal creation unit 446 to the device 300A, and data is written to the main storage device 100 by the device 300A. Is called.
[0053]
Similarly, when a read request signal is input from the device 300B to the arbiter 440 and a read request is made, if the write address is smaller than the read address, the address comparison unit 445 determines that there is data to be read, and the address comparison A write enable signal is output from the unit 445 to the write request acceptance signal creation unit 446. When no write request signal is output from the write request reception signal creation unit 446, a read reception signal is output from the read request reception signal creation unit 447 to the device 300B, and data is read from the main storage device 100 by the device 300B. Is done.
[0054]
On the other hand, when the write address is larger than the read address, the address comparison unit 445 determines that there is no write area even if a write request signal is input from the device 300A, and the address comparison unit 445 does not output a writable signal. Further, even if a read request signal is input from the device 300B, it is determined by the address comparison unit 445 that there is no data to be read, and no read enable signal is output. In this way, memory access contention is avoided, and data is not read by the device 300B before the device 300A writes data to the main storage device 100.
[0055]
<Effect of specific example 1>
As described above, according to the first specific example, the indirect tables 410A and B are provided for the devices 300A and 300B, and the upper address conversion table 200 is indirectly referenced. There is no need to provide it, and the circuit scale can be greatly reduced.
[0056]
Here, the circuit scale is compared between the case where the table for address conversion is composed of only the higher-order address conversion table and the case where the table is composed by adding an indirect table.
[0057]
In this case as well, the memory space of the main storage device is a 32-bit address space, the address space of one area is 8 bits, the address space accessible by the device is 10 bits, and the number of usable areas is seven.
[0058]
When each table is configured by an F / F circuit, one upper address conversion table is 24 × 7 bits. Since two devices are used when there are two devices, the number of F / F circuits 24 × 7 × 2 = 336 is required.
On the other hand, if an indirect table is provided, only one upper address conversion table is required, so the number of F / F circuits is 24 × 7 + 3 × 4 × 2 = 192, and the circuit scale can be reduced. .
[0059]
In Specific Example 1, since two devices are used, two indirect tables are required. However, the number of indirect tables is not limited to Specific Example 1. The table length can also be increased or decreased according to the access space of each device.
[0060]
Also, the upper address conversion table can be increased or decreased according to the number of usable areas of the main storage device, and the number of bits of each address in the table can be reduced by limiting the range of acquisition of the usable area of the main storage device. Is possible.
[0061]
For example, if the memory address space of the main storage device is 32 bits and the usable area is always limited to the second half of the address space of the main storage device, the most significant bit is always fixed, so the most significant bit at all addresses in the table One bit of can be omitted.
[0062]
Even when the device space is larger than the space of the usable area, the indirect table can be processed by setting the table length to match the device space.
For example, if the device address space is 4 areas and there are 3 areas that can actually be used, the contents of the indirect table can be set to “0”, “1”, “2”, “0”, etc. It can be used as a buffer.
[0063]
In addition, the calculation unit of the indirect table update unit can also be provided for the address of the indirect table, so that all of the indirect table can be updated simultaneously. On the other hand, by increasing the number of inputs of the selector of the indirect table update unit and making the write timing generation unit common to all devices, only one arithmetic unit for updating the indirect table of all devices is required.
[0064]
In the first specific example, the calculation unit of the indirect table update unit has a hardware configuration, but may be configured by software.
FIG. 7 is a flowchart showing the operation.
In step (step is indicated as “S” in the figure) 1, data of the indirect table 410A (or B) is input.
[0065]
In step 2, the data of the indirect table 410A and the indirect table length are added.
In step 3, this added value is compared with the upper address conversion table length.
When the added value is larger than the upper address conversion table length, the process proceeds to step 4 where the added value is subtracted from the upper address conversion table length.
[0066]
In step 5, this value is output.
If the added value exceeds the upper address conversion table length, the process proceeds to step 6 where the added value is substituted for variable B, and the process proceeds to step 5 to output variable B.
As described above, the calculation unit 423 can also be configured by software.
[0067]
<Specific example 2>
In the second specific example, in order to shorten the update time, a register table corresponding to each register of the indirect table is provided, and update data is calculated in advance and stored in the register table.
[0068]
FIG. 8 is a block diagram illustrating a configuration of the second specific example.
The indirect table update units 420A and 420B of the specific example 2 each include a register table 450 having writable registers 452a to 452d.
In addition, the same code | symbol is attached | subjected about the same element as the specific example 1, and description is abbreviate | omitted.
[0069]
<Operation>
Next, the update operation of the specific example 2 will be described.
In the second specific example, before the indirect table 410A (or B) is updated, the data in the register 411a of the indirect table 410A is read, and the update data is created by the calculation unit 423.
In the second specific example, the calculation unit 423 may be configured by hardware or software.
[0070]
Then, the calculation result is written into the register 452a of the register table 450.
Similarly, data is read from the registers 411b to 411d of the indirect table 410A, and the calculation result is written to 452b to 45d of each register table 450.
[0071]
When the rewrite timing signal is output from the write timing generator 421 when the indirect table 410A is updated, the data in the registers 452a to 452d of the register table 450 is simultaneously output and copied to the registers 411a to 411d of the indirect table 410A. The
[0072]
Note that the rewrite timing of the indirect table 410 is also notified to the CPU 500 using an interrupt signal or the like.
Copying from the register table 450 to the indirect table 410 usually ends in one clock.
After the copy is completed, the update data is written again in the register table 450 in preparation for the next update.
In this manner, a ring buffer is realized by rewriting the register table 450 and repeating copying from the register table 450 to the indirect table 410A.
[0073]
<Effect of specific example 2>
As described above, according to the second specific example, the register includes the register table 450 corresponding to each register of the indirect tables 410A and B, and the update data calculated in advance is simultaneously updated when the indirect tables 410A and B are updated. As a result, the update time can be greatly shortened. Therefore, the devices 300A and 300B can access the main storage device 100 at high speed and continuously.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a specific example 1;
FIG. 2 is a block diagram illustrating a configuration of an indirect table and an indirect table update unit according to the first specific example.
FIG. 3 is a block diagram illustrating a configuration of a calculation unit (indirect table update unit) of specific example 1;
FIG. 4 is a block diagram illustrating a configuration of an arbiter according to a specific example 1;
FIG. 5 is an operation explanatory diagram of a specific example 1;
FIG. 6 is an explanatory diagram showing transition of an indirect table in specific example 1;
FIG. 7 is a flowchart showing the operation when the arithmetic unit of the first specific example is configured by software.
FIG. 8 is a block diagram illustrating a configuration of an indirect table and an indirect table update unit according to specific example 2;
[Explanation of symbols]
100 Main memory
200 Upper address translation table
300A, B device
400 Table reference part
410 Indirect table
420 Indirect table update unit
440 Arbiter
450 register table
500 CPU

Claims (6)

A virtual memory system that virtualizes the memory space of the main storage device as a continuous area by converting continuous logical addresses into physical addresses of the memory space of the main storage device using an address conversion table, and a predetermined memory in the main storage device In a memory access device for accessing the memory space of the main storage device by applying to a control method for accessing the space so as to circulate considering the space as a ring structure,
The address conversion table stores a plurality of addresses ,
An indirect table is provided for each device that requests access to the main storage device, and the indirect table stores a plurality of address data designating addresses in the address conversion table, and is stored when access from the corresponding device is completed. Updated address data to circulate within the table size of the predetermined table,
The table size of the indirect table is smaller than the table size of the address conversion table,
The total number of addresses of the plurality of address data in the indirect table is equal to the table size of the address conversion table,
The memory access device , wherein the indirect table is updated so that the address data circulates in a cycle of the total number of addresses .   2. An indirect table updating means for updating an indirect table so that address data of an address conversion table stored in an indirect table circulates within a predetermined table size after the device access is completed. The memory access device described in 1. A virtual memory system that virtualizes the memory space of the main storage device as a continuous area by converting continuous logical addresses into physical addresses of the memory space of the main storage device using an address conversion table, and a predetermined memory in the main storage device In a memory access device for accessing the memory space of the main storage device by applying to a control method for accessing the space so as to circulate considering the space as a ring structure,
An indirect table is provided for each device that requests access to the main storage device, and the indirect table stores address data that specifies an address in the address conversion table, and is stored when access from the corresponding device is completed. The address data is configured to be updated so as to circulate within the table size of the predetermined table,
An indirect table update means for updating the indirect table so that the address data of the address conversion table stored in the indirect table circulates within a predetermined table size after the access of the device is completed;
The indirect table updating means includes an adding means for adding the table size of the indirect table to the address data of the address conversion table stored in the indirect table;
Subtraction means for subtracting the addition data added by the addition means from the table size of the address conversion table;
As a result of the subtraction by the subtracting means, when the subtraction data is less than zero, the stored address conversion table address data is rewritten to addition data, and when the subtraction data is zero, the stored address conversion table address data is changed. Rewriting means for rewriting to zero,
Features and to Rume memory access device further comprising a.   When the write request for writing data to the main storage device is from the write device and the read request for reading data from the main storage device is from the read device, the write is performed so as to avoid contention for access to the main storage device 4. The memory access apparatus according to claim 1, further comprising access control means for controlling access to the access device and the read device. The access control means compares the write address where the data is written by the write device and the read address where the data is read by the read device to determine whether there is a writable area in the main storage device. Determination means for determining whether or not there is,
When the determination means determines that there is a writable area, a write request permission means for permitting writing to the writing device;
The determination means determines that there is data that can be read, and a read request permission means that allows the read device to read when the write device does not request a write;
The memory access device according to claim 4, further comprising:   6. The memory access device according to claim 1, further comprising a register table that precalculates and stores data to be updated of address data stored in the indirect table. .

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