JP4273435B2 - Storage device and access method - Google Patents

Description

  The present invention relates to a storage device and an access method, and more particularly, to a storage device and an access method suitable for use in, for example, performing hierarchical coding in which an image is divided into a plurality of layers having different numbers of pixels.

  For example, the image data of the second resolution having a smaller number of pixels is formed as the image data of the high resolution as the image data of the lowest hierarchy or the first hierarchy, and further, the third data having a smaller number of pixels is formed. There is an encoding method in which image data of a hierarchy is formed and image data up to the highest hierarchy is formed in the same manner. Such encoding is called hierarchical encoding, and image data of each layer is displayed on a monitor having a resolution (number of pixels) corresponding to the layer. Therefore, the user can view the image data by selecting the image data corresponding to the resolution of the monitor that the user has from among the hierarchically encoded image data.

  By the way, when image data of a certain resolution is used as image data of the lowest hierarchy (first hierarchy) and image data of the upper hierarchy is sequentially formed and all of them are stored or transmitted as they are, the lowest hierarchy As compared with the case of storing only the image data, the storage capacity and the transmission capacity are required for the image data of the upper layer.

  Therefore, the present applicant has previously proposed a hierarchical encoding method for reducing such an increase in storage capacity and the like.

  That is, for example, it is assumed that an added value of 4 pixels of 2 × 2 pixels (horizontal × vertical) is an upper layer pixel (pixel value), and three layer hierarchical encoding is performed. In this case, as an image in the lowest layer, for example, as shown in FIG. 9A, when 8 × 8 pixels are considered, the upper left 2 × 2 pixels of 4 pixels h00, h10, h01, h11 The added value m0 is calculated, and this is set as one pixel at the upper left of the second hierarchy. Similarly, the addition value m1 of the upper right four pixels h20, h30, h21, h31, the addition value m2 of the lower left four pixels h02, h12, h03, h13, and the lower right four pixels h22, h32 of the image of the lowest hierarchy. , H23, and h33 are calculated, and each is set as one pixel at the upper right, lower left, and lower right of the second layer. Further, an addition value q0 of 4 pixels m0, m1, m2, and m3 of 2 × 2 pixels in the second layer is calculated, and this is set as a pixel of the image in the third layer, that is, the highest layer here.

  If all the pixels h00 to h33, m0 to m3, and q0 are stored as they are, the storage capacity is extra as much as the pixels m0 to m3 in the second hierarchy and the pixel q0 in the third hierarchy as described above. Etc. are required.

  Therefore, as shown in FIG. 9B, the pixel q0 in the third hierarchy is arranged, for example, at the position of the lower right pixel m3 among the pixels m0 to m3 in the second hierarchy. As a result, the second hierarchy is composed of pixels m0 to m2 and q0.

  Then, as shown in FIG. 9C, for example, the pixel h11 at the lower right of the pixels h00, h10, h01, and h11 of the first layer used for obtaining the pixel m0 of the second layer. Place at the position. Similarly, the remaining pixels m1, m2, and q0 in the second hierarchy are arranged in place of the pixels h31, h13, and h33 in the first hierarchy. The pixel q0 is not directly obtained from the pixels h22, h32, h23, and h33 in the first layer, but is arranged in the second layer instead of m3 obtained directly from them. Instead of arranging the pixel m3 at the position of the pixel h33, the pixel q0 is arranged.

  As described above, as shown in FIG. 9C, the total number of pixels becomes 16 pixels of 4 × 4, which is not different from the case of only the pixels in the lowest hierarchy shown in FIG. Therefore, in this case, an increase in storage capacity or the like can be reduced.

  Decoding of the pixels m3 and h33 replaced with the pixel q0 and the pixels h11, h31, and h13 replaced with the pixels m0 to m2 can be performed as follows.

  That is, since q0 is an added value of m0 to m3, the expression q0 = m0 + m1 + m2 + m3 holds. Therefore, m3 can be obtained by the equation m3 = q0− (m0 + m1 + m2).

  Since m0 is an added value of h00, h10, h01, and h11, the expression m0 = h00 + h10 + h01 + h11 holds. Therefore, h11 can be obtained by the equation h11 = m0− (h00 + h10 + h01). Similarly, h31, h13, and h33 can be obtained. Note that h33 is obtained after obtaining m3 as described above.

  By the way, in performing hierarchical encoding as described above, conventionally, in addition to a general-purpose memory (for example, SRAM (Static Random Access Memory), DRAM (Dynamic RAM), etc.) for storing the hierarchical encoding result. In addition, a delay circuit for performing a line delay of the pixels (pixel values) in the first layer is necessary.

  That is, for example, in the case shown in FIG. 9, in order to obtain the pixel m0 in the second hierarchy, it is necessary to calculate the expression m0 = h00 + h01 + h02 + h03, but in order to obtain the pixel m0 in the second hierarchy, The first-layer pixels h00, h10, h01, and h11 are necessary, and the image data is generally supplied to the memory in order from the top to the bottom in line units. The reading / writing of the image data with respect to the memory is also performed in such line units.

  Therefore, it is necessary to delay the line starting with h00 by one line, wait for the line starting with h01 to be supplied, calculate m0, and write to the memory of the line starting with h00 and the line starting with h01. There is.

  As described above, conventionally, in addition to the memory for storing the hierarchical encoding result, a delay circuit for performing line delay of the image data is necessary, and there is a problem that the apparatus becomes large.

  The present invention has been made in view of such a situation, and is intended to reduce the size of the apparatus.

  One aspect of the present invention is image data composed of a smaller number of pixels than the input image data from the input image data, and a plurality of pixels at a predetermined position among the pixels constituting the input image data. A value obtained by adding pixel values is used as a pixel value, and is used when hierarchical data, which is image data composed of one pixel determined corresponding to the plurality of pixels, is calculated and hierarchical encoding is performed. A storage device that stores the input image data and the hierarchical data, and is addressed by a first address corresponding to a horizontal position and a vertical position that specify pixel positions constituting the input image data; The first storage means for storing the pixel value of the input image data at the designated address, and a part of the bit string representing the first address. First processing data that is data in the middle of processing for calculating the pixel value of the hierarchical data from the pixel value of the input image data, or The input image not stored in the first storage means from the pixel value of the hierarchical data calculated using the first processing data and the pixel value of the input image data or the pixel value of the input image data In the first storage means calculated using the second processing data, which is data in the middle of processing for calculating the pixel value of the data, or using the second processing data and the pixel value of the input image data Second storage means for storing pixel values of the input image data that are not stored, and control of reading and writing of data to and from the first and second storage means That when together, a storage device and a control means for performing processing for calculating the pixel value of the processing or the input image data for calculating the pixel value of the hierarchical data for the data.

  The first storage means is divided into a plurality of blocks that can be simultaneously accessed based on addresses designated for each, and the second storage means is simultaneously designated based on the addresses designated for each. A plurality of accessible blocks, divided into the same number of blocks corresponding to each of the blocks of the first storage means, and the first block of the blocks of the second storage means; The pixel value of the first process data or the hierarchical data is stored, and the pixel value of the second process data or the input image data is stored in a second block of the blocks of the second storage means. Can be done.

  The first address designating a third block of the blocks of the first storage means and the second address designating the first block of the second storage means are simultaneously generated. By shifting the pixel position specified by the address specifying means and the first address by the pixel column specified based on the difference in the number of pixels of the input image data and the hierarchical data, the first address The address is a delayed address, and is represented by a first delay address designating a fourth block of the blocks of the first storage means and a part of a bit string representing the first delay address. The second delay address designating the second block of the second storage means is the same as that for generating the first address and the second address. May further comprises a delay addressing means for generating the.

  In each block of the first storage means, the number of individual storage areas corresponding to the designated address is determined based on the number of pixels constituting one screen of the input image data. The number of addresses that can be specified in the block can be subtracted.

  The control means designates the storage area of the second storage means designated by the second address generated by the address designation means by a plurality of the first addresses corresponding to the second address. A first process for writing pixel values of the first processing data or the hierarchical data obtained by adding data written to each of the storage areas of the first storage means, and the delay address designating means The pixel value of the hierarchical data stored in the storage area of the second storage means designated by the generated second delay address is read, and the second delay address is read from the pixel value of the hierarchical data The input image data stored in each of the storage areas of the first storage means specified by a plurality of the first delay addresses corresponding to The second storage data specified by the second delay address is the second processing data obtained by subtracting the pixel value or the pixel value of the input image data not stored in the first storage means. The second process of writing to the storage area of the means can be executed simultaneously.

  One aspect of the present invention is image data composed of a smaller number of pixels than the input image data from the input image data, and a plurality of pixels at a predetermined position among the pixels constituting the input image data. A value obtained by adding pixel values is used as a pixel value, and is used when hierarchical data, which is image data composed of one pixel determined corresponding to the plurality of pixels, is calculated and hierarchical encoding is performed. A storage device that stores the input image data and the hierarchical data, and is addressed by a first address corresponding to a horizontal position and a vertical position that specify a pixel position that constitutes the input image data; The first storage means for storing the pixel value of the input image data at the designated address, and a part of the bit string representing the first address. First processing data that is data in the middle of processing for calculating the pixel value of the hierarchical data from the pixel value of the input image data, or Pixel values of the hierarchical data calculated using first processing data and pixel values of the input image data, or pixels of the input image data not stored in the first storage means from the input image data Calculated using second processing data that is data in the middle of calculating the value, or using the second processing data and the pixel value of the input image data that is not stored in the first storage means. And an access method in a storage device comprising second storage means for storing pixel values of the input image data, respectively. At the same time as storing each of the values in the first storage means, the second storage means is data in the middle of processing for calculating the pixel value of the hierarchical data from the pixel value of the input image data. The first processing data, the hierarchical data calculated using the first processing data and the pixel value of the input image data, or the input image data not stored in the first storage means Second processing data, which is data in the middle of processing for calculating a pixel value of input image data, or the first storage calculated using the second processing data and the pixel value of the input image data An access method for storing pixel values of the input image data not stored in the means.

  FIG. 1 shows a configuration example of an embodiment of a storage device to which the present invention is applied.

This storage device is composed of, for example, a one-chip CMOS (Complementary Metal Oxide Semiconductor) or the like, and performs hierarchical encoding that forms, for example, a three-layer image having a different number of pixels from an input image input thereto. Has been made.

  That is, the address supply circuit 1 is supplied with a horizontal address or a vertical address as an address corresponding to the position in the horizontal direction or the vertical direction of the pixels constituting the image input to the storage device.

In the present embodiment, for example, as shown in FIG. 2, an image (digital image data) in which one screen is composed of 512 pixels in the horizontal direction and 512 lines in the vertical direction is input. Therefore, both the horizontal address and the vertical address are represented by 9 (= log ₂ 512) bits.

  The address supply circuit 1 processes the horizontal address and the vertical address supplied to the address supply circuit 1 as necessary, and supplies the processed addresses to the first hierarchy memory 2, the second hierarchy memory 3, and the third hierarchy memory 4. Yes. The address supply circuit 1 includes a horizontal address and a vertical address, a clock (not shown in FIGS. 3 to 6 and 8 described later), an R / W (Read / Write) signal, and a hierarchy flag. The address supply circuit 1 supplies addresses to the first hierarchy memory 2, the second hierarchy memory 3, and the third hierarchy memory 4 in synchronization with the clock. . Further, the address supply circuit 1 processes a horizontal address and a vertical address supplied thereto corresponding to the R / W signal and the hierarchy flag. Furthermore, the address supply circuit 1 supplies a predetermined control signal to the RMW circuit 5 as necessary.

  Here, the R / W signal is a signal for instructing reading of image data from the storage device or writing of image data to the storage device, and the hierarchy flag is used when reading an image stored in the storage device. For example, it is a 2-bit flag for instructing which one of the first to third layer images to be described later is read. Note that the image data is written to the first hierarchy memory 2, the second hierarchy memory 3, and the third hierarchy memory 4, for example, so that the R / W signal represents the writing. The hierarchy flag is ignored (meaningless). Further, reading is performed individually for each of the first hierarchy memory 2, the second hierarchy memory 3, and the third hierarchy memory 4, and therefore the hierarchy flag is valid only at the time of reading. However, it is possible to simultaneously read from the first hierarchy memory 2, the second hierarchy memory 3, and the third hierarchy memory 4. In this case, the hierarchy flag need not be used.

  The first hierarchical memory 2 stores the image data supplied from the RMW circuit 5 at the address specified by the address supply circuit 1, and reads out the image data stored at the address and outputs it to the RMW circuit 5. It is made to do. The first layer memory 2 stores the first layer image, that is, here, the image data input to the storage device as it is. Further, the first hierarchy memory 2 can store at least one screen of the first hierarchy image, that is, here, image data of 512 × 512 pixels as shown in FIG. ing. Further, the memory cells constituting the first hierarchy memory 2 have at least the same data length as the number of bits allocated to the pixels constituting the first hierarchy image. That is, when the pixels constituting the first layer image are represented by, for example, 8 bits, the memory cells constituting the first layer memory 2 have a data length of at least 8 bits.

The second hierarchical memory 3 stores the image data supplied from the RMW circuit 5 at the address specified by the address supply circuit 1, and reads out the image data stored at the address and outputs it to the RMW circuit 5. It is made to do. The second hierarchical memory 3 is configured to store the second hierarchical image. That is, in the present embodiment, for example, as in the case of FIG. 9, 1 pixel in the second layer is formed from 2 × 2 (horizontal × vertical) 4 pixels constituting the image in the first layer. The second layer memory 3 is configured to store a second layer image composed of such pixels. The second hierarchy memory 3 has a storage capacity capable of storing at least a second hierarchy image for one screen. In other words, since one pixel of the second layer is formed from 2 × 2 pixels of the first layer, one screen of the image of the second layer is 256 × 256 (= 512/2 × 512/2). It is composed of pixels. Therefore, the second hierarchy memory 2 can store at least a second hierarchy image having such a number of pixels. Further, the memory cells constituting the second hierarchy memory 3 have at least a data length that can store the pixels constituting the second hierarchy image without dropping them. That is, in the present embodiment, since the pixels of the first layer are represented by 8 bits, the pixels of the second layer which are four addition values of such 8-bit pixels are 10 (= log ₂ (2 ⁸ +2 ⁸ +2 ⁸ +2 ⁸ )) bits. Therefore, the memory cells constituting the second hierarchy memory 3 have a data length of at least 10 bits.

The third hierarchical memory 4 stores the image data supplied from the RMW circuit 5 at the address specified by the address supply circuit 1, and reads out the image data stored at the address and outputs it to the RMW circuit 5. It is made to do. The third hierarchy memory 4 is adapted to store the third hierarchy image. That is, in the present embodiment, for example, in the same manner as in FIG. 9, from 2 × 2 4 pixels constituting the second layer image, and accordingly, from 4 × 4 pixels constituting the first layer image, One pixel in the third hierarchy is formed, and the third hierarchy memory 4 stores a third hierarchy image composed of such pixels. The third hierarchy memory 4 has a storage capacity capable of storing at least a third hierarchy image for one screen. That is, in this case, since one pixel of the third layer is formed from 2 × 2 pixels of the second layer, one screen of the image of the second layer is 128 × 128 (= 256/2 × 256/2). It is composed of pixels. Therefore, the third hierarchy memory 4 can store at least a third hierarchy image having such a number of pixels. Further, the memory cells constituting the third hierarchy memory 4 have a data length that can store at least the pixels constituting the third hierarchy image without dropping digits. That is, in the present embodiment, since the second layer pixel is represented by 10 bits as described above, the third layer pixel, which is four addition values of such 10 bit pixels, is 12 (= log ₂ (2 ¹⁰ +2 ¹⁰ +2 ¹⁰ +2 ¹⁰ )) bits. Accordingly, the memory cells constituting the third hierarchy memory 4 have a data length of at least 12 bits.

  Note that a clock is supplied to the first hierarchy memory 2, the second hierarchy memory 3, and the third hierarchy memory 4, and data is read and written in synchronization with this clock. ing.

  The RMW circuit 5 writes image data supplied to the storage device in the first hierarchy memory 2 as a first hierarchy image. Further, the RMW circuit 5 performs a process of calculating a second layer image from the first layer image, and writes it in the second layer memory 3. Further, the RMW circuit 5 performs a process of calculating the third layer image from the first layer image (or the second layer image) and writes the third layer image in the third layer memory 4. The RMW circuit 5 is also configured to read out and output the image data stored in the first hierarchical memory 2, the second hierarchical memory 3, or the third hierarchical memory 4, respectively. The RMW circuit 5 is supplied with a clock, an R / W signal, a hierarchy flag, and a control signal output from the address supply circuit 1. The RMW circuit 5 synchronizes with the clock, and the R / W Various processes are performed based on the signal, the hierarchy flag, and the control signal.

  Next, the operation will be described with reference to FIGS.

  Here, as shown in FIG. 2 described above, one screen is composed of 512 × 512 pixels, and image data in which each pixel is represented by 8 bits is supplied to the storage device as an image of the first layer. Shall be. The image data is supplied by being sequentially scanned.

Further, the pixel constituting the first layer image is h (0, 0) in the upper left pixel, and the pixel in the x + 1th position from the left and the y + 1th position from the top is set to h (x , Y). Since the first layer image is composed of 512 × 512 pixels as described above, both x and y take integer values in the range of 0 to 511 (= 2 ⁹ −1).

Also, considering variables s and t that take integer values in the range of 0 to 255 (= 2 ⁹ / 2-1), the pixels constituting the second layer image are adjacent 2 × 2 pixels in the first layer. h (2s, 2t), h (2s + 1, 2t),
h (2s, 2t + 1), h (2s + 1, 2t + 1)
Is represented by m (s, t). Therefore, the formula
m (s, t) = h (2s, 2t) + h (2s + 1,2t) + h (2s, 2t + 1) + h (2s + 1,2t + 1)
... (1)
Holds.

Further, considering variables m and n taking integer values in the range of 0 to 127 (= 2 ⁹ / 4-1), the pixels constituting the third layer image are adjacent 2 × 2 pixels in the second layer. m (2m, 2n), m (2m + 1, 2n),
m (2m, 2n + 1), m (2m + 1, 2n + 1)
Value, that is, adjacent 4 × 4 pixels in the first layer
h (4m, 4n), h (4m + 1,4n), h (4m + 2,4n), h (4m + 3,4n),
h (4m, 4n + 1), h (4m + 1,4n + 1), h (4m + 2,4n + 1), h (4m + 3,4n + 1),
h (4m, 4n + 2), h (4m + 1,4n + 2), h (4m + 2,4n + 2), h (4m + 3,4n + 2),
h (4m, 4n + 3), h (4m + 1,4n + 3), h (4m + 2,4n + 3), h (4m + 3,4n + 3)
It is expressed as q (m, n). Therefore, the formula
q (m, n) = m (2m, 2n) + m (2m + 1,2n) + m (2m, 2n + 1) + m (2m + 1,2n + 1)
= h (4m, 4n) + h (4m + 1,4n) + h (4m + 2,4n) + h (4m + 3,4n)
+ h (4m, 4n + 1) + h (4m + 1,4n + 1) + h (4m + 2,4n + 1) + h (4m + 3,4n + 1)
+ h (4m, 4n + 2) + h (4m + 1,4n + 2) + h (4m + 2,4n + 2) + h (4m + 3,4n + 2)
+ h (4m, 4n + 3) + h (4m + 1,4n + 3) + h (4m + 2,4n + 3) + h (4m + 3,4n + 3)
... (2)
Holds.

The address supply circuit 1 has a combination of the horizontal address HA and the vertical address VA (HA, VA), for example, in both cases of data writing and reading, for example,
(0,0), (1,0), ..., (511,0),
(0, 1), (1, 1), ..., (511, 1),
・
・
・
(511,0), (511,1), ..., (511,511)
In this order (the order corresponding to the sequential scanning), the signals are supplied in synchronization with the clock.

  Further, each bit of the 9-bit horizontal address HA is represented as ha1, ha2,..., Ha8 (ha8 is the most significant bit) with its least significant bit ha0, and each bit of the 9-bit vertical address VA. Similarly, va0 is represented as va1, va2,..., Va8 (va8 is the most significant bit) with the least significant bit as va0.

  At the time of writing image data to the storage device, the first layer image is sequentially scanned and supplied to the RMW circuit 5 in synchronization with the clock, and accordingly, the address supply circuit 1 receives the horizontal address. It is assumed that HA and vertical address VA are supplied as described above.

  In this case, access to the first hierarchy memory 2 is performed as follows.

That is, as shown in FIG. 3, at the time of writing (when the R / W signal indicates writing), the address supply circuit 1 uses the horizontal address HA and the vertical address VA supplied thereto as they are. This is supplied to the address terminals (ADh, ADv) of the first hierarchy memory 2. On the other hand, the RMW circuit 5 writes the first layer image data supplied thereto into the memory cells (not shown) of the first layer memory 2 specified by the horizontal address HA and the vertical address VA. Thereafter, the same processing is performed, so that the first layer image for one screen composed of 512 × 512 pixels is stored in the first layer memory 2. That is, as a result, the addresses (0, 0), (1, 0),..., (511, 0),
(0, 1), (1, 1), ..., (511, 1),
...
(511,0), (511,1), ..., (511,511)
Includes the first layer pixel (pixel value)
h (0,0), h (1,0),..., h (511,0),
h (0, 1), h (1, 1), ..., h (511, 1),
...
h (511,0), h (511,1),..., h (511,511)
Are stored respectively.

  At the time of reading (when the R / W signal indicates reading), the address supply circuit 1 also supplies the horizontal address HA and the vertical address VA supplied thereto if the hierarchy flag indicates the first hierarchy. Is supplied to the address terminal of the first hierarchical memory 2 as it is. The RMW circuit 5 reads the first layer image data stored in the memory cell of the first layer memory 2 designated by the horizontal address HA and the vertical address VA, and the same processing is performed thereafter. Thus, a first layer image for one screen composed of 512 × 512 pixels is read from the first layer memory 2. That is, the first-layer image scanned sequentially is thereby output.

  Next, access to the second hierarchy memory 3 will be described.

  First, at the time of writing, as shown in FIG. 4, for example, the address supply circuit 1 has higher 8 bits ha1 to ha8 excluding the least significant bit ha0 as a part of the horizontal address HA supplied thereto. The upper 8 bits va1 to va8 excluding the least significant bit va0 as a part of the vertical address VA are supplied to the address terminals of the second hierarchical memory 3. Further, the address supply circuit 1 outputs the least significant bit ha0 of the horizontal address HA and the least significant bit va0 of the vertical address VA to the RMW circuit 5 as control signals.

  Therefore, for example, 2 × 2 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first layer as indicated by D1 in FIG. At any timing supplied to the RMW circuit 5, the address supply circuit 1 outputs a signal designating the same address (s, t) of the second hierarchy memory 3 to the second hierarchy memory 3. .

  On the other hand, in the RMW circuit 5, the first layer image data supplied thereto is input to the computing unit 13. The computing unit 13 is supplied with the output of the switch 12 in addition to the first layer image data, and the computing unit 13 adds them and supplies them to the writing unit 14. Yes.

  The switch 12 selects one of the terminals 12a and 12b corresponding to the output of the NOR gate 15, and the terminal 12a or 12b receives the output of the reading unit 11 or 0. Each is supplied. The NOR gate 15 is supplied with the least significant bit ha0 of the horizontal address HA from the address supply circuit 1 and the least significant bit va0 of the vertical address VA. Therefore, the output of the NOR gate 15 is the least significant bit. When both ha0 and va0 are 0, that is, out of 2 × 2 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first layer The pixel h (2s, 2t) at the upper left is set to the H level only at the timing when it is supplied to the calculator 13, and is set to the L level in other cases.

  The switch 12 selects the terminal 12a or 12b when the output of the NOR gate 15 is L level or H level.

  The reading unit 11 reads data (stored data) stored at an address corresponding to a signal output from the address supply circuit 1.

  Accordingly, the upper left pixel h (2s, 2t) among the 2 × 2 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first layer is obtained. At the timing supplied to the arithmetic unit 13, the data stored in the address (s, t) of the second hierarchical memory 3 is read by the reading unit 11 and supplied to the terminal 12 a. Since the least significant bit ha0 of the address HA and the least significant bit va0 of the vertical address VA are both 0, the output of the NOR gate 15 becomes H level, and the switch 12 selects the terminal 12b.

  As a result, 0 is supplied to the calculator 13 via the switch 12.

  In the arithmetic unit 13, the 0 and the first-layer pixel h (2s, 2t) are added, and the added value (0 + h (2s, 2t)) is supplied to the writing unit 14. The writing unit 14 writes the output of the arithmetic unit 13 to the address corresponding to the signal output from the address supply circuit 1, that is, the address (s, t) of the second hierarchy memory 3.

  Next, the upper left pixel h (2s, 2t) of the 2 × 2 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first layer At the timing at which the pixel h (2s + 1, 2t) on the right side of the signal is supplied to the calculator 13, the data stored in the address (s, t) of the second hierarchical memory 3 in the reading unit 11 (here, , 0 + h (2s, 2t)) is read and supplied to the terminal 12a.

  On the other hand, in this case, since the least significant bit ha0 of the horizontal address HA is 1 and the least significant bit va0 of the vertical address VA is 0, the output of the NOR gate 15 becomes L level, and the switch 12 selects the terminal 12a. To do.

  As a result, the data (stored data) read in the reading unit 11 (here, 0 + h (2s, 2t)) is supplied to the arithmetic unit 13 via the switch 12.

  In the arithmetic unit 13, the data supplied via the switch 12 is added to the pixel h (2s + 1, 2t) in the first layer, and the added value (0 + h (2s, 2t) + h (2s + 1, 2t)) is obtained. , Supplied to the writing unit 14. The writing unit 14 writes the output of the arithmetic unit 13 to the address corresponding to the signal output from the address supply circuit 1, that is, the address (s, t) of the second hierarchy memory 3.

  Thereafter, the supply of image data on the 2t + 1 line from the top of the first layer is started, and 2 × 2 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h of the first layer are started. When the lower left pixel h (2s, 2t + 1) of (2s + 1, 2t + 1) is supplied to the calculator 13, it is also stored in the address (s, t) of the second hierarchical memory 3 in the reading unit 11. The data (here, 0 + h (2s, 2t) + h (2s + 1, 2t)) is read and supplied to the terminal 12a.

  On the other hand, in this case, since the least significant bit ha0 of the horizontal address HA is 0 and the least significant bit va0 of the vertical address VA is 1, the output of the NOR gate 15 becomes L level, and the switch 12 selects the terminal 12a. To do.

  As a result, the data (stored data) read in the reading unit 11 (here, 0 + h (2s, 2t) + h (2s + 1, 2t)) is supplied to the arithmetic unit 13 via the switch 12.

  The arithmetic unit 13 adds the data supplied via the switch 12 and the pixel h (2s, 2t + 1) in the first layer and adds the value (0 + h (2s, 2t) + h (2s + 1, 2t) + h ( 2s, 2t + 1)) is supplied to the writing unit 14. The writing unit 14 writes the output of the arithmetic unit 13 to the address corresponding to the signal output from the address supply circuit 1, that is, the address (s, t) of the second hierarchy memory 3.

  Next, the lower left pixel h (2s, 2t + 1) of 2 × 2 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first layer When the pixel h (2s + 1, 2t + 1) on the right side is supplied to the computing unit 13, the data stored in the address (s, t) of the second hierarchy memory 3 (here, 0 + h (2s, 2t) + h (2s + 1, 2t) + h (2s, 2t + 1)) is read and supplied to the terminal 12a.

  On the other hand, in this case, since the least significant bit ha0 of the horizontal address HA and the least significant bit va0 of the vertical address VA are both 1, the output of the NOR gate 15 becomes L level, and the switch 12 selects the terminal 12a. To do.

  As a result, the arithmetic unit 13 receives the data (stored data) read by the reading unit 11 via the switch 12 (here, 0 + h (2s, 2t) + h (2s + 1, 2t) + h (2s, 2t + 1)). ) Is supplied.

  The computing unit 13 adds the data supplied via the switch 12 and the pixel h (2s + 1, 2t + 1) in the first layer and adds the value (0 + h (2s, 2t) + h (2s + 1, 2t) + h ( 2s, 2t + 1) + h (2s + 1, 2t + 1)) is supplied to the writing unit 14. The writing unit 14 writes the output of the arithmetic unit 13 to the address corresponding to the signal output from the address supply circuit 1, that is, the address (s, t) of the second hierarchy memory 3.

  Therefore, the address (s, t) of the second hierarchical memory 3 is finally expressed by the equation h (2s, 2t) + h (2s + 1, 2t) + h (2s, 2t + 1) + h (2s + 1, 2t + 1). In other words, the second-layer pixel (pixel value) m (s, t) shown in the above equation (1) is stored.

  As described above, the second hierarchy memory 3 stores the second hierarchy image in which one screen is configured by 256 × 256 pixels.

  As described above, the first layer image data is written to the address (HA, VA) of the first layer memory 2 specified by the horizontal address HA and the vertical address VA, and a part of the horizontal address HA and the vertical address VA. The storage data stored in the second hierarchical memory address designated by ha1 to ha8 and va1 to va8 is read out, and the storage data and the first hierarchical image data are added, and the addition is performed. Since the value (first processing data) is written to the address of the second hierarchy memory where the stored data was stored, the image data of the second hierarchy is generated simultaneously with the storage of the image data of the first hierarchy And memorize it. That is, the image data of the second hierarchy can be obtained in real time.

  Further, in this case, the second layer memory 3 for storing the second layer image also serves as a circuit for performing a conventional line delay. Therefore, it is not necessary to provide such a circuit, so that the size of the apparatus can be reduced. Can be achieved.

  Next, reading of the second layer image from the second layer memory 3 will be described.

  At the time of reading, when the hierarchy flag indicates the second hierarchy, the address supply circuit 1 again uses the upper 8 bits ha1 to ha8 or va1 to va8 of the horizontal address HA or the vertical address VA supplied thereto, respectively. Are supplied to the address terminals of the second hierarchical memory 2, and the least significant bits ha0 or va0 are output to the RMW circuit 5 as control signals.

  On the other hand, in the RMW circuit 5, the hierarchy flag, the R / W signal, and the output of the NOR gate 15 are supplied to the reading unit 11, and the reading unit 11 reads the R / W signal. When the level flag indicates the second level, for example, only when the output of the NOR gate 15 is at the H level, it is stored in the address corresponding to the signal output from the address supply circuit 1. Read and output the second layer image data.

  That is, from the above, when the set of the horizontal address HA and the vertical address VA is (2s, 2t), (2s + 1, 2t), (2s, 2t + 1), (2s + 1, 2t + 1), the address supply circuit 1 , The same address (s, t) is output to the second hierarchical memory 3. Therefore, when data is simply read from the address of the second hierarchical memory 3 corresponding to the signal output from the address supply circuit 1, the same data is read four times.

  Therefore, in the reading unit 11, a set of the horizontal address HA and the vertical address VA is (2s, 2t), (2s + 1, 2t), (2s, 2t + 1), (2s + 1, 2t + 1), for example, (2s, 2t), that is, only when the output of the NOR gate 15 is at the H level, from the address (s, t) of the second hierarchy memory 3, the pixel (pixel value) m (s, t) of the second hierarchy Is read out.

  The second layer image data read by the reading unit 11 is supplied to the switch 16. The switch 16 is turned on only when the R / W signal indicates reading, and is turned off in other cases. Therefore, in this case, the switch 16 is turned on. The read second layer image data is output via the switch 16.

  As described above, the second hierarchy image stored in the second hierarchy memory 3 is read out from the second hierarchy image for one screen composed of 256 × 256 pixels. That is, the second-level image scanned sequentially is output.

  Next, access to the third hierarchy memory 4 will be described.

  First, at the time of writing, as shown in FIG. 5, for example, the address supply circuit 1 uses the upper 7 bits ha2 to ha2 and excluding the lower 2 bits ha0 and ha1 as part of the horizontal address HA supplied thereto. ha8 and the upper 7 bits va2 to va8 excluding the lower 2 bits va0 and va1 as a part of the vertical address VA are supplied to the address terminals of the third hierarchy memory 4. Furthermore, the address supply circuit 1 outputs the lower 2 bits ha0 and ha1 of the horizontal address HA and the lower 2 bits va0 and va1 of the vertical address VA to the RMW circuit 5 as control signals.

  Therefore, for example, as shown by D2 in FIG. 2, 4 × 4 16 pixels h (4m, 4n), h (4m + 1, 4n), h (4m + 2, 4n), h (4m + 3, 4n), h (4m, 4n + 1), h (4m + 1, 4n + 1), h (4m + 2, 4n + 1), h (4m + 3, 4n + 1), h (4m, 4n + 2), h (4m + 1, 4n + 2), h (4m + 2, 4n + 2), h (4m + 3, 4n + 2), h (4m, 4n + 3), h (4m + 1, 4n + 3), h (4m + 2, 4n + 3), h (4m + 3, 4n + 3) are supplied to the RMW circuit 5 at any timing. The address supply circuit 1 outputs a signal designating the same address (m, n) of the third hierarchy memory 4.

  On the other hand, in the RMW circuit 5, the first layer image data supplied thereto is input to the computing unit 23. The computing unit 23 is supplied with the output of the switch 22 in addition to the image data of the first layer, and the computing unit 23 adds them and supplies them to the writing unit 24. Yes.

  The switch 22 selects one of the terminals 22a and 22b corresponding to the output of the NOR gate 25. The terminal 22a or 22b receives the output of the reading unit 21 or 0. Each is supplied. The NOR gate 25 is supplied with the lower 2 bits ha0 and ha1 of the horizontal address HA from the address supply circuit 1 and the lower 2 bits va0 and va1 of the vertical address VA. When the lower 2 bits ha0 and ha1 and va0 and va1 are both 0, that is, 4 × 4 pixels h (4m, 4n), h (4m + 1, 4n), h (4m + 2, 4n), h in the first layer (4m + 3, 4n), h (4m, 4n + 1), h (4m + 1, 4n + 1), h (4m + 2, 4n + 1), h (4m + 3, 4n + 1), h (4m, 4n + 2), h (4m + 1, 4n + 2), h ( 4m + 2, 4n + 2), h (4m + 3, 4n + 2), h (4m, 4n + 3), h (4m + 1, 4n + 3), h (4m + 2, 4n + 3), h (4m 3, 4n + 3) top left pixel h (4m of, 4n) is the case of the timing to be supplied to the arithmetic unit 23 only, the H level, in other cases have been made so as to be L level.

  The switch 22 selects the terminal 22a or 22b when the output of the NOR gate 25 is L level or H level.

  The reading unit 21 reads data (stored data) stored at an address corresponding to a signal output from the address supply circuit 1.

  Therefore, at the timing when the pixel h (4m, 4n) in the first hierarchy is supplied to the computing unit 23, the data stored at the address (m, n) in the third hierarchy memory 4 is read out by the readout unit 21. In this case, since the lower 2 bits ha0 and ha1 of the horizontal address HA and the lower 2 bits va0 and va1 of the vertical address VA are both 0, the output of the NOR gate 25 is H The switch 22 selects the terminal 22b.

  As a result, 0 is supplied to the computing unit 23 via the switch 22.

  In the computing unit 23, 0 and the pixel h (4m, 4n) of the first layer are added, and the added value (0 + h (4m, 4n)) is supplied to the writing unit 24. The writing unit 24 writes the output of the arithmetic unit 23 to the address corresponding to the signal output from the address supply circuit 1, that is, the address (m, n) of the third hierarchy memory 4.

  Next, at the timing when the pixel h (4m + 1, 4n) on the right side of the pixel h (4m, 4n) in the first hierarchy is supplied to the computing unit 23, the readout unit 21 again stores the third hierarchy memory 4 in the third hierarchy memory 4. Data stored in the address (m, n) (here, 0 + h (4m, 4n)) is read and supplied to the terminal 22a.

  On the other hand, in this case, the lower 2 bits ha0 or ha1 of the horizontal address HA are 1 or 0, respectively, and the lower 2 bits va0 and va1 of the vertical address VA are both 0. Therefore, the output of the NOR gate 25 is L level. Thus, the switch 22 selects the terminal 22a.

  As a result, the data (stored data) read in the reading unit 21 (here, 0 + h (4m, 4n)) is supplied to the computing unit 23 via the switch 22.

  In the computing unit 23, the data supplied via the switch 22 and the pixel h (4m + 1, 4n) of the first layer are added, and the added value (0 + h (4m, 4n) + h (4m + 1, 4n)) is obtained. , Supplied to the writing unit 24. The writing unit 24 writes the output of the arithmetic unit 23 to the address corresponding to the signal output from the address supply circuit 1, that is, the address (m, n) of the third hierarchy memory 4.

  Next, at the timing when the pixel h (4m + 2, 4n) on the right side of the pixel h (4m + 1, 4n) in the first hierarchy is supplied to the computing unit 23, the readout unit 21 again stores the third hierarchy memory 4 in the third hierarchy memory 4. Data stored in the address (m, n) (here, 0 + h (4m, 4n) + h (4m + 1, 4n)) is read and supplied to the terminal 22a.

  On the other hand, in this case, since the lower 2 bits ha0 or ha1 of the horizontal address HA are 0 or 1, respectively, and the lower 2 bits va0 and va1 of the vertical address VA are both 0, the output of the NOR gate 25 is L level. Thus, the switch 22 selects the terminal 22a.

  As a result, the data (stored data) read in the reading unit 21 (here, 0 + h (4m, 4n) + h (4m + 1, 4n)) is supplied to the computing unit 23 via the switch 22.

  In the arithmetic unit 23, the data supplied via the switch 22 and the pixel h (4m + 2, 4n) of the first layer are added, and the added value (0 + h (4m, 4n) + h (4m + 1, 4n) + h ( 4m + 2, 4n)) is supplied to the writing unit 24. The writing unit 24 writes the output of the arithmetic unit 23 to the address corresponding to the signal output from the address supply circuit 1, that is, the address (m, n) of the third hierarchy memory 4.

  Hereinafter, pixels h (4m + 3, 4n), h (4m, 4n + 1), h (4m + 1, 4n + 1), h (4m + 2, 4n + 1), h (4m + 3, 4n + 1), h (4m, 4n + 2), h in the first layer (4m + 1, 4n + 2), h (4m + 2, 4n + 2), h (4m + 3, 4n + 2), h (4m, 4n + 3), h (4m + 1, 4n + 3), h (4m + 2, 4n + 3), h (4m + 3, 4n + 3) In any case, the same processing as described above is performed at the timing supplied to the device 23, and as a result, the address (m, n) of the third hierarchical memory 4 is finally set to the above-described case. The pixel (pixel value) q (m, n) in the third hierarchy shown in Expression (2) is stored.

  As described above, the third hierarchy memory 4 stores the third hierarchy image in which one screen is composed of 128 × 128 pixels.

  Accordingly, at the same time as storing the image data of the first layer, the image data of the second layer, and further, the image data of the third layer can be generated and stored. That is, the second and third layer image data can be obtained in real time.

  In this case as well, the third layer memory 4 for storing the third layer image also serves as a circuit for performing a conventional line delay, and therefore it is not necessary to provide such a circuit. Can be miniaturized.

  Next, reading of the third layer image from the third layer memory 4 will be described.

  At the time of reading, when the hierarchy flag indicates the third hierarchy, the address supply circuit 1 again uses the upper 7 bits ha2 to ha8 or va2 to va8 of the horizontal address HA or the vertical address VA supplied thereto, respectively. The lower two bits ha0 and ha1 or va0 and va1 are output to the RMW circuit 5 as control signals.

  On the other hand, in the RMW circuit 5, the hierarchy flag, the R / W signal, and the output of the NOR gate 25 are supplied to the reading unit 21, and the reading unit 21 reads the R / W signal. In the case where the level flag indicates the third level, for example, only when the output of the NOR gate 25 is at the H level, it is stored in the address corresponding to the signal output from the address supply circuit 1. Read and output the third layer image data.

  That is, from the above, the set of the horizontal address HA and the vertical address VA is (4m, 4n), (4m + 1, 4n), (4m + 2, 4n), (4m + 3, 4n), (4m, 4n + 1), ( 4m + 1, 4n + 1), (4m + 2, 4n + 1), (4m + 3, 4n + 1), (4m, 4n + 2), (4m + 1, 4n + 2), (4m + 2, 4n + 2), (4m + 3, 4n + 2), (4m, 4n + 3), (4m + 1, In the case of (4n + 3), (4m + 2, 4n + 3), (4m + 3, 4n + 3), the address supply circuit 1 outputs the same address (m, n). Therefore, simply reading out data from the address of the third hierarchical memory 4 corresponding to the signal output from the address supply circuit 1, the same data is read out 16 times.

  Therefore, in the reading unit 21, only when the set of the horizontal address HA and the vertical address VA is, for example, (4m, 4n), that is, only when the output of the NOR gate 25 is at the H level. The third layer pixel (pixel value) m (m, n) is read from the address (m, n) of the third layer memory 4.

  The third layer image data read by the reading unit 21 is supplied to the switch 26. The switch 26 is turned on only when the R / W signal indicates reading, and is turned off in other cases. Therefore, in this case, the switch 26 is turned on. The read third layer image data is output via the switch 26.

  As described above, from the third hierarchy memory 4, the image of the third hierarchy for one screen composed of 128 × 128 pixels stored therein is read out. That is, the third-layer image scanned sequentially is output.

  The reading of the image data of the second hierarchy from the second hierarchy memory 3 is performed as described above. For example, the lower 8 bits ha0 to ha7 of the horizontal address HA and the vertical address VA are supplied from the address supply circuit 1. The lower 8 bits va0 to va7 can be given as addresses of the second hierarchical memory 3. Similarly, the reading of the third layer image data from the third layer memory 4 is also performed by reading from the address supply circuit 1 the lower 7 bits ha0 to ha6 of the horizontal address HA and the lower 7 bits va0 to va6 of the vertical address VA. This can be done by giving it as the address of the third hierarchy memory 4.

  Next, from what has been described with reference to FIG. 9, among the adjacent 2 × 2 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), and h (2s + 1, 2t + 1) in the first layer For example, the lower right pixel h (2s + 1, 2t + 1) is the remaining first layer pixel h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), and Can be obtained from the pixel m (s, t) in the second layer, which is the added value of.

That is, the pixel h (2s + 1, 2t + 1) in the first layer
h (2s + 1,2t + 1) = m (s, t)-(h (2s, 2t) + h (2s + 1,2t) + h (2s, 2t + 1))
Can be obtained.

  Therefore, the pixel h (2s + 1, 2t + 1) in the first layer can be obtained from the above equation without being stored.

  Therefore, the first hierarchy memory 2 is one of 2 × 2 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) of the first hierarchy. It is possible to configure without providing a memory cell for storing h (2s + 1, 2t + 1).

  That is, in the above case, the first layer memory 2 has at least memory cells capable of storing image data of 512 × 512 pixels, but the first layer pixels h (2s + 1, 2t + 1). In the case where is not stored, at least 512 × 512 × 3/4 pixel image data can be stored in the memory cell. In this case, the first hierarchy memory 2 calculates the number of addresses of the second hierarchy memory 3 (the number of pixels constituting one screen of the second hierarchy (256 × 256)) from the number of pixels constituting one screen of the first hierarchy image. ) Is subtracted from the number of memory cells (storage capacity).

  Further, it is one of adjacent 2 × 2 pixels m (2m, 2n), m (2m + 1, 2n), m (2m, 2n + 1), m (2m + 1, 2n + 1) in the second layer, for example, right The lower pixel m (2m + 1, 2n + 1) is also the remaining second-layer pixel m (2m, 2n), m (2m + 1, 2n), m (2m, 2n + 1), and the third added value thereof. It can be obtained from the pixel q (m, n) of the hierarchy.

That is, the pixel m (2m + 1, 2n + 1) in the second hierarchy is expressed by the equation
m (2m + 1,2n + 1) = q (m, n)-(m (2m, 2n) + m (2m + 1,2n) + m (2m, 2n + 1))
Can be obtained.

  Accordingly, the pixel m (2m + 1, 2n + 1) in the second layer can be obtained without being stored.

  Therefore, the second layer memory 3 is also one of 2 × 2 4 pixels m (2m, 2n), m (2m + 1, 2n), m (2m, 2n + 1), m (2m + 1, 2n + 1) in the second layer. It is possible to configure without providing memory cells for storing m (2m + 1, 2n + 1).

  That is, in the above-described case, the second hierarchical memory 3 has at least memory cells capable of storing image data of 256 × 256 pixels. However, the second hierarchical pixel m (2m + 1, 2n + 1). In the case where is not stored, the memory cell can be configured to store at least image data of 256 × 256 × 3/4 pixels. In this case, the second hierarchy memory 3 calculates the number of addresses of the third hierarchy memory 4 (the number of pixels constituting one screen of the third hierarchy (128 × 128)) from the number of pixels constituting one screen of the second hierarchy image. ) Is subtracted from the number of memory cells (storage capacity).

  Even when the first hierarchy memory 2 and the second hierarchy memory 3 have a small storage capacity as described above, the images to the first hierarchy memory 2, the second hierarchy memory 3, and the third hierarchy memory 4 are displayed. Data writing can be performed as described with reference to FIGS. However, the first layer memory 2 does not have a memory cell that stores the pixel h (2s + 1, 2t + 1) in the first layer, that is, a memory cell corresponding to the address (2s + 1, 2t + 1). The address (2s + 1, 2t + 1) is supplied to the first layer memory 2, and even if the first layer pixel h (2s + 1, 2t + 1) is supplied from the RMW circuit 5, the pixel h (2s + 1, 2t + 1) Are not stored in the first hierarchy memory 2.

  Similarly, the second hierarchy memory 3 has no memory cell for storing the pixel m (2m + 1, 2n + 1) in the second hierarchy, that is, the memory cell corresponding to the address (2m + 1, 2n + 1). Therefore, the address supply circuit 1 Address (2m + 1, 2n + 1) is supplied to the second hierarchy memory 3 from the RMW circuit 5 (writing unit 14 (FIG. 4)) and the pixel m (2m + 1, 2n + 1) of the second hierarchy is supplied. However, the pixel m (2m + 1, 2n + 1) is not stored in the second hierarchical memory 3.

  Further, the third layer image stored in the storage device can be read in the same manner as in FIG. 5 described above. However, the first or second layer image can be read as follows. Is called.

  That is, FIG. 6 shows a configuration example of the storage device of FIG. 1 when reading the image of the first hierarchy when the storage capacity of the first hierarchy memory 2 is small.

  In this case, the address supply circuit 1 includes a delay circuit 31 and selection circuits 32 to 34. The delay circuit 31 receives the horizontal address HA and the vertical address VA. For example, the upper 7 bits va2 to va8 of the vertical address VA are latched corresponding to the change of the lower third bit va2. Output.

That is, the delay circuit 31 detects when the lower third bit va2 of the vertical address VA changes from 0 to 1 and when it changes from 1 to 0, and the upper 7 bits of the vertical address VA immediately before the change. va2 to va8 are latched and output together with the remaining vertical and horizontal addresses. Therefore, the horizontal address HA and the vertical address VA output from the delay circuit 31 are obtained by delaying the horizontal address HA and the vertical address VA supplied to the address supply circuit 1 by 4 (= 2 ^3-1 ) lines. The delay circuit 31 only needs to latch the upper 7 bits va2 to va8 of the vertical address VA immediately before the change when the lower third bit va2 of the vertical address VA changes, so that the conventional image is line-delayed. Therefore, it does not become a large-sized one like a delay circuit. That is, the delay circuit 31 can be configured by, for example, seven flip-flops that latch the upper 7 bits va2 to va8 of the vertical address VA, and thus can be configured in a small size.

  Here, the horizontal address HA or vertical address VA four lines before generated by the delay circuit 31 will be referred to as a delayed horizontal address HA or a delayed vertical address (predetermined address signal), respectively.

  The delayed horizontal address HA and the delayed vertical address VA are supplied to the selection circuit 32. Of the delayed horizontal address HA and the delayed vertical address VA, the upper 8 bits ha1 to ha8 excluding the least significant bit ha0 of the delayed horizontal address HA and the upper 8 bits va1 to va0 except for the least significant bit va0 of the delayed vertical address VA. va8 is supplied to the selection circuit 33. Further, of the delayed horizontal address HA and the delayed vertical address VA, the higher 7 bits ha2 to ha8 excluding the lower 2 bits ha0 and ha1 of the delayed horizontal address HA and the upper 2 bits excluding the lower 2 bits va0 and va1 of the delayed vertical address VA. The 7 bits va2 to va8 are supplied to the selection circuit 34.

  In addition to the delayed horizontal address HA and the delayed vertical address VA, the selection circuit 32 is supplied with the horizontal address HA and the vertical address VA supplied to the address supply circuit 1 as they are, and the lower third bit of the vertical address VA. va2 is supplied as a control signal. In the selection circuit 32, in response to the control signal va2, one of the delayed horizontal address HA and the delayed vertical address VA, the horizontal address HA and the vertical address VA is an A bank address, and the other is a B bank address. These are selected and supplied to the A bank address terminal and the B bank address terminal of the first hierarchical memory 2 respectively.

  That is, for example, when the selection circuit 32 selects the delayed horizontal address HA and the delayed vertical address VA as the A bank address and the horizontal address HA and the vertical address VA as the B bank address, the control signal va2 changes. Then, the delayed horizontal address HA and delayed vertical address VA are selected as B bank addresses, and the horizontal address HA and vertical address VA are selected as A bank addresses, respectively. Further, after that, when the control signal va2 changes again, the selection circuit 32 again selects the delayed horizontal address HA and the delayed vertical address VA as the A bank address and the horizontal address HA and the vertical address VA as the B bank address, respectively. Therefore, in the selection circuit 32, every time the control signal va2 changes, the delayed horizontal address HA and the delayed vertical address VA are alternately selected as the A bank address or the B bank address, and the horizontal address HA and the vertical address VA are changed. , B bank address or A bank address are alternately selected.

  The selection circuit 33 includes the upper 8 bits ha1 to ha8 of the delayed horizontal address HA and the upper 8 bits va1 to va8 of the delayed vertical address VA, as well as the upper 8 bits ha1 to ha8 of the horizontal address HA supplied to the address supply circuit 1. The upper 8 bits va1 to va8 of the vertical address VA are supplied, and the lower third bit va2 of the vertical address VA is supplied as a control signal. In the selection circuit 33, as in the selection circuit 32, each time the control signal va2 changes, the upper 8 bits ha1 to ha8 of the delayed horizontal address HA and the upper 8 bits va1 to va8 of the delayed vertical address VA are changed. Are alternately selected as the A bank address or the B bank address, and the upper 8 bits ha1 to ha8 of the horizontal address HA and the upper 8 bits va1 to va8 of the vertical address VA are alternately selected as the B bank address or the A bank address. It is made to be done.

  What is selected as the A bank address or the B bank address in the selection circuit 33 is supplied to the A bank address terminal or the B bank address terminal of the second hierarchical memory 3, respectively.

  The selection circuit 34 includes the upper 7 bits ha2 to ha8 of the delayed horizontal address HA and the upper 7 bits va2 to va8 of the delayed vertical address VA, as well as the upper 7 bits ha2 to ha8 of the horizontal address HA supplied to the address supply circuit 1. The upper 7 bits va2 to va8 of the vertical address VA are supplied, and the lower third bit va2 of the vertical address VA is supplied as a control signal. In the selection circuit 34, as in the selection circuit 32, each time the control signal va2 changes, the upper 7 bits ha2 to ha8 of the delayed horizontal address HA and the upper 7 bits va2 to va8 of the delayed vertical address VA are changed. Are alternately selected as the A bank address or the B bank address, and the upper 7 bits ha2 to ha8 of the horizontal address HA and the upper 7 bits va2 to va8 of the vertical address VA are alternately selected as the B bank address or the A bank address. It is made to be done.

  What is selected as the A bank address or the B bank address in the selection circuit 34 is supplied to the A bank address terminal or the B bank address terminal of the third layer memory 4, respectively.

  In the embodiment of FIG. 6 (the same applies to FIG. 8 described later), the address space of the first hierarchical memory 2 is divided into two banks (blocks) of A bank and B bank. That is, in FIG. 2, for example, the storage area of the first hierarchical memory 2 for storing pixels of the 8α to 8α + 3 lines stores the A bank and the pixels of the 8α + 4 to 8α + 7 lines. The storage areas of the first hierarchical memory 2 for this purpose are designated as B banks (where α = 0, 1, 2,..., 63).

  An address terminal (A bank address terminal) for accessing the A bank and an address terminal (B bank address terminal) for accessing the B bank so that both the A bank and the B bank can be accessed simultaneously. These two address terminals are provided. Furthermore, two data terminals, that is, an A bank data terminal and a B bank data terminal, are provided as input / output terminals for reading / writing data from / to the A bank and B bank.

  Therefore, in the first hierarchical memory 2, data (A bank data) is read from and written to the address (A bank address) input to the A bank address terminal via the A bank data terminal, and the B bank address is read. Data (B bank data) can be read from and written to the address (B bank address) input to the terminal via the B bank data terminal.

  In this embodiment, the delayed horizontal address HA and the delayed vertical address VA are obtained by delaying the horizontal address HA and the vertical address VA by 4 lines (4 lines of the first stage image). Therefore, in the selection circuit 32, for example, when the horizontal address HA and the vertical address VA are selected as the A bank address and the delayed horizontal address HA and the delayed vertical address VA are selected as the B bank address, respectively, Are accessed to the memory cells in the A bank corresponding to the horizontal address HA and the vertical address VA. At this time, the delayed horizontal address HA and the delayed vertical address accessed at the same time by the time corresponding to the four lines at the same time. A memory cell in B bank corresponding to VA is also accessed.

  That is, for example, as shown in FIG. 7, if the first-tier memory 2 is divided into a storage area as A bank and a storage area as B bank, a memory cell with A bank is accessed. At the same time, the memory cell in the B bank corresponding to the memory cell is also accessed. In the present embodiment, the corresponding memory cells in the A bank and B bank that are accessed simultaneously are separated by an amount corresponding to four lines. Here, the memory cells in the A bank and the B bank that are simultaneously accessed in this way are separated by an amount corresponding to four lines. In this embodiment, one pixel in the third hierarchy, which is the highest hierarchy, is separated. However, since 4 × 4 pixels in the first layer are generated as a unit, it is preferable that the bank be at least such a unit. Therefore, here, every four lines are alternately divided into A bank and B bank. However, for example, it is also possible to divide into four columns, and the number of banks is the same as that of A bank and B bank. It is not limited to two. Furthermore, it is also possible to open banks in both the horizontal and vertical directions, that is, in a so-called lattice pattern.

  Returning to FIG. 6, in the second hierarchy memory 3, as in the first hierarchy memory 2, the address space is divided into two banks, A bank and B bank. However, in the present embodiment, the number of horizontal or vertical pixels constituting the second layer image is ½ of the first layer image. Therefore, in the second layer memory 3, the second layer image The storage area of the second hierarchy memory 3 for storing the pixels of the 4α line and the 4α + 1 line is the A bank, and the storage area of the second hierarchy memory 3 for storing the pixels of the 4α + 2 line and the 4α + 3 line B bank, respectively.

  In the third hierarchy memory 4, as in the first hierarchy memory 2, the address space is divided into two banks, A bank and B bank. However, in the present embodiment, since the number of horizontal or vertical pixels constituting the third layer image is 1/4 of the first layer image, the third layer memory 4 has the third layer image. The storage area of the third hierarchy memory 4 for storing pixels of the second α line is designated as A bank, and the storage area of the third hierarchy memory 4 for storing pixels of the second α + 1 line is designated as B bank. .

  Both the A bank data terminal and the B bank data terminal from which data (A bank data or B bank data) read from the A bank or B bank of the first hierarchy memory 2 is output are connected to the selection circuit 41. ing. The selection circuit 41 is supplied with the lower third bit va2 of the vertical address VA from the address supply circuit 1 as a control signal. In the selection circuit 41, the selection circuit 41 corresponds to the control signal va2. One of the A bank data terminal and the B bank data terminal is connected to the reading unit 44, and the other is connected to the reading unit 45.

  That is, at a certain point in time, for example, when the A bank data terminal or the B bank data terminal is connected to the reading unit 44 or 45, the selection circuit 41 changes the A bank data terminal or The B bank data terminal is connected to the reading unit 45 or 44, respectively. Further, after that, when the control signal va2 changes again, the selection circuit 41 reconnects the A bank data terminal or the B bank data terminal to the reading unit 44 or 45, respectively. Therefore, according to the selection circuit 41, every time the control signal va2 changes, the A bank data terminal is alternately connected to the reading unit 44 or 45, and the B bank data terminal is alternately connected to the reading unit 45 or 44. Is done.

  The data to be written to the A bank of the second hierarchical memory 3 is supplied, the A bank data terminal to which the data read from the A bank is output, and the data to be written to the B bank are supplied, and B The B bank data terminals to which data read from the bank is output are all connected to the selection circuit 42. The selection circuit 42 is also supplied with the lower third bit va2 of the vertical address VA from the address supply circuit 1 as a control signal. The selection circuit 42 corresponds to the control signal va2, One of the A bank data terminal and the B bank data terminal is connected to the writing unit 46 and the reading unit 47, and the other is connected to the writing unit 48 and the reading unit 49.

  That is, the selection circuit 42 is controlled at a certain point in time when, for example, the A bank data terminal is connected to the writing unit 46 and the reading unit 47 and the B bank data terminal is connected to the writing unit 48 and the reading unit 49. When the signal va2 changes, the A bank data terminal is connected to the writing unit 48 and the reading unit 49, and the B bank terminal is connected to the writing unit 46 and the reading unit 47. Further, after that, when the control signal va2 changes again, the selection circuit 42 reconnects the A bank data terminal to the writing unit 46 and the reading unit 47 and reconnects the B bank data terminal to the writing unit 48 and the reading unit 49. To do. Therefore, according to the selection circuit 42, every time the control signal va2 changes, the A bank data terminal is alternately connected to the writing unit 46 and the reading unit 47, or the writing unit 48 and the reading unit 49, and the B bank Data terminals are alternately connected to the writing unit 48 and the reading unit 49 or between the writing unit 46 and the reading unit 47.

  The data to be written to the A bank of the third hierarchy memory 4 is supplied, the A bank data terminal to which the data read from the A bank is output, and the data to be written to the B bank are supplied, and B The B bank data terminals to which data read from the bank are output are all connected to the selection circuit 43. Further, the lower third bit va2 of the vertical address VA is supplied from the address supply circuit 1 to the selection circuit 43 as a control signal. In the selection circuit 43, as in the selection circuit 42, each time the control signal va <b> 2 changes, the A bank data terminal alternates between the writing unit 50 and the reading unit 51 or between the writing unit 52 and the reading unit 53. And the B bank data terminal is alternately connected to the writing unit 52 and the reading unit 53 or between the writing unit 50 and the reading unit 51.

  The reading unit 44 or 45 reads data from the first hierarchy memory 2 via the selection circuit 41. The data read by the reading unit 44 is supplied to the computing unit 54 and the selection circuit 58 and is also supplied to the computing unit 56 via the switch 61. The data read by the reading unit 45 is supplied to the calculators 55 and 57. The writing unit 46 writes the output of the computing unit 54 into the second hierarchy memory 3 via the selection circuit 42. The reading unit 47 reads data from the second hierarchical memory 3 via the selection circuit 42 and supplies the data to the arithmetic unit 54 and the selection circuit 58. The writing unit 48 writes the output of the computing unit 55 into the second hierarchy memory 3 via the selection circuit 42. The reading unit 49 reads data from the second hierarchy memory 3 via the selection circuit 42 and supplies the data to the arithmetic unit 55 and the switch 62. The writing unit 50 writes the output of the computing unit 56 into the third hierarchy memory 4 via the selection circuit 43. The reading unit 51 reads data from the third hierarchy memory 4 via the selection circuit 43 and supplies the data to the arithmetic unit 56 and the selection circuit 58. The writing unit 52 writes the output of the computing unit 57 into the third hierarchy memory 4 via the selection circuit 43. The reading unit 53 reads data from the third hierarchy memory 4 via the selection circuit 43 and supplies the data to the calculator 57.

  The computing unit 54 subtracts the output of the reading unit 44 from the output of the reading unit 47 and supplies the subtraction result to the writing unit 46. The computing unit 55 adds the outputs of the reading units 45 and 49 and supplies the addition result to the writing unit 48. The computing unit 56 subtracts the signal supplied via the switch 61 from the output of the reading unit 51 and supplies it to the writing unit 50. The computing unit 57 adds the outputs of the reading units 45 and 53 and supplies the addition result to the writing unit 52. In addition, when the switch 62 is in the ON state, and the output of the reading unit 49 is supplied to the calculator 57, the output is also added.

  The selection circuit 58 selects and outputs one of the outputs of the reading units 44, 47, or 51 corresponding to the outputs of the AND gates 59 and 60. The AND gate 59 is supplied from the address supply circuit 1 with the least significant bit ha0 of the horizontal address HA and the least significant bit va0 of the vertical address VA as control signals. A logical product is calculated and supplied to the selection circuit 58. The AND gate 60 is supplied with the lower second bit ha1 of the horizontal address HA and the lower second bit va1 of the vertical address VA from the address supply circuit 1 as control signals. The logical product is calculated and supplied to the selection circuit 58.

  The switch 61 selects one of the terminals 61a and 61b corresponding to the output of the AND gate 59. Note that the output of the reading unit 44 or 47 is supplied to the terminal 61a or 61b, respectively. The switch 62 is turned on / off in response to the output of the NOR gate 63, and supplies the output of the reading unit 49 to the computing unit 57. As with the AND gate 59, the least significant bits ha0 and va0 are supplied to the NOR gate 63, and on / off of the switch 62 is controlled by the output.

  Here, the above selection circuits 41 to 43, reading units 44 and 45, writing unit 46, reading unit 47, writing unit 48, reading unit 49, writing unit 50, reading unit 51, writing unit 52, reading unit 53, calculation The RMW circuit 5 is composed of the devices 54 to 57, the selection circuit 58, the AND gates 59 and 60, the switches 61 and 62, and the NOR gate 63.

  In FIG. 6 (the same applies to FIG. 8 described later), the clock, the R / W signal, and the hierarchy flag are not shown.

  Next, the operation will be described.

  Now, in the selection circuit 32, for example, the horizontal address HA and the vertical address VA supplied to the address supply circuit 1 are selected as the A bank address, and the delayed horizontal address HA and the delayed vertical address VA are selected as the B bank address, respectively. And

  In this case, in the selection circuits 33 and 34, the A bank address and the B bank address are selected in the same manner. That is, in the selection circuit 33, the upper 8 bits ha1 to ha8 of the horizontal address HA and the upper 8 bits va1 to va8 of the vertical address VA are used as the A bank address as the upper 8 bits ha1 to ha8 of the delayed horizontal address HA and the delayed vertical address. The upper 8 bits va1 to va8 of VA are selected as B bank addresses, respectively. In the selection circuit 34, the upper 7 bits ha2 to ha8 of the horizontal address HA and the upper 7 bits va2 to va8 of the vertical address VA are used as the A bank address as the upper 7 bits ha2 to ha8 of the delayed horizontal address HA and the delayed vertical address. The upper 7 bits va2 to va8 of VA are selected as B bank addresses, respectively.

  The A bank address and the B bank address selected by the selection circuits 32 to 34 are supplied to the A bank address terminal and the B bank address terminal of the first hierarchy memory 2, the second hierarchy memory 3, or the third hierarchy memory 4, respectively. The

  Further, in this case, in the selection circuit 41, the A bank data terminal of the first hierarchical memory 2 is connected to the reading unit 44 and the B bank data terminal is connected to the reading unit 45. In the selection circuit 42, the A bank data terminal of the second hierarchical memory 3 is connected to the writing unit 46 and the reading unit 47, and the B bank data terminal is connected to the writing unit 48 and the reading unit 49. . Further, in the selection circuit 43, the A bank data terminal of the third hierarchy memory 4 is connected to the writing unit 50 and the reading unit 51, and the B bank data terminal is connected to the writing unit 52 and the reading unit 53. .

  The reading unit 44 reads the first layer pixel (pixel value) stored in the A bank address output from the selection circuit 32 from the first layer memory 2 via the selection circuit 41, and selects the computing unit 54. This is supplied to the circuit 58 and the terminal 61 a of the switch 61.

  When the output of the AND gate 59 is not 1 (when it is 0), the selection circuit 58 selects and outputs the output of the reading unit 44 as a pixel in the first hierarchy. That is, when the output of the AND gate 59 is not 1, it is when at least one of ha0 or va0 is 0, and 2 × 2 4 pixels h in the first hierarchy as indicated by D1 in FIG. Among the (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1), the pixel h (2s, 2t) excluding the lower right pixel h (2s + 1, 2t + 1), This is the timing at which one of h (2s + 1, 2t) and h (2s, 2t + 1) is read. Since h (2s, 2t), h (2s + 1, 2t), and h (2s, 2t + 1) are all stored in the first hierarchy memory 2, the values read from the first hierarchy memory 2 are As it is, it is selected by the selection circuit 58 and outputted.

  On the other hand, the readout unit 47 reads out the pixel (pixel value) in the second hierarchy stored in the A bank address output from the selection circuit 33 from the second hierarchy memory 3 via the selection circuit 42, and the arithmetic unit 54. , To the selection circuit 58 and the terminal 61b of the switch 61.

  Here, at the timing when access is made to 2 × 2 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first hierarchy, In the case where access is made to the A bank addresses (2s, 2t), (2s + 1, 2t), (2s, 2t + 1), (2s + 1, 2t + 1) of the first hierarchy memory 2, either of the above cases is explained. Also, the A bank address (s, t) of the second hierarchy memory 3 is accessed.

  Therefore, when the reading unit 44 reads the pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1) of the first layer from the first layer memory 2 and supplies them to the computing unit 54, In the reading unit 47, data is read from the A bank address (s, t) of the second hierarchy memory 3 and supplied to the computing unit 54.

  In the computing unit 54, the output of the reading unit 44 is subtracted from the output of the reading unit 47 and supplied to the writing unit 46. The writing unit 46 writes the output of the computing unit 54 to the A bank address (s, t) of the second hierarchical memory 3 via the selection circuit 42.

  Therefore, at first, the A bank address (s, t) of the second hierarchy memory 3 is set to 2 × 2 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, t) of the first hierarchy. 2t + 1), h (2s + 1, 2t + 1), which is the added value of the second layer pixel m (s, t), is stored, but the reading unit 44 reads the first layer pixel h (2s, 2t). At the same time, the readout unit 47 reads out the data (here, m (s, t)) stored in the A bank address (s, t) of the second hierarchical memory 3, so that the computing unit 54 A subtraction value (m (s, t) −h (2s, 2t)) is obtained and written to the A bank address (s, t) of the second hierarchy memory 3 by the writing unit 46.

  Further, the readout unit 44 reads out the pixel h (2s + 1, 2t) in the first hierarchy, and the readout unit 47 stores data (here, the A bank address (s, t) in the second hierarchy memory 3). , M (s, t) −h (2s, 2t)), the subtracted value (m (s, t) −h (2s, 2t) −h (2s + 1, 2t)) is obtained in the computing unit 54. ) Is obtained, and is written into the A bank address (s, t) of the second hierarchical memory 3 by the writing unit 46.

  Thereafter, the reading unit 44 reads the pixel h (2s, 2t + 1) in the first layer, and the reading unit 47 stores data (here, the A bank address (s, t) of the second layer memory 3). , M (s, t) −h (2s, 2t) −h (2s + 1, 2t)), the subtraction value (m (s, t) −h (2s, 2t)) is obtained in the computing unit 54. −h (2s + 1, 2t) −h (2s, 2t + 1)) is obtained and written to the A bank address (s, t) of the second hierarchical memory 3 by the writing unit 46. That is, the A bank address (s, t) of the second layer memory 3 includes the pixel h (2s + 1, 2t + 1) (= m (s, t) −h (2s, 2t) −h (2s + 1, 2t) -h (2s, 2t + 1)) is written.

  Accordingly, the A bank address (2s + 1, 2t + 1) of the first layer memory 2 (here, there is no memory cell corresponding to this address, and therefore, nothing is written, for example, even if this address is accessed) The data read from the A bank address (s, t) of the second hierarchical memory 3 by the reading unit 47 at the timing when access is made to (not read) is the first hierarchical 2 as shown by D1 in FIG. The lower right pixel (pixel value) h (2s + 1, 2t + 1) out of 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) of x2 (However, h (4m + 3, 4n + 3) is excluded).

  On the other hand, when only the output of the AND gate 59 is 1 among the outputs of the AND gate 59 or 60 (therefore, the output of the AND gate 60 is 0), the selection circuit 58 outputs the output of the reading unit 47 to the first hierarchy. The pixel is selected and output. That is, when only the output of the AND gate 59 is 1, it is when both ha0 and va0 are 1 and either one of ha1 or va1 or both are 0, and D1 in FIG. The lower right pixel h (2) of 2 × 2 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first hierarchy as shown in FIG. 2s + 1, 2t + 1) (excluding h (4m + 3, 4n + 3)). Since the pixel h (2s + 1, 2t + 1) is read by the reading unit 47 from the A bank address (s, t) of the second hierarchical memory 3 as described above, the output of the reading unit 47 is output by the selection circuit 58. Selected and output.

  On the other hand, the reading unit 51 reads out the third layer pixel (pixel value) stored in the A bank address output from the selection circuit 34 from the third layer memory 4 via the selection circuit 43, and calculates the arithmetic unit 56. And is supplied to the selection circuit 58.

  Here, 4 × 4 16 pixels h (4m, 4n), h (4m + 1, 4n), h (4m + 2, 4n), h (4m + 3, 4n), h in the first layer as shown by D2 in FIG. (4m, 4n + 1), h (4m + 1, 4n + 1), h (4m + 2, 4n + 1), h (4m + 3, 4n + 1), h (4m, 4n + 2), h (4m + 1, 4n + 2), h (4m + 2, 4n + 2), h ( 4m + 3, 4n + 2), h (4m, 4n + 3), h (4m + 1, 4n + 3), h (4m + 2, 4n + 3), and h (4m + 3, 4n + 3) are accessed at any timing from the above. The A bank address (m, n) of the third hierarchy memory 4 is accessed.

  Accordingly, the reading unit 44 removes from the first layer memory 2 the first layer pixels h (4m, 4n), h excluding the lower right pixel h (2s + 1, 2t + 1) among the 2 × 2 pixels of the first layer. (4m + 1, 4n), h (4m + 2, 4n), h (4m + 3, 4n), h (4m, 4n + 1), h (4m + 2, 4n + 1), h (4m, 4n + 2), h (4m + 1, 4n + 2), h ( 4m + 2, 4n + 2), h (4m + 3, 4n + 2), h (4m, 4n + 3), h (4m + 2, 4n + 3) are read and supplied to the terminal 61a. Data is read from (m, n) and supplied to the computing unit 56.

  The switch 61 selects the terminal 61a when the output of the AND gate 59 is 0. Therefore, the first-layer pixels h (4m, 4n) and h (4m + 1, 4n) output from the readout unit 44 are selected. ), H (4m + 2, 4n), h (4m + 3, 4n), h (4m, 4n + 1), h (4m + 2, 4n + 1), h (4m, 4n + 2), h (4m + 1, 4n + 2), h (4m + 2, 4n + 2) , H (4m + 3, 4n + 2), h (4m, 4n + 3), h (4m + 2, 4n + 3) are supplied to the computing unit 56 via the switch 61.

  In addition, as described above, the reading unit 47 performs pixels h (4m + 1, 4n + 1), h (4m + 3, 4n + 1), corresponding to the lower right pixel h (2s + 1, 2t + 1) of the 2 × 2 pixels in the first layer, When outputting h (4m + 1, 4n + 3), that is, when the output of the AND gate 59 is 1, the switch 61 is configured to select the terminal 61b, and accordingly, the first layer output from the reading unit 47 is output. Pixels h (4m + 1, 4n + 1), h (4m + 3, 4n + 1), and h (4m + 1, 4n + 3) are also supplied to the calculator 56 via the switch 61.

  In the computing unit 56, the output of the switch 61 is subtracted from the output of the reading unit 51 and supplied to the writing unit 50. The writing unit 50 writes the output of the computing unit 56 to the A bank address (m, n) of the third hierarchy memory 4 via the selection circuit 43.

  Therefore, at first, the A-bank address (m, n) of the third-layer memory 4 has the third-layer pixel q (m, n), which is the added value of the above-mentioned 4 × 4 16 pixels in the first layer. ) Is stored, but the reading unit 44 reads the pixel h (4m, 4n) in the first layer, and the reading unit 51 is stored in the A bank address (m, n) of the third layer memory 4. The subtracted value (q (m, n) -h (4m, 4n)) is obtained by the computing unit 56 by reading the data (here, q (m, n)), and the writing unit 50 Are written in the A bank address (m, n) of the third hierarchical memory 4.

  Further, the reading unit 44 reads the pixel h (4m + 1, 4n) in the first layer, and the reading unit 51 stores data (here, the A bank address (m, n) of the third layer memory 4). , Q (m, n) −h (4m, 4n)), the subtracted value (q (m, n) −h (4m, 4n) −h (4m + 1,4n)) is obtained in the computing unit 56. ) Is obtained, and is written in the A bank address (m, n) of the third hierarchy memory 4 in the writing unit 50.

  Thereafter, similarly, the stored value of the A bank address (m, n) of the third hierarchy memory 4 is rewritten.

  When the reading unit 47 reads out the first layer pixel h (4m + 1, 4n + 1) corresponding to the lower right pixel h (2s + 1, 2t + 1) of the 2 × 2 pixels in the first layer, As described above, the data is supplied to the computing unit 56 via the switch 61. At this time, the A bank address (m, n) of the third hierarchy memory 4 has an expression q (m, n) −h (4m, 4n) −h (4m + 1, 4n) −h (4m + 2, 4n) −h. Data represented by (4m + 3, 4n) −h (4m, 4n + 1) is stored, and the reading unit 51 reads this data and supplies it to the computing unit 56.

  In the computing unit 56, the output of the reading unit 47 is subtracted from the output of the reading unit 51, and the subtraction value (q (m, n) -h (4m, 4n) -h (4m + 1,4n) -h (4m + 2,4n) is obtained. ) −h (4m + 3,4n) −h (4m, 4n + 1) −h (4m + 1,4n + 1)) is written to the A bank address (m, n) of the third hierarchy memory 4 by the writing unit 50.

  Thereafter, in the same manner, finally, that is, the reading unit 44 reads the pixel h (4m + 2, 4n + 3) in the first layer, and the reading unit 51 reads the A bank address (m, n) data (here, q (m, n) -h (4m, 4n) -h (4m + 1,4n) -h (4m + 2,4n) -h (4m + 3,4n) -h (4m , 4n + 1) -h (4m + 1,4n + 1) -h (4m + 2,4n + 1) -h (4m + 3,4n + 1) -h (4m, 4n + 2) -h (4m + 1,4n + 2) -h (4m + 2,4n + 2) -h (4m + 3) 4n + 2) −h (4m, 4n + 3) −h (4m + 1, 4n + 3)) is read out by the computing unit 56, and the writing unit 50 determines the A band of the third hierarchical memory 4. Address (m, n) is written into. That is, the A bank address (m, n) of the third layer memory 4 includes the first layer pixel h (4m + 3, 4n + 3) (= q (m, n) −h (4m, 4n) −h (4m + 1, 4n) -h (4m + 2,4n) -h (4m + 3,4n) -h (4m, 4n + 1) -h (4m + 1,4n + 1) -h (4m + 2,4n + 1) -h (4m + 3,4n + 1) -h (4m, 4n + 2) ) −h (4m + 1,4n + 2) −h (4m + 2,4n + 2) −h (4m + 3,4n + 2) −h (4m, 4n + 3) −h (4m + 1,4n + 3) −h (4m + 2,4n + 3)) is written.

  Therefore, the A bank address (4m + 3, 4n + 3) of the first layer memory 2 (here, there is no memory cell corresponding to this address, and therefore, nothing is written, for example, nothing is accessed even if this address is accessed. The data read by the reading unit 51 from the A bank address (m, n) of the third layer memory 4 is 4 in the first layer as indicated by D2 in FIG. Of the 16 pixels of × 4, the lower right pixel (pixel value) is h (4m + 3, 4n + 3).

  On the other hand, when both the outputs of the AND gates 59 and 60 are 1, the selection circuit 58 selects and outputs the output of the reading unit 51 as a pixel in the first hierarchy. That is, when both the outputs of the AND gates 59 and 50 are 1, this is when all of ha0, va0, ha1, va1 are 1, and 4 × of the first hierarchy as shown by D2 in FIG. This is the timing at which the lower right pixel h (4m + 3, 4n + 3) is read out of the four 16 pixels. Since the pixel h (4m + 3, 4n + 3) is read out from the A bank address (m, n) of the third hierarchical memory 4 by the reading unit 51 as described above, the output of the reading unit 51 is output by the selection circuit 58. Selected and output.

  By the way, when pixels in the first layer are read out as described above, the pixels h (2s + 1, 2t + 1) (however, h (4m + 3, 4n + 3) in the first layer are stored in the second layer memory 3. The third layer memory 4 stores the first layer pixels h (4m + 3, 4n + 3).

  That is, the stored value of the second hierarchy memory 3 or the third hierarchy memory 4 is rewritten from the second or third hierarchy pixel to the first hierarchy pixel.

  Therefore, it is necessary to return the stored values of the second hierarchy memory 3 or the third hierarchy memory 4 rewritten in this way to the original pixels of the second or third hierarchy, respectively. Not required).

  Therefore, as described above, the first hierarchy memory 2 is divided into the A bank for storing the pixels of the 8α to 8α + 3 lines and the B bank for storing the pixels of the 8α + 4 lines to the 8α + 7 lines. It is separated. Further, the second hierarchy memory 3 stores the A bank for storing the pixels of the 4α line and the 4α + 1 line of the second hierarchy, and the B for storing the pixels of the 4α + 2 line and the 4α + 3 line of the second hierarchy. The third hierarchy memory 4 is divided into A bank for storing the pixels of the second α line of the third hierarchy and B bank for storing the pixels of the second α + 1 line. Has been.

  In this embodiment, the delayed horizontal address HA and the delayed vertical address VA are obtained by delaying the horizontal address HA and the vertical address VA by four lines, and as described above, the horizontal address HA and the vertical address VA. Is selected as the A bank address, and the delayed horizontal address HA and the delayed vertical address VA are selected as the B bank addresses, respectively, in the first hierarchy memory 2, the A bank corresponding to the horizontal address HA and the vertical address VA At this time, at the same time, the memory cells in the B bank corresponding to the delayed horizontal address HA and the delayed vertical address VA accessed by the previous four lines (the memory cells in the A bank) are accessed. B bank memory cell corresponding to the location is not accessed. That.

  Similarly, in the second hierarchical memory 3, access is made to the memory cells in the A bank and access is made to the memory cells in the B bank that are accessed two lines before. Further, in the third hierarchical memory 4, access is made to the memory cells in the A bank, and access is made to the memory cells in the B bank that are accessed by one line before.

  Therefore, when the reading unit 44 reads the pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1) of the first layer from the A bank of the first layer memory 2, the reading unit 45 The pixels h (2s, 2t ′), h (2s + 1, 2t ′), h (2s) of the first layer accessed four lines before from the B bank of the first layer memory 2 via the selection circuit 41. , 2t ′ + 1) are read out and supplied to the computing unit 55. Here, t ′ = t−2.

  When the reading unit 45 reads out the pixels h (2s, 2t ′), h (2s + 1, 2t ′), and h (2s, 2t ′ + 1) of the first layer from the B bank of the first layer memory 2, In any case, the reading unit 49 reads data from the address (predetermined address) (s, t ′) in the B bank of the second hierarchical memory 3 via the selection circuit 42, and the arithmetic unit 55. To be supplied.

  In the computing unit 55, the output of the reading unit 45 and the output of the reading unit 49 are added, and the added value is supplied to the writing unit 48. The writing unit 48 writes the output of the calculator 55 to the B bank address (s, t ′) of the second hierarchical memory 3 via the selection circuit 42.

  Therefore, at first, the B bank address (s, t ′) of the second hierarchy memory 3 is obtained by being accessed by two lines before the second hierarchy (four lines for the first hierarchy). The first-layer pixel h (2s + 1, 2t ′ + 1) is stored, but the reading unit 45 reads the first-layer pixel h (2s, 2t ′) from the B bank of the first-layer memory 2. At the same time, the reading unit 49 reads the data (here, h (2s + 1, 2t ′ + 1)) stored in the B bank address (s, t ′) of the second hierarchy memory 3, so that the computing unit 55 The added value (h (2s, 2t ′) + h (2s + 1, 2t ′ + 1)) is obtained and written in the B bank address (s, t ′) of the second hierarchical memory 3 by the writing unit 48.

  Further, the reading unit 45 reads the pixel h (2s + 1, 2t ′) of the first layer from the B bank of the first layer memory 2, and the reading unit 49 reads the B bank address (s, By reading the data (here, h (2s, 2t ′) + h (2s + 1, 2t ′ + 1)) stored in t ′), the arithmetic unit 55 adds the added values (h (2s, 2t ′). ) + H (2s + 1, 2t) + h (2s + 1, 2t ′ + 1)) is obtained and written in the B bank address (s, t ′) of the second hierarchical memory 3 by the writing unit 48.

  After that, the reading unit 45 reads the pixel h (2s, 2t ′ + 1) of the first layer from the B bank of the first layer memory 2 and the reading unit 49 reads the B bank address (s of the second layer memory 3). , T ′) by reading out the data (here, h (2s, 2t ′) + h (2s + 1, 2t) + h (2s + 1, 2t ′ + 1)), the arithmetic unit 55 adds them. (H (2s, 2t ′) + h (2s + 1, 2t) + h (2s, 2t ′ + 1) + h (2s + 1, 2t ′ + 1)) is obtained, and the write unit 48 uses the B bank address ( s, t ′). In other words, the B bank address (s, t ′) of the second layer memory 3 includes the original second layer pixel m (s, t ′) (= h (2s, 2t ′) + h (2s + 1, 2t) + h. (2s, 2t ′ + 1) + h (2s + 1, 2t ′ + 1)) is written.

  In addition, the reading unit 44 removes the lower right pixel h (2s + 1, 2t + 1) out of the 2 × 2 pixels of the first hierarchy from the A bank of the first hierarchy memory 2, and the pixel h (4m, 4n) of the first hierarchy. ), H (4m + 1, 4n), h (4m + 2, 4n), h (4m + 3, 4n), h (4m, 4n + 1), h (4m + 2, 4n + 1), h (4m, 4n + 2), h (4m + 1, 4n + 2) , H (4m + 2, 4n + 2), h (4m + 3, 4n + 2), h (4m, 4n + 3), h (4m + 2, 4n + 3), the reading unit 45 selects the selection circuit from the B bank of the first hierarchy memory 2. 41, the pixels h (4m, 4n ′), h (4m + 1, 4n ′), h (4m + 2, 4n ′), h (4m + 3, 4n ′), h (4m, 4n '+ 1), h (4m + 2 4n ′ + 1), h (4m, 4n ′ + 2), h (4m + 1, 4n ′ + 2), h (4m + 2, 4n ′ + 2), h (4m + 3, 4n ′ + 2), h (4m, 4n ′ + 3), h (4m + 2, 4n ′ + 3) is read out and supplied to the computing unit 57. However, n ′ = n−1.

  Further, in this case, in the reading unit 53, data is read from the B bank address (m, n ′) of the third hierarchy memory 4 via the selection circuit 43 and supplied to the calculator 57.

  The computing unit 57 is also supplied with the output of the reading unit 49 via the switch 62. The switch 62 is turned on only when the output of the NOR gate 63 is at the H level (when ha0 = va0 = 0), and turned off otherwise. Accordingly, in the switch 62, the readout unit 49 causes the pixels h (4m + 1, 4n ′ + 1), h (4m + 3, 4n ′ + 1), h (4m + 1, 4n ′) of the first hierarchy from the B bank of the second hierarchy memory 3. +3) is turned on only when reading out. As a result, the pixels h (4m + 1, 4n ′ + 1), h (4m + 3, 4n ′ + 1), h (4m + 1, 4n ′ + 3) in the first layer are connected via the switch 62. To the calculator 57.

  In the computing unit 57, the output of the reading unit 45 and the output of the reading unit 53 are added, and when the switch 62 is on and the output of the reading unit 49 is supplied, the output is also added, The added value is supplied to the writing unit 52. The writing unit 52 writes the output of the arithmetic unit 57 to the B bank address (m, n ′) of the third hierarchy memory 4 via the selection circuit 43.

  Therefore, at first, the A bank address (m, n ′) of the third hierarchy memory 4 is obtained by being accessed by one line before the third hierarchy (four lines for the first hierarchy). The first-layer pixel h (4m + 3, 4n ′ + 3) is stored, but the readout unit 45 or 49 selects the first-layer pixel h (4m, 4n ′) or h (4m + 1, 4n ′ + 1). The readout unit 53 reads out the data (here, h (4m + 3, 4n ′ + 3)) stored in the B bank address (m, n ′) of the third hierarchy memory 4, thereby calculating the computing unit. 57, the added value (h (4m, 4n ′) + h (4m + 1, 4n ′ + 1) + h (4m + 3, 4n ′ + 3)) is obtained, and the B band of the third hierarchy memory 4 is obtained in the writing unit 52. Address (m, n ') are written in.

  Further, the readout unit 45 reads out the pixel h (4m + 1, 4n ′) in the first layer, and the readout unit 53 stores the data (the memory (B) (m, n ′) in the third layer memory 4 ( Here, by reading out h (4m, 4n ′) + h (4m + 1, 4n ′ + 1) + h (4m + 3, 4n ′ + 3)), the arithmetic unit 57 adds those values (h (4m, 4n ′) + h (4m + 1,4n ′) + h (4m + 1,4n ′ + 1) + h (4m + 3,4n ′ + 3)) is obtained and written to the B bank address (m, n ′) of the third-level memory 4 by the writing unit 52. .

  Thereafter, similarly, finally, that is, the reading unit 45 reads the pixel h (4m + 2, 4n ′ + 3) in the first layer, and the reading unit 53 reads the B bank address ( m, n ′) (here, h (4m, 4n ′) + h (4m + 1,4n ′) + h (4m + 2,4n ′) + h (4m + 3,4n ′) + h (4m, 4n ′ + 1) ) + H (4m + 1,4n ′ + 1) + h (4m + 2,4n ′ + 1) + h (4m + 3,4n ′ + 1) + h (4m, 4n ′ + 2) + h (4m + 1,4n ′ + 2) + h (4m + 2,4n ′ + 2) + h By reading (4m + 3, 4n ′ + 2) + h (4m, 4n ′ + 3) + h (4m + 1, 4n ′ + 3) + h (4m + 3, 4n ′ + 3)), the arithmetic unit 57 obtains the added value thereof. book In write unit 52, and written bank B address in the third layer memory 4 (m, n ') in the. That is, the B bank address (m, n ′) of the third layer memory 4 includes the original third layer pixel q (m, n ′) (= h (4m, 4n ′) + h (4m + 1, 4n ′). + H (4m + 2,4n ′) + h (4m + 3,4n ′) + h (4m, 4n ′ + 1) + h (4m + 1,4n ′ + 1) + h (4m + 2,4n ′ + 1) + h (4m + 3,4n ′ + 1) + h (4m, 4n ′ + 2) + h (4m + 1,4n ′ + 2) + h (4m + 2,4n ′ + 2) + h (4m + 3,4n ′ + 2) + h (4m, 4n ′ + 3) + h (4m + 1,4n ′ + 3) + h (4m + 2,4n ′) +3) + h (4m + 3, 4n ′ + 3)) is written.

  Thereafter, when the lower third bit va2 of the vertical address VA changes, in the selection circuit 32, the horizontal address HA and the vertical address VA supplied to the address supply circuit 1 are used as the B bank address, and the delayed horizontal address HA and the delayed vertical address VA. Are selected as A bank addresses, respectively.

  In this case, in the selection circuits 33 and 34, the A bank address and the B bank address are selected in the same manner. That is, in the selection circuit 33, the upper 8 bits ha1 to ha8 of the horizontal address HA and the upper 8 bits va1 to va8 of the vertical address VA are used as the B bank address as the upper 8 bits ha1 to ha8 and the delayed vertical address of the delayed horizontal address HA. The upper 8 bits va1 to va8 of VA are selected as A bank addresses, respectively. In the selection circuit 34, the upper 7 bits ha2 to ha8 of the horizontal address HA and the upper 7 bits va2 to va8 of the vertical address VA are used as the B bank address as the upper 7 bits ha2 to ha8 and the delayed vertical address of the delayed horizontal address HA. The upper 7 bits va2 to va8 of VA are selected as A bank addresses, respectively.

  The A bank address and the B bank address selected by the selection circuits 32 to 34 are supplied to the A bank address terminal and the B bank address terminal of the first hierarchy memory 2, the second hierarchy memory 3, or the third hierarchy memory 4, respectively. The

  Further, in the selection circuit 41, the B bank data terminal of the first hierarchy memory 2 is connected to the reading unit 44, and the A bank data terminal is connected to the reading unit 45. In the selection circuit 42, the B bank data terminal of the second hierarchical memory 3 is connected to the writing unit 46 and the reading unit 47, and the A bank data terminal is connected to the writing unit 48 and the reading unit 49. . Further, in the selection circuit 43, the B bank data terminal of the third hierarchy memory 4 is connected to the writing unit 50 and the reading unit 51, and the A bank data terminal is connected to the writing unit 52 and the reading unit 53. .

  Then, a process is performed in which A bank or B bank in the above-described process is replaced with B bank or A bank, respectively.

  Thereafter, the same processing is performed, and the first layer pixels are output from the selection circuit 58, and the contents stored in the second layer memory 3 and the third layer memory 4 rewritten accordingly are changed to the original values. It will be rewritten again.

  Next, FIG. 8 shows the storage device shown in FIG. 1 when reading the image of the second hierarchy when the first hierarchy memory 2 and the second hierarchy memory 3 have a small storage capacity as described above. The example of a structure is shown. In FIG. 8, the portion related to the first hierarchy memory 2 is not shown.

  In this case, the address supply circuit 1 includes a delay circuit 71 and selection circuits 73 and 74. The delay circuit 31 and the selection circuits 73 and 74 are configured in the same manner as the delay circuit 31 and the selection circuits 33 and 34 in FIG.

  Also, the second hierarchy memory 3 and the third hierarchy memory 4 are configured in the same manner as in FIG.

  Further, the RMW circuit 5 includes selection circuits 81 and 82, reading units 84 and 85, writing unit 86, reading unit 87, writing unit 88, reading unit 89, switches 91 and 92, arithmetic units 94 and 95, selection circuits 98, It consists of AND gates 99 and 100.

  Both the A bank data terminal and the B bank data terminal from which data (A bank data or B bank data) read from the A bank or B bank of the second hierarchical memory 3 is output are connected to the selection circuit 81. ing. The selection circuit 81 is supplied with the lower third bit va2 of the vertical address VA from the address supply circuit 1 as a control signal. In the selection circuit 81, the selection circuit 81 corresponds to the control signal va2. One of the A bank data terminal and the B bank data terminal is connected to the reading unit 84, and the other is connected to the reading unit 85.

  That is, at a certain point in time, for example, when the A bank data terminal or the B bank data terminal is connected to the reading unit 84 or 85, respectively, the selection circuit 81 changes the A bank data terminal or The B bank data terminal is connected to the reading unit 85 or 84, respectively. Further, after that, when the control signal va2 changes again, the selection circuit 81 connects the A bank data terminal or the B bank data terminal to the reading unit 84 or 85 again. Therefore, according to the selection circuit 81, every time the control signal va2 changes, the A bank data terminal is alternately connected to the reading unit 84 or 85, and the B bank data terminal is alternately connected to the reading unit 85 or 84. Is done.

  The data to be written to the A bank of the third hierarchy memory 4 is supplied, the A bank data terminal to which the data read from the A bank is output, and the data to be written to the B bank are supplied, and B The B bank data terminals to which data read from the bank are output are all connected to the selection circuit 82. The selection circuit 82 is also supplied with the lower third bit va2 of the vertical address VA from the address supply circuit 1 as a control signal. The selection circuit 82 corresponds to the control signal va2, One of the A bank data terminal and the B bank data terminal is connected to the writing unit 86 and the reading unit 87, and the other is connected to the writing unit 88 and the reading unit 89.

  That is, the selection circuit 82 is controlled at a certain point in time when, for example, the A bank data terminal is connected to the writing unit 86 and the reading unit 87 and the B bank data terminal is connected to the writing unit 88 and the reading unit 89. When the signal va2 changes, the A bank data terminal is connected to the writing unit 88 and the reading unit 89, and the B bank terminal is connected to the writing unit 86 and the reading unit 87. Further, after that, when the control signal va2 changes again, the selection circuit 82 reconnects the A bank data terminal to the writing unit 86 and the reading unit 87, and reconnects the B bank data terminal to the writing unit 88 and the reading unit 89. To do. Therefore, according to the selection circuit 82, every time the control signal va2 changes, the A bank data terminal is alternately connected to the writing unit 86 and the reading unit 87, or the writing unit 88 and the reading unit 89, and the B bank. Data terminals are alternately connected to the writing unit 88 and the reading unit 89 or between the writing unit 86 and the reading unit 87.

  The reading unit 84 or 85 reads data from the second hierarchy memory 3 via the selection circuit 81. The data read by the reading unit 84 is supplied to the terminal 91b of the switch 91 and the selection circuit 98. Further, the data read by the reading unit 85 is supplied to the terminal 92b of the switch 92. The writing unit 86 writes the output of the arithmetic unit 94 into the third hierarchy memory 4 via the selection circuit 82. The reading unit 87 reads data from the third hierarchy memory 4 via the selection circuit 82 and supplies the data to the arithmetic unit 94 and the selection circuit 98. The writing unit 88 is configured to write the output of the arithmetic unit 95 into the third hierarchy memory 4 via the selection circuit 82. The reading unit 89 reads data from the third hierarchy memory 4 via the selection circuit 82 and supplies the data to the arithmetic unit 95.

  The switch 91 selects one of the terminals 91a and 91b corresponding to the output of the AND gate 99, and the output is supplied to the arithmetic unit 94. Note that 0 is supplied to the terminal 91b. The switch 92 selects one of the terminals 92a and 92b corresponding to the output of the AND gate 99, and the output is supplied to the arithmetic unit 95. Note that 0 is supplied to the terminal 92b.

  The arithmetic unit 94 subtracts the output of the switch 91 from the output of the reading unit 87 and supplies the subtraction result to the writing unit 86. The computing unit 95 adds the output of the reading unit 89 and the output of the switch 92 and supplies the addition result to the writing unit 88.

  The selection circuit 98 selects and outputs one of the outputs of the reading unit 84 or 87 corresponding to the outputs of the AND gates 99 and 100. The AND gate 99 is supplied with the least significant bit ha0 of the horizontal address HA and the least significant bit va0 of the vertical address VA from the address supply circuit 1 as control signals. The logical product is calculated and supplied to the selection circuit 98 and the switches 91 and 92. The AND gate 100 is supplied from the address supply circuit 1 with the lower second bit ha1 of the horizontal address HA and the lower second bit va1 of the vertical address VA as control signals. The logical product is calculated and supplied to the selection circuit 98.

  Next, the operation will be described.

  Now, in the selection circuits 73 and 74, for example, the horizontal address HA and vertical address VA supplied to the address supply circuit 1 are selected as A bank addresses, and the delayed horizontal address HA and delayed vertical address VA are selected as B bank addresses, respectively. Suppose that

  That is, in the selection circuit 73, the upper 8 bits ha1 to ha8 of the horizontal address HA and the upper 8 bits va1 to va8 of the vertical address VA are used as the A bank address as the upper 8 bits ha1 to ha8 of the delayed horizontal address HA and the delayed vertical address. It is assumed that the upper 8 bits va1 to va8 of VA are selected as B bank addresses, respectively. In the selection circuit 74, the upper 7 bits ha2 to ha8 of the horizontal address HA and the upper 7 bits va2 to va8 of the vertical address VA are used as the A bank address as the upper 7 bits ha2 to ha8 of the delayed horizontal address HA and the delayed vertical address. It is assumed that the upper 7 bits va2 to va8 of VA are selected as B bank addresses.

  The A bank address and the B bank address selected by the selection circuit 73 or 74 are supplied to the A bank address terminal and the B bank address terminal of the second hierarchical memory 3 or the third hierarchical memory 4, respectively.

  Further, in this case, in the selection circuit 81, the A bank data terminal of the second hierarchical memory 3 is connected to the reading unit 84 and the B bank data terminal is connected to the reading unit 85. In the selection circuit 82, the A bank data terminal of the third hierarchy memory 4 is connected to the writing unit 86 and the reading unit 87, and the B bank data terminal is connected to the writing unit 88 and the reading unit 89. .

  The readout unit 84 reads out the second layer pixel (pixel value) stored in the A bank address output from the selection circuit 73 from the second layer memory 3 via the selection circuit 81, and outputs the terminal 91 b of the switch 91. And is supplied to the selection circuit 98.

  For example, when only the output of the AND gate 99 is 1 among the outputs of the AND gates 99 and 100, the selection circuit 98 selects and outputs the output of the reading unit 84 as a pixel in the second hierarchy. That is, when only the output of the AND gate 99 is 1, it is when both ha0 and va0 are 1 and either one of ha1 or va1 or both are 0, and D1 in FIG. As shown in the figure, the lower right pixel h (2) of 2 × 2 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first hierarchy as shown in FIG. 2s + 1, 2t + 1) (excluding h (4m + 3, 4n + 3)).

  On the other hand, from the above, the timing at which access is made to 2 × 2 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first layer. In any case, the pixel m (s, t) in the second layer is accessed. Therefore, at any timing when the 2 × 2 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first layer are accessed. If the data read from the second hierarchy memory 3, that is, the pixel m (s, t) of the second hierarchy is output, the same pixel is output four times.

  Therefore, in the selection circuit 98, the lower right of the 2 × 2 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first layer The output of the reading unit 84, that is, the pixel m (s, t) in the second layer is selected only at the timing when the pixel h (2s + 1, 2t + 1) (except the pixel h (4m + 3, 4n + 3)) is read out. Is output.

  For the same reason, the switch 91 also selects the terminal 91b only at the timing when the pixel h (2s + 1, 2t + 1) in the first layer is output from the readout unit 84 (the timing when the output of the AND gate 99 becomes 1). In other cases, the terminal 91a is selected. In other words, the arithmetic unit 94 has 2 × 2 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first layer. Only at the timing when the lower right pixel h (2s + 1, 2t + 1) is read out, the pixel m (s, t) of the second hierarchy output from the reading unit 84 is supplied, and 0 is supplied in other cases.

  On the other hand, the readout unit 87 reads out the third layer pixel (pixel value) stored in the A bank address output from the selection circuit 74 from the third layer memory 4 via the selection circuit 82, and calculates the arithmetic unit 94. And is supplied to the selection circuit 98.

  That is, in the reading unit 87, the addresses (4m, 4n), (4m + 1, 4n), (4m + 2, 4n), (4m + 3, 4n), (4m, 4n + 1), (4m + 1, 4n + 1), (4m + 1, 4n + 1), (4m + 2, 4n + 1), (4m + 3, 4n + 1), (4m, 4n + 2), (4m + 1, 4n + 2), (4m + 2, 4n + 2), (4m + 3, 4n + 2), (4m, 4n + 3), (4m + 1, 4n + 3), (4m + 2) , 4n + 3), (4m + 3, 4n + 3), the data is read from the A bank address (m, n) of the third layer memory 4 and supplied to the arithmetic unit 94 at any timing.

  As described above, the switch 91 is an address excluding (4m + 1, 4n + 1), (4m + 3, 4n + 1), (4m + 1, 4n + 3), and (4m + 3, 4n + 3) corresponding to the address (2s + 1, 2t + 1) of the first hierarchy memory 2. (4m, 4n), (4m + 1, 4n), (4m + 2, 4n), (4m + 3, 4n), (4m, 4n + 1), (4m + 2, 4n + 1), (4m, 4n + 2), (4m + 1, 4n + 2), (4m + 2) , 4n + 2), (4m + 3, 4n + 2), (4m, 4n + 3), and (4m + 2, 4n + 3), the terminal 91b is selected. Accordingly, in this case, the arithmetic unit 94 subtracts 0 from the data read from the A bank address (m, n) of the third hierarchy memory 4, and the subtraction value, ie, the third hierarchy memory 4 The data itself read from the A bank address (m, n) is supplied to the writing unit 86. In the writing unit 86, the data from the arithmetic unit 94 is written to the A bank address (m, n) of the third hierarchy memory 4 via the selection circuit 82. Accordingly, in this case, the stored value of the A bank address (m, n) of the third hierarchy memory 4 remains unchanged.

  On the other hand, at the timing when the addresses (4m + 1, 4n + 1), (4m + 3, 4n + 1), and (4m + 1, 4n + 3) of the first hierarchy memory 2 are accessed, the switch 91 selects the terminal 91b. In this case, in the reading unit 84, the pixels m (2m, 2n), m (2m + 1, 2n), and m (2m, 2n + 1) in the second layer are read from the second layer memory 3 and the switch 91 is turned on. To the arithmetic unit 94.

  In the arithmetic unit 94, the output of the reading unit 84 is subtracted from the output of the reading unit 87 and supplied to the writing unit 86. The writing unit 86 writes the output of the arithmetic unit 94 to the A bank address (m, n) of the third hierarchy memory 4 via the selection circuit 82.

  Therefore, at first, the A bank address (m, n) of the third layer memory 4 has 4 × 4 16 pixels h (4m, 4n), h (4m + 1, 4n), h (4m + 2, 2) in the first layer. 4n), h (4m + 3, 4n), h (4m + 4n + 1), h (4m + 1, 4n + 1), h (4m + 2, 4n + 1), h (4m + 3, 4n + 1), h (4m, 4n + 2), h (4m + 1, 4n + 2) ), H (4m + 2, 4n + 2), h (4m + 3, 4n + 2), h (4m, 4n + 3), h (4m + 1, 4n + 3), h (4m + 2, 4n + 3), h (4m + 3, 4n + 3), A third-layer pixel q (m, 2), which is an addition value of 2 × 2 4 pixels m (2m, 2n), m (2m + 1,2n), m (2m, 2n + 1), m (2m + 1,2n + 1) in two layers. n) is stored, but the first layer At the timing when the address (4m + 1, 4n + 1) of the memory 2 is accessed, the arithmetic unit 94 is supplied with the pixel m (2m, 2n) of the second hierarchy from the readout unit 84 via the switch 91. The data (here, q (m, n)) stored in the A bank address (m, n) of the third hierarchy memory 4 is supplied from the reading unit 87.

  The arithmetic unit 94 obtains these subtraction values (q (m, n) -m (2m, 2n)) and writes them in the A bank address (m, n) of the third hierarchy memory 4 in the writing unit 86. .

  Further, at the timing when the address (4m + 3, 4n + 1) of the first hierarchy memory 2 is accessed, the arithmetic unit 94 sends the pixel m (2m + 1, 2n) of the second hierarchy from the readout unit 84 via the switch 91. And the data stored in the A bank address (m, n) of the third hierarchy memory 4 (here, q (m, n) −m (2m, 2n)) are supplied from the reading unit 87. Supplied.

  The arithmetic unit 94 obtains these subtraction values (q (m, n) −m (2m, 2n) −m (2m + 1,2n)), and the writing unit 86 uses the A bank address ( m, n).

  Thereafter, when it is time to access the address (4m + 1, 4n + 3) of the first hierarchy memory 2, the computing unit 94 receives the pixel m (2m, 2n + 1) of the second hierarchy from the readout unit 84 via the switch 91. Is supplied from the reading unit 87 to the data (here, q (m, n) −m (2m, 2n) −m) stored in the A bank address (m, n) of the third hierarchical memory 4. (2m + 1, 2n)) is supplied.

  The arithmetic unit 94 obtains these subtraction values (q (m, n) -m (2m, 2n) -m (2m + 1,2n) -m (2m, 2n + 1)). The data is written to the A bank address (m, n) of the memory 4.

  That is, the A bank address (m, n) of the third layer memory 4 includes the pixel m (2m + 1, 2n + 1) (= q (m, n) -m (2m, 2n) -m (2m + 1, 2n) -m (2m, 2n + 1)) is written.

  Therefore, the A bank address (4m + 3, 4n + 3) of the first layer memory 2 (here, there is no memory cell corresponding to this address, and therefore, nothing is written, for example, nothing is accessed even if this address is accessed. At the timing when access is made at the time of not being read (the timing at which access is made to the A bank address (2m + 1, 2n + 1) of the second hierarchy memory 3 (there is no memory cell corresponding to this address)) The data read out from the A bank address (m, n) of the third layer memory 4 by the unit 87 is 2 × 4 in the lower right of the 16 × 4 pixels in the first layer as indicated by D2 in FIG. 2 pixels h (4m + 2, 4n + 2), h (4m + 3, 4n + 2), h (4m + 2, 4n + 3), h (4m + 3, 4n + 3) added value (second layer) Pixel m (2m + 1, 2n + 1)).

  On the other hand, when both the outputs of the AND gates 99 and 100 are 1, the selection circuit 98 selects and outputs the output of the reading unit 51 as the second-layer pixel. That is, when both the outputs of the AND gates 99 and 50 are 1, it is when all of ha0, va0, ha1, and va1 are 1, and the address (4m + 3, 4n + 3) of the first hierarchy memory 2 is accessed. Is the timing when At this timing, as described above, the data read by the reading unit 87 from the A bank address (m, n) of the third hierarchy memory 4 is the pixel m (2m + 1, 2n + 1) in the second hierarchy. Data is selected by the selection circuit 98 and output.

  By the way, when the pixels of the second hierarchy are read out as described above, the pixels m (2m + 1, 2n + 1) of the second hierarchy are stored in the third hierarchy memory 4 as in the case of FIG. Will come to be.

  That is, the stored value of the third hierarchy memory 4 is rewritten from the pixel of the third hierarchy to the pixel of the second hierarchy.

  Therefore, it is necessary to return the stored value of the third layer memory 4 rewritten in this way to the original pixel of the third layer.

  Therefore, as described above, for example, when the horizontal address HA and the vertical address VA are selected as the A bank address and the delayed horizontal address HA and the delayed vertical address VA are selected as the B bank address, respectively, the first hierarchical memory 2, the memory cells in the A bank corresponding to the horizontal address HA and the vertical address VA are accessed. At this time, the delayed horizontal address HA and the delayed vertical address accessed at the same time four lines earlier are simultaneously accessed. A memory cell in B bank corresponding to VA is also accessed.

  Similarly, in the second hierarchical memory 3, access is made to the memory cells in the A bank and access is made to the memory cells in the B bank that are accessed two lines before. Further, in the third hierarchical memory 4, access is made to the memory cells in the A bank, and access is made to the memory cells in the B bank that are accessed by one line before.

  Therefore, when the reading unit 84 reads the pixels m (2m, 2n), m (2m + 1, 2n), and m (2m, 2n + 1) in the second layer from the A bank of the second layer memory 3, the reading unit 85 The second layer pixels m (2m, 2n ′), m (2m + 1, 2n ′), and m (2m, 2n ′ + 1) are respectively transmitted from the B bank of the second layer memory 3 via the selection circuit 81. It is read out and supplied to the terminal b of the switch 92. Here, n ′ = n−1.

  Similarly to the switch 91, the switch 92 selects the terminal 92b only at the timing when the pixel h (2s + 1, 2t + 1) in the first layer is output from the reading unit 84 (the timing when the output of the AND gate 99 becomes 1). In other cases, the terminal 92a is selected. In other words, the computing unit 95 has 2 × 2 4 pixels h (2s, 2t), h (2s + 1, 2t), h (2s, 2t + 1), h (2s + 1, 2t + 1) in the first layer. Only at the timing when the lower right pixel h (2s + 1, 2t + 1) is read out, the second layer pixel output from the reading unit 85 is supplied, and in other cases, 0 is supplied.

  When the reading unit 85 reads out the pixels m (2m, 2n ′), m (2m + 1, 2n ′), and m (2m, 2n ′ + 1) in the second layer from the B bank of the second layer memory 3. In any case, the reading unit 89 reads data from the address (m, n ′) in the B bank of the third hierarchy memory 4 via the selection circuit 82 and supplies the data to the arithmetic unit 95.

  In the arithmetic unit 95, the output of the reading unit 85 and the output of the reading unit 89 are added, and the added value is supplied to the writing unit 88. The writing unit 88 writes the output of the arithmetic unit 95 to the B bank address (m, n ′) of the third hierarchy memory 4 via the selection circuit 82.

  Therefore, at first, the B bank address (m, n ′) of the third layer memory 4 is obtained by being accessed by two lines before the second layer (four lines for the first layer). The second-layer pixel m (2m + 1, 2n ′ + 1) is stored, but the reading unit 85 reads the second-layer pixel m (2m, 2n ′) from the B bank of the second-layer memory 3. At the same time, the reading unit 89 reads the data (here, the pixel m (2m + 1, 2n ′ + 1) in the second hierarchy) stored in the B bank address (m, n ′) of the third hierarchy memory 4. The arithmetic unit 95 obtains the added value (m (2m, 2n ′) + m (2m + 1, 2n ′ + 1)), and the writing unit 88 stores the B bank address (m, n ′) of the third hierarchy memory 4. ) That.

  Further, the reading unit 85 reads the pixel m (2m + 1, 2n ′) of the second hierarchy from the B bank of the second hierarchy memory 3, and the reading unit 89 reads the B bank address (m, n ′) by reading out the data (here, m (2m, 2n ′) + m (2m + 1, 2n ′ + 1)), the arithmetic unit 95 adds those values (m (2m, 2n ′) ) + M (2m + 1, 2n) + m (2m + 1, 2n ′ + 1)) is obtained and written to the B bank address (m, n ′) of the third-level memory 4 by the writing unit 88.

  Thereafter, the readout unit 85 reads out the pixel m (2m, 2n ′ + 1) of the second hierarchy from the B bank of the second hierarchy memory 3, and the readout unit 89 reads the B bank address (m of the third hierarchy memory 4). , N ′) (in this case, m (2m, 2n ′) + m (2m + 1, 2n) + m (2m + 1, 2n ′ + 1)) is read out by the arithmetic unit 95. (M (2m, 2n ′) + m (2m + 1, 2n) + m (2m, 2n ′ + 1) + m (2m + 1, 2n ′ + 1)) is obtained, and the B bank address (third layer memory 4) ( m, n ′). That is, the B bank address (m, n ′) of the third layer memory 4 includes the original third layer pixel q (m, n ′) (= m (2m, 2n ′) + m (2m + 1, 2n) + m. (2m, 2n ′ + 1) + m (2m + 1, 2n ′ + 1) = h (4m, 4n), h (4m + 1, 4n), h (4m + 2, 4n), h (4m + 3, 4n), h (4m, 4n + 1) , H (4m + 1, 4n + 1), h (4m + 2, 4n + 1), h (4m + 3, 4n + 1), h (4m, 4n + 2), h (4m + 1, 4n + 2), h (4m + 2, 4n + 2), h (4m + 3, 4n + 2), h (4m, 4n + 3), h (4m + 1, 4n + 3), h (4m + 2, 4n + 3), h (4m + 3, 4n + 3)) are written.

  Thereafter, when the lower third bit va2 of the vertical address VA changes, the selection of the A bank address and the B bank address is changed in the selection circuits 73 and 74. That is, in the selection circuit 73, the upper 8 bits ha1 to ha8 of the horizontal address HA and the upper 8 bits va1 to va8 of the vertical address VA are used as the B bank address as the upper 8 bits ha1 to ha8 and the delayed vertical address of the delayed horizontal address HA. The upper 8 bits va1 to va8 of VA are selected as A bank addresses, respectively. In the selection circuit 74, the upper 7 bits ha2 to ha8 of the horizontal address HA and the upper 7 bits va2 to va8 of the vertical address VA are used as the B bank address as the upper 7 bits ha2 to ha8 and the delayed vertical address of the delayed horizontal address HA. The upper 7 bits va2 to va8 of VA are selected as A bank addresses, respectively.

  The A bank address and the B bank address selected by the selection circuit 73 or 74 are supplied to the A bank address terminal and the B bank address terminal of the second hierarchy memory 3 or the third hierarchy memory 4, respectively.

  Further, in the selection circuit 81, the B bank data terminal of the second hierarchy memory 3 is connected to the reading unit 84 and the A bank data terminal is connected to the reading unit 85. In the selection circuit 82, the B bank data terminal of the third hierarchy memory 4 is connected to the writing unit 86 and the reading unit 87, and the A bank data terminal is connected to the writing unit 88 and the reading unit 89. .

  Then, a process is performed in which A bank or B bank in the above-described process is replaced with B bank or A bank, respectively.

  Thereafter, the same processing is performed, and the pixels of the second hierarchy are output from the selection circuit 98, and the storage contents of the third hierarchy memory 4 rewritten accordingly are rewritten to the original values.

  As described above, the first hierarchy memory 2, the second hierarchy memory 3, and the third hierarchy memory 4 are divided into two banks A and B, and both banks are accessed in parallel. Thus, the stored values of the second hierarchy memory 3 and the third hierarchy memory 4 can be rewritten to the pixels of the first or second hierarchy, and the rewritten data can be rewritten to the original data again.

  That is, for example, the pixel of the first layer stored in the A bank address of the first layer memory 2 designated by the horizontal address HA and the vertical address VA is read and designated by a part of the horizontal address HA and the vertical address VA. The second layer pixel (first processing data) stored in the A bank address of the second layer memory 3 is read and the first layer pixel is subtracted from the second layer pixel to obtain the final Specifically, the first pixel (second processing data) can be calculated and written to the address of the second hierarchical memory 3 in which the second hierarchical pixel was stored. At the same time, the pixels of the first hierarchy stored in the B bank address of the first hierarchy memory 2 designated by the delayed horizontal address HA and the delayed vertical address VA are read, and the delayed horizontal address HA and the delayed vertical address VA are read. By reading the first layer pixels (second processing data) stored in the B bank address of the second layer memory 3 specified by a part of the first layer pixels, and adding the pixels of the first layer, Finally, the original second layer pixel (first processing data) is calculated, and the second layer pixel is replaced with the B bank address of the second layer memory 3 rewritten to the first layer pixel. The stored value can be rewritten again.

  In the present embodiment, the first hierarchy memory 2, the second hierarchy memory 3, and the third hierarchy memory 4 are divided into two banks, A bank and B bank. As described above, the present invention is not limited to this.

  In this embodiment, addition or subtraction is performed using data read from the A bank or B bank. However, processing using data read from the A bank or B bank is performed using addition or subtraction. It is not limited to subtraction.

  Further, in the present embodiment, the second hierarchical memory 3 and the third hierarchical memory 4 are accessed by giving a part of the horizontal address HA and the vertical address VA given to the first hierarchical memory 2. The second hierarchical memory 3 and the third hierarchical memory 4 may be accessed by giving dedicated (independent) addresses separately from the horizontal address HA and the vertical address VA given to the first hierarchical memory 2. Is possible.

  In the present embodiment, the horizontal address or the vertical address corresponding to the horizontal or vertical position of the pixels constituting the image with respect to the first hierarchical memory 2, the second hierarchical memory 3, and the third hierarchical memory 4, respectively. However, for example, the first hierarchical memory 2, the second hierarchical memory 3, and the third hierarchical memory 4 may be accessed by further giving addresses corresponding to the time direction, for example. Etc. are also possible. In this case, the second and third layer pixels are formed by adding the first layer pixels scattered in the time direction in addition to the first layer pixels scattered in the horizontal and vertical spatial directions.

  Furthermore, the first hierarchy memory 2, the second hierarchy memory 3, and the third hierarchy memory 4 do not have to be physically one memory, and all of them can be configured by one memory. . In this case, the storage area of one memory may be allocated to each of the first hierarchy memory 2, the second hierarchy memory 3, and the third hierarchy memory 4.

  In this embodiment, the address supply circuit 1, the first hierarchy memory 2, the second hierarchy memory 3, the third hierarchy memory 4, and the RMW circuit 5 are all formed on one chip. These are not necessarily formed on one chip.

  Furthermore, in the present embodiment, the bit allocation amount of the pixels in the first hierarchy is 8 bits, and the data length of the memory cells in the first hierarchy memory 2, the second hierarchy memory 3, or the third hierarchy memory 4 is set to the first Or 8 bits, 10 bits, or 12 bits so as not to drop the pixels in the third layer, but the data lengths of the memory cells of the first layer memory 2, the second layer memory 3, and the third layer memory 4 For example, it may be uniformly 8 bits. However, in this case, for pixels in the second or third hierarchy, a value obtained by rounding down the lower 2 bits of the addition value of the 2 × 2 pixels in the first or second hierarchy (this value is obtained by dividing the addition value by 4). Therefore, the loss of data will be lost.

  That is, for example, as described above, when the storage capacities of the first hierarchy memory 2 and the second hierarchy memory 3 are reduced and some of the pixels of the first and second hierarchies are not stored, digits are lost. If not, the first-layer pixels and the second-layer pixels (pixel values) that are not stored can be accurately obtained by the above formulas (1) and (2). On the other hand, when a part of the pixels of the first and second hierarchies is not memorized and a digit loss occurs, the pixels of the first hierarchies and the pixels of the second hierarchies that are not memorized are stored. Will not be able to determine the exact value.

  The present invention is applicable to both non-interlaced scanned images and interlaced scanned images.

  Furthermore, in the present embodiment, the number of hierarchies is three, but the number of hierarchies may be two, or four or more.

  In the present embodiment, the addition value of 2 × 2 4 pixels in the lower layer is set as the upper layer pixel (pixel value) that is one level higher. Is not limited to this.

  Furthermore, in the present embodiment, the present invention is realized by hardware, but the present invention can also be realized by causing a computer to execute a program that performs the above-described processing.

  In this embodiment, pixels (pixel values) are stored in a memory represented by, for example, a RAM (Random Access Memory). However, the pixels may be stored in, for example, a magnetic disk or a magneto-optical device. It is also possible to store (record) in a recording medium such as a disk, a magnetic tape, or an optical card.

It is a block diagram which shows the structural example of one Embodiment of the memory | storage device of this invention. It is a figure which shows the structural example of 1 screen of the image of a 1st hierarchy. FIG. 2 is a block diagram illustrating a first functional configuration example of the storage device of FIG. 1. FIG. 3 is a block diagram illustrating a second functional configuration example of the storage device in FIG. 1. FIG. 4 is a block diagram illustrating a third functional configuration example of the storage device in FIG. 1. FIG. 6 is a block diagram illustrating a fourth functional configuration example of the storage device in FIG. 1. It is a figure for demonstrating the 1st hierarchy memory 2 of FIG. 6 divided | segmented into A bank and B bank. FIG. 7 is a block diagram illustrating a fifth functional configuration example of the storage device in FIG. 1. It is a figure for demonstrating hierarchical encoding.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Address supply circuit, 2 1st hierarchy memory, 3 2nd hierarchy memory, 4 3rd hierarchy memory, 5 RMW circuit, 11 reading part, 12 switch, 12a, 12b terminal, 13 calculator, 14 writing part, 15 NOR gate , 16 switch, 21 reading unit, 22 switch, 22a, 22b terminal, 23 arithmetic unit, 24 writing unit, 25 NOR gate, 26 switch, 31 delay circuit, 32 to 34, 41 to 43 selection circuit, 44, 45 reading unit , 46 writing unit, 47 reading unit, 48 writing unit, 49 reading unit, 50 writing unit, 51 reading unit, 52 writing unit, 53 reading unit, 54 to 57 computing unit, 58 selection circuit, 59, 60 AND gate, 61 Sui , 61a, 61b terminal, 62 switch, 63 NOR gate, 71 delay circuit, 73, 74, 81, 82 selection circuit, 84, 85 read unit, 86 write unit, 87 read unit, 88 write unit, 89 read unit, 91 Switch, 91a, 91b terminal, 92 switch, 92a, 92b terminal, 94, 95 arithmetic unit, 98 selection circuit, 99, 100 AND gate

Claims (6)

Image data composed of a smaller number of pixels than the input image data from the input image data, and obtained by adding pixel values of a plurality of pixels at predetermined positions among the pixels constituting the input image data. The obtained value is used as a pixel value, and is used when hierarchical data, which is image data composed of each of the pixels determined corresponding to the plurality of pixels, is calculated and hierarchical encoding is performed. A storage device for storing the hierarchical data,
A first address is specified by a first address corresponding to a horizontal position and a vertical position that specify a pixel position constituting the input image data, and each of the pixel values of the input image data is stored at the specified address. Storage means,
Addressed by a second address represented by a part of the bit string representing the first address, and for calculating the pixel value of the hierarchical data from the pixel value of the input image data at the designated address From the first processing data which is data in the middle of processing, the pixel value of the hierarchical data calculated using the first processing data and the pixel value of the input image data, or the pixel value of the input image data Second processing data which is data in the middle of processing for calculating pixel values of the input image data not stored in the first storage means, or pixel values of the second processing data and the input image data Second storage means for storing pixel values of the input image data that are not stored in the first storage means calculated using
Controlling reading and writing of data to and from the first and second storage means, and processing for calculating the pixel value of the hierarchical data for the data or processing for calculating the pixel value of the input image data A storage device. The first storage means is divided into a plurality of simultaneously accessible blocks based on addresses designated for each;
The second storage means is a plurality of blocks that can be simultaneously accessed based on addresses designated for each, and is divided into the same number of blocks corresponding to each of the blocks of the first storage means And
The first processing data or the pixel value of the hierarchical data is stored in a first block of the blocks of the second storage means,
The storage device according to claim 1, wherein a pixel value of the second processing data or the input image data is stored in a second block of the blocks of the second storage unit. The first address designating a third block of the blocks of the first storage means and the second address designating the first block of the second storage means are simultaneously generated. Addressing means;
The first address is delayed by shifting the pixel position specified by the first address by the amount of the pixel column specified based on the difference in the number of pixels of the input image data and the hierarchical data. An address represented by a first delay address designating a fourth block of the blocks of the first storage means and a part of a bit string representing the first delay address, A second delay address designating the second block of the second storage means, and a delay address designating means for generating at the same time as the first address and the second address are generated. The storage device according to claim 2. In each block of the first storage means, the number of individual storage areas corresponding to the designated address is determined based on the number of pixels constituting one screen of the input image data. The storage device according to claim 3, wherein the number is obtained by subtracting the number of addresses that can be specified in a block. The control means includes
The first area specified by the plurality of first addresses corresponding to the second address in the storage area of the second storage means specified by the second address generated by the address specifying means. A first process for writing pixel values of the first process data or the hierarchical data obtained by adding data written to each of the storage areas of the storage means;
Read the pixel value of the hierarchical data stored in the storage area of the second storage means specified by the second delay address generated by the delay address specifying means, and from the pixel value of the hierarchical data, Obtained by subtracting the pixel value of the input image data stored in each of the storage areas of the first storage means specified by the plurality of first delay addresses corresponding to the second delay address. A second value for writing the pixel value of the input image data not stored in the second processing data or the first storage means to the storage area of the second storage means specified by the second delay address. The storage device according to claim 4, wherein: Image data composed of a smaller number of pixels than the input image data from the input image data, and obtained by adding pixel values of a plurality of pixels at predetermined positions among the pixels constituting the input image data. The obtained value is used as a pixel value, and is used when hierarchical data, which is image data composed of each of the pixels determined corresponding to the plurality of pixels, is calculated and hierarchical encoding is performed. A storage device for storing the hierarchical data,
A first address is specified by a first address corresponding to a horizontal position and a vertical position that specify a pixel position constituting the input image data, and each of the pixel values of the input image data is stored at the specified address. Storage means,
Addressed by a second address represented by a part of the bit string representing the first address, and for calculating the pixel value of the hierarchical data from the pixel value of the input image data at the designated address The first processing data that is data in the middle of processing, the pixel value of the hierarchical data calculated using the first processing data and the pixel value of the input image data, or the first image data based on the input image data. Stored in the second storage data or the second processing data and the first storage means, which is data in the middle of processing for calculating the pixel value of the input image data not stored in the storage means. And a second storage means for storing each of the pixel values of the input image data calculated using the pixel values of the input image data not included in the storage device. A that access method,
Simultaneously storing each of the pixel values of the input image data in the first storage means,
In the second storage means, the first processing data which is data in the middle of processing for calculating the pixel value of the hierarchical data from the pixel value of the input image data, or the first processing data and the input image The hierarchical data calculated using the pixel value of the data, or data in the middle of processing for calculating the pixel value of the input image data not stored in the first storage means from the input image data Second processing data, or pixel values of the input image data not stored in the first storage means calculated using the second processing data and the pixel values of the input image data are stored. how to access.

Images