JP4273782B2 - Semiconductor device manufacturing method and semiconductor substrate manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device and a method of manufacturing a semiconductor substrate, and in particular, a technique effective for easily and surely realizing a SON (Silicon On Notifying) structure called an ultimate SOI (Silicon On Insulator) structure. About.
[0002]
[Prior art]
In order to realize high performance and low power consumption of semiconductor devices, device development using an SOI structure in which a semiconductor layer is laminated on a semiconductor substrate via an insulating layer is being actively performed.
In recent years, holes (ESS: Empty Space Silicon) have been formed in a semiconductor substrate in order to make it possible to achieve higher performance and lower power consumption by the SOI structure, and the air present in the holes is used as an insulator. The SON structure to function has been attracting attention.
[0003]
One method for manufacturing a semiconductor substrate having this SON structure will be described with reference to FIG. FIG. 9 is a cross-sectional view showing one manufacturing process of a semiconductor substrate having a conventional SON structure.
First, as shown in FIG. 9A, a plurality of grooves (recesses) 10 h are two-dimensionally formed on the surface of the semiconductor substrate 10.
[0004]
Next, the semiconductor substrate 10 is subjected to high-temperature annealing in a hydrogen atmosphere, and as shown in FIG. 9B, the surface is recrystallized by the surface migration phenomenon of Si, as shown in FIG. 9C. In addition, one flat hole portion 10H in which a plurality of grooves 10h are connected in the semiconductor substrate 10 is formed (for example, see Patent Document 1).
[0005]
[Patent Document 1]
JP 2001-144276 A.
[0006]
[Problems to be solved by the invention]
However, in the method for manufacturing a semiconductor substrate described in Patent Document 1 described above, since the single crystal semiconductor layer formed on the surface of the semiconductor substrate by recrystallization becomes an element region, the layer thickness of the single crystal semiconductor layer is controlled. It was difficult to do. For this reason, if the single crystal semiconductor layer is to be thinned in order to realize further miniaturization and higher performance of the device, the surface of the semiconductor substrate is thermally oxidized and then etched or etched by CMP (Chemical Mechanical Polishing). A complicated process was necessary.
[0007]
In the method for manufacturing a semiconductor substrate described in Patent Document 1 described above, a plurality of grooves 10h formed on the surface of the semiconductor substrate 10 are connected to form a cavity 10H on one flat plate. It has been difficult to selectively build a SON structure for each element formed on the substrate 10.
The present invention has been made in view of the above circumstances, and can manufacture a single crystal semiconductor layer as an element formation region, and can manufacture a SON structure selectively on an element basis. It is an object of the present invention to provide a method and a method for manufacturing a semiconductor substrate.
[0008]
[Means for Solving the Problems]
In order to solve such problems, the present inventor has intensively studied, and as a result, has found that the above problems can be solved by devising a method for manufacturing a void portion formed in a semiconductor substrate. It came to an eggplant.
That is, a first manufacturing method of a semiconductor device according to the present invention includes a step of forming a porous semiconductor layer in a semiconductor substrate at least in an element formation region, and a heat treatment on the semiconductor substrate, and at least the porous semiconductor layer A step of crystallizing the vicinity of the surface of the substrate, a step of forming a first single crystal semiconductor layer over the entire surface of the semiconductor substrate including the porous semiconductor layer, and an opening in a part of the first single crystal semiconductor layer And exposing a part of the porous semiconductor layer; etching the porous semiconductor layer from the opening; and forming a hole in the semiconductor substrate that is at least an element formation region; And a step of closing the opening, and a step of forming a semiconductor element in the first single crystal semiconductor layer immediately above the hole.
[0009]
A second manufacturing method of a semiconductor device according to the present invention includes a step of forming a porous semiconductor layer in a semiconductor substrate at least in an element formation region, and a heat treatment on the semiconductor substrate, and at least a surface of the porous semiconductor layer A step of crystallizing the vicinity, a step of forming a first single crystal semiconductor layer on the entire surface of the semiconductor substrate including the porous semiconductor layer, and forming an opening in a part of the first single crystal semiconductor layer A step of exposing a part of the porous semiconductor layer, a step of etching the porous semiconductor layer from the opening, and forming a void in at least the semiconductor substrate serving as an element formation region, A second single crystal semiconductor layer is formed on an upper surface of the first single crystal semiconductor layer and an upper surface of the semiconductor substrate immediately below the opening, and the opening formed in the first single crystal semiconductor layer is formed. in front A step of closing the second single crystal semiconductor layer, wherein the second single crystal semiconductor layer directly cavity, is characterized in that it comprises a step of forming a semiconductor device formation, the.
[0010]
A third manufacturing method of a semiconductor device according to the present invention includes a step of forming a porous semiconductor layer in a semiconductor substrate at least in an element formation region and an element isolation region, and heat-treating the semiconductor substrate, and at least the porous A step of crystallizing the vicinity of the surface of the semiconductor layer, a step of forming a first single crystal semiconductor layer on the entire surface of the semiconductor substrate including the porous semiconductor layer, and a part of the first single crystal semiconductor layer Forming an opening to expose a part of the porous semiconductor layer; and etching the porous semiconductor layer from the opening to form a void in the semiconductor substrate at least as an element formation region Forming a second single crystal semiconductor layer on the upper surface of the first single crystal semiconductor layer and the upper surface of the semiconductor substrate immediately below the opening, and forming the first single crystal semiconductor layer on the first single crystal semiconductor layer; A step of closing the opening with the second single crystal semiconductor layer, a step of forming a semiconductor element in the second single crystal semiconductor layer immediately above the hole, and the porous semiconductor in the element isolation region The method includes a step of removing a layer and forming a recess in the semiconductor substrate to be an element isolation region, and a step of filling an insulator in the recess.
[0011]
Here, in the first to third manufacturing methods of the semiconductor device according to the present invention, the porous semiconductor layer is preferably formed using an anodizing method.
In the first to third manufacturing methods of the semiconductor device according to the present invention, the porous semiconductor layer includes a highly porous semiconductor layer formed in a deep part in the semiconductor substrate, and the highly porous semiconductor layer. It is preferable to comprise a low porous semiconductor layer formed on the upper surface.
[0012]
Furthermore, in the first to third manufacturing methods of the semiconductor device according to the present invention, an oxide film is formed at least on the surface of the first single crystal semiconductor layer and the semiconductor substrate constituting the inner surface of the hole portion. It is preferable to provide a process.
A first manufacturing method of a semiconductor substrate according to the present invention is a manufacturing method of a semiconductor substrate in which a hole portion is formed in an element forming region, and a porous semiconductor layer is formed at least in the semiconductor substrate in the element forming region. Performing a heat treatment on the semiconductor substrate to crystallize at least the vicinity of the surface of the porous semiconductor layer, and forming a first single crystal semiconductor layer on the entire surface of the semiconductor substrate including the porous semiconductor layer. Forming an opening in a part of the first single crystal semiconductor layer, exposing a part of the porous semiconductor layer, etching the porous semiconductor layer from the opening, and at least The method includes a step of forming a hole in the semiconductor substrate to be an element formation region, and a step of closing the opening.
[0013]
A second manufacturing method of a semiconductor substrate according to the present invention is a manufacturing method of a semiconductor substrate in which a hole portion is formed in an element forming region, and a porous semiconductor layer is formed at least in the semiconductor substrate in the element forming region. Performing a heat treatment on the semiconductor substrate to crystallize at least the vicinity of the surface of the porous semiconductor layer, and forming a first single crystal semiconductor layer on the entire surface of the semiconductor substrate including the porous semiconductor layer. Forming an opening in a part of the first single crystal semiconductor layer, exposing a part of the porous semiconductor layer, etching the porous semiconductor layer from the opening, and at least Forming a hole in the semiconductor substrate to be an element forming region; and a second single crystal semiconductor layer on the upper surface of the first single crystal semiconductor layer and the upper surface of the semiconductor substrate immediately below the opening. Form Together, it is characterized in that and a step of closing the said opening formed in the first single crystal semiconductor layer with the second single crystal semiconductor layer.
[0014]
A third method for manufacturing a semiconductor substrate according to the present invention is a method for manufacturing a semiconductor substrate in which a hole portion is formed in an element formation region, and a porous semiconductor layer is formed at least in the semiconductor substrate in the element isolation region. Performing a heat treatment on the semiconductor substrate to crystallize at least the vicinity of the surface of the porous semiconductor layer, and forming a first single crystal semiconductor layer on the entire surface of the semiconductor substrate including the porous semiconductor layer. Forming an opening in a part of the first single crystal semiconductor layer, exposing a part of the porous semiconductor layer, etching the porous semiconductor layer from the opening, and at least Forming a hole in the semiconductor substrate to be an element forming region, and forming a second single crystal semiconductor layer on the upper surface of the first single crystal semiconductor layer and the upper surface of the semiconductor substrate immediately below the opening; Do Both the step of closing the opening formed in the first single crystal semiconductor layer with the second single crystal semiconductor layer, and removing the porous semiconductor layer in the element isolation region to form an element isolation region A step of forming a recess in the semiconductor substrate and a step of filling the recess with an insulator are provided.
[0015]
Here, in the first to third manufacturing methods of the semiconductor substrate according to the present invention, the porous semiconductor layer is preferably formed using an anodizing method.
In the first to third methods of manufacturing a semiconductor substrate according to the present invention, the porous semiconductor layer includes a highly porous semiconductor layer formed in a deep portion in the semiconductor substrate, and the highly porous semiconductor layer. It is preferable to comprise a low porous semiconductor layer formed on the upper surface.
[0016]
Further, in the first to third manufacturing methods of the semiconductor substrate according to the present invention, an oxide film is formed on at least the first single crystal semiconductor layer constituting the inner surface of the hole and the surface of the semiconductor substrate. It is preferable to provide a process.
In the first method of manufacturing a semiconductor device according to the present invention, the “step of forming a semiconductor element in the first single crystal semiconductor layer immediately above the hole portion” is a step before the “step of closing the opening”. You may go to or later.
[0017]
Further, in the third method for manufacturing a semiconductor device according to the present invention, the “step of forming a recess in a semiconductor substrate serving as an element isolation region” and the “step of filling an insulator in the recess” It may be performed before or after the “step of forming a semiconductor element in the second single crystal semiconductor layer immediately above the hole”.
Thus, according to the first method for manufacturing a semiconductor device of the present invention, a single crystal semiconductor layer is stacked on a semiconductor substrate having a porous semiconductor layer formed at least in an element formation region, and the single crystal semiconductor layer By removing the porous semiconductor layer by etching from the opening where a part of the porous semiconductor layer formed on the substrate is exposed, a void portion is formed in the semiconductor substrate which is an element formation region. The film thickness of the crystalline semiconductor layer can be easily and reliably controlled. For this reason, since it is easy to reduce the thickness of the single crystal semiconductor layer, it is possible to realize further higher performance and lower power consumption of the semiconductor device.
[0018]
In addition, by forming holes in the semiconductor substrate that will be the element formation region by etching, only those parts that require the formation of the SON structure are selected from the semiconductor elements formed on the semiconductor substrate. Thus, it becomes possible to form a hole portion. For this reason, it becomes possible to improve the freedom degree of element design on a semiconductor substrate.
[0019]
According to the second method for manufacturing a semiconductor device according to the present invention, a semiconductor element is formed on the second single crystal semiconductor layer formed on the first single crystal semiconductor layer, thereby providing a more precise structure. Since the semiconductor element is formed over the single crystal semiconductor layer having a crystal structure, it is possible to realize further higher performance of the semiconductor device.
According to the third manufacturing method of the semiconductor device of the present invention, the element forming region and the element isolation region are formed by etching the porous semiconductor layer formed in the semiconductor substrate. It is possible to greatly reduce the number of processes and costs involved in the manufacture of the above.
[0020]
According to the first to third methods for manufacturing a semiconductor substrate according to the present invention, the semiconductor device according to the present invention can be easily realized.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this embodiment shows an example of this invention and this invention is not limited to this embodiment.
<First embodiment>
FIG. 1 is a cross-sectional view showing a configuration example of the semiconductor device according to the first embodiment of the present invention.
[0022]
As shown in FIG. 1, the semiconductor device 100 </ b> A according to the present embodiment is formed of a Si film having a two-layer structure on the upper surface of a hole portion H formed in a silicon substrate (semiconductor substrate) 1 to be an element formation region S. It has a SON structure in which an epitaxial growth layer (single crystal semiconductor layer) 2 is formed. Further, the side surface and the upper surface of the void portion H are formed of the epitaxial growth layer 2 and the lower surface thereof is formed of a silicon substrate. A silicon oxide film (oxide film) is formed on the upper surface and the lower surface of the void portion H. ) 3 is formed.
[0023]
The semiconductor device 100A is formed on the upper surface of the epitaxial growth layer 2 to be the element formation region S via the gate oxide film 4 and on the epitaxial growth layers 2 on both sides of the gate electrode 5 A MOS transistor comprising a sidewall 6 and a source / drain region 7 formed through an LDD region 7 a is provided in the epitaxial growth layer 2 on both sides of the gate electrode 5.
[0024]
Next, one manufacturing process of the semiconductor device 100A in the present embodiment will be described with reference to FIG.
FIG. 2 is a cross-sectional view showing one manufacturing process of the semiconductor device shown in FIG. FIG. 3 is a plan view showing one manufacturing process of the semiconductor device shown in FIG.
First, as shown in FIG. 2A, the anode is formed in a state where a pattern R made of SiC or SiN is formed on the upper surface of the silicon substrate 1 so that the element formation region S and the region X surrounding the element formation region S are exposed. An anodizing (anodic oxidation) method is performed by using the silicon substrate 1 and a mixture of hydrogen fluoride and ethyl alcohol as the ionic conductor (electrolytic solution). Then, the porous silicon layer 1A is formed in the silicon substrate 1 in the element forming region S and the region X surrounding the region (porous semiconductor layer forming step).
[0025]
Here, in the next step, in order to grow a dense epitaxial growth layer 2 on the upper surface of the porous silicon layer 1 </ b> A, the porous silicon layer 1 </ b> A formed in the silicon substrate 1 is highly porous in the deep part of the silicon substrate 1. It is preferable to form the silicon layer 1a and form the low porous silicon layer 1b in the upper layer portion of the silicon substrate 1. The porosity of the porous silicon layer 1A can be changed by adjusting the anodizing current density and anodizing time for anodizing.
[0026]
Next, the silicon substrate 1 on which the porous silicon layer 1A is formed is subjected to heat treatment in a reducing atmosphere at 900 to 1100 ° C. to recrystallize the surface of the porous silicon layer 1A.
Next, as shown in FIG. 2B, the upper surface of the silicon substrate 1 after the porous silicon layer 1A is formed is made of a Si film having the same crystal orientation as that of the silicon substrate 1 by a known epitaxial growth technique. First epitaxial growth layer (single crystal semiconductor layer) 2A is formed (single crystal semiconductor layer forming step).
[0027]
Next, in the first epitaxial growth layer 2A formed on the porous silicon layer 1A, a resist (not shown) pattern is formed so that a part of the region X surrounding the element forming region S is exposed. Then, anisotropic etching is performed. Then, as shown in FIG. 2C, in the first epitaxial growth layer 2A formed on the porous silicon layer 1A, an opening 2a is formed in a part of the region X surrounding the element formation region S. (Etching opening forming step).
[0028]
Here, if the opening 2a formed in the first epitaxial growth layer 2A has a dimension that can remove at least the porous silicon layer 1A formed immediately below the first epitaxial growth layer 2A by etching, The opening dimension is not particularly limited. For example, a plurality of discontinuous openings 2a may be formed in the region X surrounding the element forming region S as in the semiconductor device of the present embodiment shown in FIG.
[0029]
Next, isotropic wet etching is performed on the silicon substrate 1 from the opening 2a formed in the first epitaxial growth layer 2A, and the porous material formed in the silicon substrate 1 as shown in FIG. The silicon layer 1A is selectively removed, and a hole portion H is formed in the silicon substrate 1 in the element formation region S and the region X surrounding the element formation region S (hole portion forming step).
[0030]
Next, as shown in FIG. 2 (e), the silicon substrate 1 in which the hole portion H is formed is subjected to heat treatment by a thermal oxidation method, so that the upper surface of the first epitaxial growth layer 2A and the inner surface of the hole portion H are formed. An oxide film 3 is formed (oxide film forming step).
Next, anisotropic dry etching is performed on the oxide film 3 formed on the upper surface of the silicon substrate 1, and the upper surface of the first epitaxial growth layer 2A and the void portion H immediately below the opening 2a of the first epitaxial growth layer 2A are processed. Of the oxide film 3 formed on the inner surface, 50 to 90% of the initial film thickness is removed. Subsequently, isotropic wet etching is performed on the oxide film 3 remaining in the anisotropic dry etching in the previous step, so that the upper surface of the first epitaxial growth layer 2A and the space immediately below the opening 2a of the first epitaxial growth layer 2A are formed. The remaining film of the oxide film 3 formed on the inner surface of the hole H is removed. Here, as shown in FIG. 2 (f), the oxide film 3 is formed only on the first epitaxial growth layer 2 and the silicon substrate 1 immediately below the element formation region S in the hole H formed in the silicon substrate 1. Remain.
[0031]
Next, as shown in FIG. 2G, a second epitaxial growth layer 2B made of a Si film is formed on the entire upper surface of the silicon substrate 1 by a known epitaxial growth technique. At the same time as the opening 2a of the epitaxial growth layer 2A, the holes formed immediately below the opening 2a are filled. Here, the hole H is formed in a vacuum state between the silicon substrate 1 in the element formation region S and the first epitaxial growth layer 2A (opening filling step).
[0032]
Next, after forming the gate oxide film 4 on the upper surface of the second epitaxial growth layer 2B by a thermal oxidation method, a polycrystalline silicon film (not shown) is formed by a known CVD method. Then, etching is performed on the polycrystalline silicon film in a state where a resist pattern (not shown) is formed so as to cover a portion where the gate electrode is to be formed and is exposed, and an element on the second epitaxial growth layer 2B is formed. In the formation region S, the gate electrode 5 is formed.
[0033]
Next, after the gate electrode 5 is formed, a resist pattern (not shown) is formed so as to cover other than the element formation region S, and the LDD region is formed in a state where the gate electrode 5 is used as a mask for ion implantation. Ions are implanted into the second epitaxial growth layer 2B. Thereafter, a sidewall formation film (not shown) made of silicon oxide is formed on the entire upper surface of the second epitaxial growth layer 2B using a known CVD method, and then etched back, so that both sides of the gate electrode 5 are formed. Sidewall 6 is formed.
[0034]
Next, a resist pattern (not shown) is formed on the second epitaxial growth layer 2B so as to cover other than the element formation region S, and the gate electrode 5 and the sidewall 6 are used as a mask for ion implantation. Source / drain region forming ions are implanted into the second epitaxial growth layer 2B.
In this manner, as shown in FIG. 1, a MOS transistor is completed on the silicon substrate 1 having the SON structure.
[0035]
According to the semiconductor device 100A having such a structure, the silicon substrate in which the porous silicon layer 1A is formed in the element forming region S and the region X surrounding the hole portion H (insulator portion) of the SON structure. The epitaxial growth layer 2 is laminated on the substrate 1, and the epitaxial growth layer 2 is formed by removing the porous silicon layer 1A by etching from the opening 2a formed in a part of the region X surrounding the element forming region S. By doing so, the film thickness of the epitaxial growth layer 2 can be controlled easily and reliably. For this reason, by reducing the thickness of this epitaxial growth layer, it is possible to achieve further higher performance and lower power consumption of the MOS transistor.
[0036]
Further, by forming the hole H formed in the silicon substrate 1 in the element formation region S by etching, it is selectively formed only on the semiconductor element on which the SON structure is to be formed on the silicon substrate 1. Will be able to. For this reason, it becomes possible to greatly improve the element design freedom in the silicon substrate 1.
[0037]
Furthermore, by forming the hole H formed in the element formation region S in the silicon substrate 1 by etching the porous silicon layer 1A formed in the silicon substrate 1, Since the etching selectivity with respect to the porous silicon layer 1A is large, it is possible to easily and surely form the hole H with stable etching characteristics.
[0038]
Further, in the porous silicon layer 1A, a low porous silicon layer 1b close to a crystalline state is formed on the surface, and the surface layer is subjected to heat treatment and recrystallized to form an epitaxial growth formed on the upper surface thereof. It becomes possible to form the layer 2 more densely.
<Modification of First Embodiment>
In this modification, in the semiconductor device 100A of the first embodiment, the epitaxial growth layer 2 is formed of only the first epitaxial growth layer 2A, and the opening 2a of the first epitaxial growth layer 2A and the vacant space immediately below the opening 2a are formed. The hole is filled with the silicon oxide film 3.
[0039]
Next, a method for manufacturing the semiconductor device 100B according to this modification will be described with reference to FIG.
FIG. 4 is a cross-sectional view showing one manufacturing process of the semiconductor device according to the modification of the first embodiment of the present invention.
First, as shown in FIGS. 2A to 2D, a hole portion H is formed in the element formation region S of the silicon substrate 1 and the region X surrounding the periphery in the same process as in the first embodiment described above. To do.
[0040]
Next, as shown in FIG. 4A, in the oxide film forming step shown in the first embodiment, the silicon oxide film 3 formed by thermal oxidation is formed into the depth of the hole H formed in the silicon substrate 1. It is formed to be thicker than the dimension. Here, the opening 2a of the first epitaxial growth layer 2A and the hole formed immediately below the opening 2a are filled with the silicon oxide film 3, and the silicon substrate immediately below the element formation region S and the region X surrounding the element formation region S. A hole H is formed in 1.
[0041]
Next, anisotropic etching is performed on the silicon oxide film 3 formed on the upper surface of the first epitaxial growth layer 2A so that the upper surface of the first epitaxial growth layer 2 is exposed.
Then, a MOS transistor is formed in the first epitaxial growth layer 2A, which is the element formation region S formed immediately above the hole portion H in the silicon substrate 1, through the same process as in the first embodiment described above. A semiconductor device 100B as shown in FIG. 4B is completed.
[0042]
According to the semiconductor device 100B configured in this way, as shown in the first embodiment, the step of selectively etching the oxide film 3 after the oxide film formation step and the opening filling step are not necessary. The manufacturing process of the semiconductor device 100B can be further simplified.
<Second embodiment>
FIG. 5 is a sectional view showing one manufacturing process of the semiconductor device according to the second embodiment of the present invention. 5 that are the same as those in FIG. 1 are denoted by the same reference numerals.
[0043]
The semiconductor device 100C in the present embodiment is the same as the semiconductor device 100A shown in the first embodiment, in which the opening 2a of the first epitaxial growth layer 2A and the vacancies formed immediately below the opening 2a are filled with the interlayer insulating layer 8. It is a thing.
Next, a method for manufacturing the semiconductor device 100C in the present embodiment will be described.
First, as shown in FIGS. 2A to 2E, a silicon substrate in which a hole portion H is formed in an element forming region S and a region X surrounding the element forming region S in the same process as in the first embodiment described above. The oxide film 3 is formed on the upper surface of the first epitaxial growth layer 2 </ b> A and the inner surface of the hole portion H by performing heat treatment on 1.
[0044]
Next, the silicon oxide layer 3 formed on the first epitaxial growth layer 2A is removed by anisotropic dry etching.
Next, as shown in FIG. 5A, a MOS type transistor is formed on the first epitaxial growth layer 2A immediately above the hole H formed in the silicon substrate 1 through the same process as in the first embodiment. Form.
[0045]
Next, as shown in FIG. 5B, an interlayer made of, for example, silicon oxide is formed on the entire upper surface of the first epitaxial growth layer 2 </ b> A having the MOS transistor formed on the upper surface by using a CVD (Chemical Vapor Deposition) method. By forming the insulating layer 8, the opening 2a of the first epitaxial growth layer 2A and the hole formed immediately below the opening 2a are filled to complete the semiconductor device 100C.
[0046]
According to the semiconductor device 100C configured as described above, after the semiconductor element is formed on the upper surface of the first epitaxial growth layer 2A to be the element formation region S, the opening 2a of the first epitaxial growth layer 2A and the opening 2a immediately below the opening 2a. By filling the formed holes, it is possible to obtain the same effect as in the first embodiment.
[0047]
In addition, according to the method for manufacturing the semiconductor device 100C, the opening 2a of the first epitaxial growth layer 2A and the hole formed immediately below the opening 2a are formed by the interlayer insulating layer 8 required in the next process. By making it block, the manufacturing process of the semiconductor device 100C can be further simplified.
<Third embodiment>
FIG. 6 is a cross-sectional view showing a configuration example of the semiconductor device according to the third embodiment of the present invention.
[0048]
As shown in FIG. 6, the semiconductor device 100 </ b> D in the present embodiment is similar to the semiconductor device 100 </ b> C shown in the second embodiment in the element formation region S in which the hole H is formed in the silicon substrate 1 and the recess h. And the element isolation region B filled with the interlayer insulating layer 8 are formed together.
Next, a method for manufacturing the semiconductor device 100D in the present embodiment will be described.
[0049]
FIG. 7 is a cross-sectional view showing one manufacturing process of the semiconductor device according to the second embodiment of the present invention.
First, as shown in FIG. 7A, a pattern R made of SiC or SiN is exposed on the upper surface of the silicon substrate 1 so that the element formation region S and the region X surrounding the element formation region S and the element isolation region B are exposed. In the formed state, an anodizing (anodic oxidation) method is performed as in the first embodiment. In the silicon substrate 1 in the element formation region S, the region X surrounding the element formation region S, and the element isolation region B, a porous layer composed of a high porous silicon layer 1a and a low porous silicon layer 1b is formed as in the first embodiment. A porous silicon layer 1A is formed (porous semiconductor layer forming step).
[0050]
Next, the silicon substrate 1 on which the porous silicon layer 1A is formed is subjected to heat treatment in a reducing atmosphere at 900 to 1100 ° C. to recrystallize the surface of the porous silicon layer 1A.
Next, as shown in FIG. 7B, a first epitaxial growth having the same crystal orientation as that of the silicon substrate 1 is formed on the upper surface of the silicon substrate 1 after the porous silicon layer 1A is formed by a known epitaxial growth technique. A layer (single crystal silicon layer) 2A is formed (step of forming a single crystal semiconductor layer).
[0051]
Next, in the first epitaxial growth layer 2A formed on the porous silicon layer 1A, a part of the region X surrounding the element formation region S is exposed, and the other is covered with a resist pattern (not shown). ) Is formed, anisotropic dry etching is performed. Then, as shown in FIG. 7C, in the first epitaxial growth layer 2A formed on the porous silicon layer 1A, an opening 2a is formed in a part of the region X surrounding the element formation region S. (Etching opening forming step).
[0052]
Next, isotropic wet etching is performed on the silicon substrate 1 from the opening 2a formed in the first epitaxial growth layer 2A, and the porous silicon layer formed in the silicon substrate 1 as shown in FIG. 1A is selectively removed, and a hole portion H is formed in the silicon substrate 1 in the element forming region S and the region X surrounding the element forming region S (hole portion forming step).
[0053]
Next, as shown in FIG. 7E, the upper surface of the first epitaxial growth layer 2A and the hole H are formed by subjecting the silicon substrate 1 on which the holes H are formed to a heat treatment by a thermal oxidation method. An oxide film 3 is formed on the inner surface (oxide film forming step).
Next, anisotropic dry etching is performed on the oxide film 3 formed on the upper surface of the silicon substrate 1, and among the oxide films 8 formed on the upper surface of the first epitaxial growth layer 2A, an initial film thickness of 50 to 90% is removed. Subsequently, isotropic wet etching is performed on the oxide film 3 remaining in the anisotropic dry etching in the previous step, and the remaining film of the oxide film 3 formed on the upper surface of the first epitaxial growth layer 2A is removed. .
[0054]
Next, as shown in FIG. 7F, a MOS transistor is formed on the first epitaxial growth layer 2A immediately above the hole H formed in the silicon substrate 1 through the same process as in the first embodiment. Form.
Next, anisotropic dry etching is performed in a state where a resist pattern R that exposes the element isolation region B is formed on the upper surface of the silicon substrate 1 on which the MOS transistor is formed, as shown in FIG. As described above, the recess h is formed in the silicon substrate 1 to be the element isolation region B (element isolation region forming step).
[0055]
Next, the interlayer insulating layer 8 is formed on the entire upper surface of the first epitaxial growth layer 2A having the MOS transistor formed on the upper surface using a known CVD method, so that the recess h formed in the element isolation region B is formed. Interlayer insulating layer 8 is filled to complete semiconductor device 100D as shown in FIG.
According to the semiconductor device 100D configured as described above, the element formation region S in which the hole portion H is formed in the silicon substrate 1 and the element isolation region B in which the interlayer insulating layer 8 is filled are divided into the silicon substrate. In the first embodiment, the porous silicon layer 1 </ b> A formed in 1 is required to be formed separately from the step of forming the hole portion H in the element forming region S. Since the element isolation step is not necessary, the semiconductor device 100D can be formed more simply.
<Modification of Third Embodiment>
In the semiconductor device according to this modification, in the method for manufacturing the semiconductor device 100D shown in the third embodiment, first, after forming the element isolation region B in the silicon substrate 1, the hole portion H is formed in the element formation region S. It is what you do.
[0056]
Next, one manufacturing process of the semiconductor device in this modification will be described.
FIG. 8 is a cross-sectional view showing a manufacturing process of a modification of the third embodiment of the present invention.
First, as shown in FIG. 7A, a porous silicon layer is formed in the element formation region S and the region X surrounding the element formation region S and the element isolation region B in the silicon substrate 1 in the same process as in the third embodiment. 1A is formed (polycrystalline semiconductor layer forming step).
[0057]
Next, as shown in FIG. 8A, anisotropic dry etching is performed in a state where a resist pattern R is formed on the upper surface of the silicon substrate 1 so that the element isolation region B is exposed, and the element isolation region B is formed. A recess h is formed in the silicon substrate 1 to be (element isolation region forming step).
Next, as shown in FIG. 8B, an insulating layer 9 is formed on the entire upper surface of the silicon substrate 1 by using known CVD, so that, for example, silicon oxide is formed in the recess h formed in the element isolation region B. An insulating layer 9 made of or the like is filled.
[0058]
Next, as shown in FIG. 8C, the insulating layer 9 formed on the entire upper surface of the silicon substrate 1 is etched back until the porous silicon layer 1A is exposed.
Next, as shown in FIGS. 2B to 2G, through the same process as in the first embodiment, the second epitaxial growth layer 2B causes the opening 2a of the first epitaxial growth layer 2A and the opening 2a thereof. The element forming region S in which the hole portion formed immediately below is filled and the hole portion H is formed in the silicon substrate 1 is formed. Here, a semiconductor device including the element formation region S in which the hole H is formed and the element isolation region B in which the insulating layer 9 is filled is completed.
[0059]
According to the semiconductor device configured as described above, the hole H formed in the element formation region S and the recess h formed in the element isolation region B are simultaneously formed in the silicon substrate 1. As a result, the same effects as those of the third embodiment can be obtained.
In the modification of the first embodiment, the second embodiment, and the third embodiment, the case where the epitaxial growth layer 2 has a single layer structure has been described. However, the semiconductor device formed in the epitaxial growth layer 2 has higher performance. In order to realize the above, it is desirable that the epitaxial growth layer 2 has a two-layer structure as shown in the modification of the first embodiment or the third embodiment.
[0060]
In the first to third embodiments, the Si film is epitaxially grown as the epitaxial growth layer 2. However, the present invention is not limited to this as long as a semiconductor element can be formed. For example, the Si-Ge film is formed by epitaxial growth. It doesn't matter.
Further, in the first to third embodiments, the porous silicon layer 1A is formed in the silicon substrate 1 in the element forming region S and the region X surrounding the element forming region S, and the epitaxial growth layer formed on the porous silicon layer 1A. Although the opening 2a is formed in the region X surrounding the periphery of the element formation region S in FIG. 2, it is not limited to this as long as the hole portion H can be formed in the silicon substrate 1 serving as the element formation region S. Absent. For example, the porous silicon layer 1A is formed in the silicon substrate 1 in the element formation region S, and the opening 2a is formed in a part of the element formation region S in the epitaxial growth layer 2 formed on the porous silicon layer 1A. It is also possible to form a MOS transistor in the epitaxial growth layer 2 where the opening 2a is not formed. However, in order to ensure device performance and element design flexibility formed in the element formation region S, it is preferable to perform the manufacturing method as shown in the first to third embodiments.
[0061]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device according to the present invention, at least the porous semiconductor layer formed in the semiconductor substrate serving as the element forming region is removed, so that the semiconductor substrate serving as the element forming region is emptied. By forming the hole portion, the thickness of the single crystal semiconductor layer can be easily and reliably controlled. For this reason, since it is easy to reduce the thickness of the single crystal semiconductor layer, it is possible to realize further higher performance and lower power consumption of the semiconductor device.
[0062]
In addition, by forming a hole portion to be formed in the semiconductor substrate to be an element formation region by etching, the SON structure is selectively formed only in a necessary portion of the semiconductor elements formed on the semiconductor substrate. Can be formed. For this reason, it becomes possible to improve the freedom degree of element design on a semiconductor substrate.
Furthermore, the element formation region and the element isolation region are formed by etching the porous semiconductor layer formed in the semiconductor substrate, thereby greatly reducing the number of steps and costs involved in manufacturing the semiconductor device. Is possible.
[0063]
Furthermore, the semiconductor element is formed on the single crystal semiconductor layer having a denser crystal structure by forming the semiconductor element on the second single crystal semiconductor layer formed on the first single crystal semiconductor layer. Therefore, it is possible to realize further higher performance of the semiconductor device.
In addition, according to the method for manufacturing a semiconductor substrate according to the present invention, it is possible to realize higher performance and lower power consumption of the semiconductor device and to improve the element design flexibility on the semiconductor substrate.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 1;
FIG. 3 is a plan view showing one manufacturing process of the semiconductor device shown in FIG. 2 (c);
FIG. 4 is a cross-sectional view showing one manufacturing process of a semiconductor device according to a modification of the first embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the invention.
FIG. 6 is a cross-sectional view showing a configuration example of a semiconductor device according to a third embodiment of the present invention.
7 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 6; FIG.
FIG. 8 is a cross-sectional view showing one manufacturing process of a semiconductor device according to a modification of the third embodiment of the present invention.
FIG. 9 is a cross-sectional view showing one manufacturing process of a conventional semiconductor device.
[Explanation of symbols]
1, 10, silicon substrate (semiconductor substrate). 1A, 10A, porous silicon layer (porous semiconductor layer). 2. Epitaxial growth layer (single crystal semiconductor layer). Silicon oxide film (oxide film). 4. Gate oxide film. 5, gate electrode. 6. Side wall. 7. Source / drain regions. 8. Interlayer insulation layer. 9. Insulating layer. B, element isolation region. S, element formation region. X, a region surrounding the periphery of the element formation region. h, recess. H, hole part. 100A to 100D Semiconductor device.

Claims (11)

Forming a porous semiconductor layer in the semiconductor substrate in the element formation region;
Applying a heat treatment to the semiconductor substrate to crystallize at least the surface of the porous semiconductor layer; and
Forming a first single crystal semiconductor layer on the entire surface of the semiconductor substrate including the porous semiconductor layer;
Forming an opening in a part of the first single crystal semiconductor layer and exposing a part of the porous semiconductor layer;
Etching the porous semiconductor layer from the opening to form a void in the semiconductor substrate that is at least an element formation region;
A second single crystal semiconductor layer is formed on an upper surface of the first single crystal semiconductor layer and an upper surface of the semiconductor substrate immediately below the opening, and the opening formed in the first single crystal semiconductor layer Clogging with the second single crystal semiconductor layer,
Forming a semiconductor element on the second single crystal semiconductor layer immediately above the hole portion;
A method for manufacturing a semiconductor device, comprising: Forming a porous semiconductor layer in the semiconductor substrate at least in the element formation region and the element isolation region;
Applying a heat treatment to the semiconductor substrate to crystallize at least the surface of the porous semiconductor layer; and
Forming a first single crystal semiconductor layer on the entire surface of the semiconductor substrate including the porous semiconductor layer;
Forming an opening in a part of the first single crystal semiconductor layer and exposing a part of the porous semiconductor layer;
Etching the porous semiconductor layer from the opening to form a void in the semiconductor substrate that is at least an element formation region;
Forming a second single crystal semiconductor layer on an upper surface of the first single crystal semiconductor layer and an upper surface of the semiconductor substrate immediately below the opening; and forming the opening formed in the first single crystal semiconductor layer. Clogging with the second single crystal semiconductor layer;
Forming a semiconductor element on the second single crystal semiconductor layer immediately above the hole portion;
Removing the porous semiconductor layer in the element isolation region and forming a recess in the semiconductor substrate to be the element isolation region;
Filling the recess with an insulator;
A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 1, wherein the porous semiconductor layer is formed by using an anodizing method. The porous semiconductor layer is composed of a highly porous semiconductor layer formed in a deep portion in the semiconductor substrate, and a low porous semiconductor layer formed on an upper surface of the highly porous semiconductor layer, A method for manufacturing a semiconductor device according to any one of claims 1 to 3. 5. The method according to claim 1, further comprising a step of forming an oxide film on a surface of at least the first single crystal semiconductor layer constituting the inner surface of the hole and the semiconductor substrate. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. A method of manufacturing a semiconductor substrate in which a hole is formed in an element formation region,
Forming a porous semiconductor layer in a semiconductor substrate at least in the element formation region;
Applying a heat treatment to the semiconductor substrate to crystallize at least the surface of the porous semiconductor layer; and
Forming a first single crystal semiconductor layer on the entire surface of the semiconductor substrate including the porous semiconductor layer;
Forming an opening in a part of the first single crystal semiconductor layer and exposing a part of the porous semiconductor layer ;
Etching the porous semiconductor layer from the opening to form a void in the semiconductor substrate that is at least an element formation region;
Forming a second single crystal semiconductor layer on an upper surface of the first single crystal semiconductor layer and an upper surface of the semiconductor substrate immediately below the opening; and forming the opening formed in the first single crystal semiconductor layer. Clogging with the second single crystal semiconductor layer;
Method of manufacturing a semi-conductor substrate you comprising the. A method of manufacturing a semiconductor substrate in which a hole is formed in an element formation region,
Forming a porous semiconductor layer in the semiconductor substrate at least in the element isolation region;
Applying a heat treatment to the semiconductor substrate to crystallize at least the surface of the porous semiconductor layer; and
Forming a first single crystal semiconductor layer on the entire surface of the semiconductor substrate including the porous semiconductor layer;
Forming an opening in a part of the first single crystal semiconductor layer and exposing a part of the porous semiconductor layer;
Etching the porous semiconductor layer from the opening to form a void in the semiconductor substrate that is at least an element formation region;
Forming a second single crystal semiconductor layer on an upper surface of the first single crystal semiconductor layer and an upper surface of the semiconductor substrate immediately below the opening; and forming the opening formed in the first single crystal semiconductor layer. Clogging with the second single crystal semiconductor layer ;
Removing the porous semiconductor layer in the element isolation region and forming a recess in the semiconductor substrate to be the element isolation region;
Filling the recess with an insulator;
A method for manufacturing a semiconductor substrate, comprising: The method of manufacturing a semiconductor substrate according to claim 6, wherein the porous semiconductor layer is formed using an anodizing method. The porous semiconductor layer is composed of a highly porous semiconductor layer formed in a deep part in the semiconductor substrate, and a low porous semiconductor layer formed on the upper surface of the highly porous semiconductor layer, The manufacturing method of the semiconductor substrate as described in any one of Claim 6 thru | or 8 . 10. The method according to claim 6, further comprising a step of forming an oxide film on the surface of at least the first single crystal semiconductor layer constituting the inner surface of the hole and the semiconductor substrate. The manufacturing method of the semiconductor substrate as described in any one of. Forming a porous semiconductor layer in the recess of the semiconductor substrate having the recess;
Crystallization of the surface of the porous semiconductor layer;
Forming a first single crystal semiconductor layer on the semiconductor substrate and the porous semiconductor layer;
Forming an opening exposing a portion of the porous semiconductor layer;
Etching the porous semiconductor layer from the opening to form a void in the recess; and
Forming a second single crystal semiconductor layer on the first single crystal semiconductor layer and in a region surrounding the periphery of the void portion of the recess;
Wherein said second single crystal semiconductor layer on the cavity, a method of manufacturing a semiconductor device characterized by comprising a step of forming a semiconductor element.

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