JP4276231B2 - Varistor element - Google Patents

Description

  The present invention relates to a varistor element.

As this type of varistor element, a varistor element having a varistor layer that exhibits voltage nonlinear characteristics and a pair of internal electrodes arranged so as to sandwich the varistor layer, and positioned at both ends of the varistor element, respectively. In addition, a device including a pair of terminal electrodes each connected to a corresponding internal electrode among a plurality of internal electrodes is known (see, for example, Patent Document 1).
JP 2002-246207 A

  In recent years, with the miniaturization of electronic devices such as DSC (Digital Still Camera), DVC (Digital Video Camera), PDA (Personal Digital Assistant), notebook personal computer or mobile phone, etc., for high-density mounting of electronic devices such as varistor devices. The demand is getting stricter. In order to satisfy this requirement for high-density mounting, it is considered that the electronic element package is a ball grid array package (hereinafter simply referred to as a BGA package). The BGA package has a large number of solder bumps arranged in parallel on the back surface thereof. The BGA package is mounted on the mounting substrate by reflowing each solder bump in a state of being superimposed on the corresponding pad of the mounting substrate.

  By the way, when the varistor element is configured to correspond to the BGA package, the solder bumps and terminal electrodes are located on the back side facing the mounting substrate, so that it is difficult to identify the mounting direction of the varistor element. If the varistor element is mounted in the wrong mounting direction, it will not function normally.

  It is an object of the present invention to provide a varistor element that can be mounted appropriately and easily even when configured to correspond to a BGA package.

  The varistor element according to the present invention includes a varistor element body having first and second main surfaces facing each other, and first and second varistor elements disposed in the varistor element body so that at least some of the varistor elements face each other. A plurality of internal electrode pairs having internal electrodes and a connection conductor formed on the first main surface so as to electrically connect the first internal electrodes of a predetermined internal electrode pair among the plurality of internal electrode pairs And a plurality of terminal electrodes provided corresponding to each second internal electrode of the plurality of internal electrode pairs and formed on the second main surface so as to be electrically connected to the second internal electrode; .

  In the varistor element according to the present invention, the plurality of terminal electrodes are formed on the second main surface, so that the second main surface faces the mounting component (for example, an electronic component or a mounting substrate). A varistor element can be mounted, and a configuration corresponding to the BGA package is realized. Since the connection conductor is formed on the first main surface so as to electrically connect the first internal electrodes of the predetermined internal electrode pair among the plurality of internal electrode pairs, the connection conductor is formed at a position corresponding to the connection conductor. There will be a region that functions as a varistor. Therefore, the connection conductor functions as a mark for identifying the mounting direction of the varistor element, and the varistor element can be mounted appropriately and easily. Furthermore, according to the present invention, it is not necessary to newly provide a mark for identifying the mounting direction of the varistor element, and the manufacturing cost of the varistor element does not increase.

  Preferably, the varistor element body has a square shape when viewed from a direction perpendicular to the first and second main surfaces. In this case, since it is difficult to identify the mounting direction of the varistor element based on the shape of the varistor element body, it is particularly effective.

  Preferably, the plurality of terminal electrodes are two-dimensionally arranged in n rows and n columns (n is an even number of 2 or more).

  Preferably, the first internal electrode is drawn out to the first main surface, the portion drawn out to the first main surface is physically and electrically connected to the connection conductor, and the second internal electrode is connected to the second main electrode. A portion drawn out to the main surface and drawn out to the second main surface is physically and electrically connected to the terminal electrode.

  Preferably, the varistor element body is formed by laminating a varistor layer in which the first internal electrode is formed and a varistor layer in which the second internal electrode is formed. The layer extends in a direction parallel to the stacking direction of the layers and perpendicular to the first and second internal electrodes.

  The varistor element according to the present invention can be mounted appropriately and easily even in the case of a BGA package.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted. In the present embodiment, the present invention is applied to a multilayer chip varistor.

  The configuration of the multilayer chip varistor 1 according to the present embodiment will be described with reference to FIGS. 1 and 2 are perspective views showing the multilayer chip varistor according to the present embodiment. FIG. 3 is a diagram illustrating a cross-sectional configuration along the line III-III in FIG. FIG. 4 is a diagram illustrating a cross-sectional configuration along the line IV-IV in FIG. FIG. 5 is a diagram illustrating a cross-sectional configuration along the line V-V in FIG. 4.

  As shown in FIGS. 1 to 5, the multilayer chip varistor 1 includes a varistor element body 11, a plurality (two in the present embodiment) of connection conductors 41, and a plurality (four in the present embodiment). ) Terminal electrode 51.

  The varistor element body 11 has a substantially rectangular plate shape. For example, the varistor element body 11 is set to have a length of about 1 mm, a width of about 1 mm, and a thickness of about 0.5 mm. The varistor element body 11 has a first main surface 13 and a second main surface 15 that face each other. The first main surface 13 and the second main surface 15 have a square shape. That is, the varistor element body 11 has a square shape when viewed from a direction perpendicular to the first main surface 13 and the second main surface 15.

  The varistor element body 11 is configured as a stacked body in which a plurality of varistor layers that exhibit voltage nonlinear characteristics (hereinafter referred to as “varistor characteristics”) are stacked. In the actual multilayer chip varistor 1, the plurality of varistor layers are integrated so that the boundary between them cannot be visually recognized. The varistor layer contains ZnO (zinc oxide) as a main component and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, K) as subcomponents. Rb, Cs) and simple earth metals such as alkaline earth metal elements (Mg, Ca, Sr, Ba) and element bodies containing these oxides. In the present embodiment, the varistor layer contains Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents.

  In the present embodiment, Pr is used as the rare earth metal. Pr is a material for expressing varistor characteristics. The reason for using Pr is that voltage non-linearity is excellent and characteristic variation during mass production is small.

  In the present embodiment, Ca is used as the alkaline earth metal element. Ca becomes a material for controlling the sinterability of the ZnO-based varistor material and improving the moisture resistance. The reason for using Ca is to improve voltage nonlinearity.

  Although content of ZnO in a varistor layer is not specifically limited, When the whole material which comprises a varistor layer is 100 mass%, it is 99.8-69.0 mass% normally. The thickness of the varistor layer is, for example, about 5 to 60 μm.

  The varistor element body 11 is provided with a plurality of (in this embodiment, two layers) first internal electrode layers 21 and second internal electrode layers 31. The first internal electrode layer 21 and the second internal electrode layer 31 are arranged so that at least one varistor layer is interposed between them.

  Each first internal electrode layer 21 includes a plurality of (in the present embodiment, two) first internal electrodes 23 as shown in FIGS. 3 to 5. Each first internal electrode 23 has a substantially rectangular shape. One first internal electrode 23 is opposed to one second internal electrode 33, which will be described later, with at least a part thereof sandwiching the varistor layer. The first internal electrodes 23 included in the same first internal electrode layer 21 have a predetermined interval from a side surface parallel to the stacking direction of the varistor layers (hereinafter simply referred to as “stacking direction”) and are electrically connected to each other. Are located at predetermined intervals so as to be electrically insulated. Each first internal electrode 23 is drawn out to the first main surface 13 so that one end thereof faces the first main surface 13.

  As shown in FIGS. 3 to 5, each second internal electrode layer 31 includes a plurality (two in the present embodiment) of second internal electrodes 33. Each second internal electrode 33 has a substantially rectangular shape. One second internal electrode 33 faces at least a part of the first internal electrode 23 across the varistor layer. Similar to the first internal electrode 23, the second internal electrodes 33 included in the same second internal electrode layer 31 have a predetermined interval from the side surface parallel to the stacking direction and are electrically insulated from each other. In this way, they are located at predetermined intervals. Each second internal electrode 33 is drawn out to the second main surface 15 so that one end thereof faces the second main surface 15.

  As described above, the first internal electrode 23 and the second internal electrode 33 are arranged in the varistor element body 11 so that at least some of them face each other. Thereby, in the multilayer chip varistor 1, a plurality of (internal) pairs of internal electrodes including the first and second internal electrodes 23 and 33 arranged in the varistor element body 11 so that at least some of them are opposed to each other. In the embodiment, four) are provided.

  The first internal electrode 23 and the second internal electrode 33 include a conductive material. Although it does not specifically limit as a electrically conductive material contained in the 1st internal electrode 23 and the 2nd internal electrode 33, It is preferable to consist of Pd or an Ag-Pd alloy. The thickness of the first internal electrode 23 and the second internal electrode 33 is, for example, about 0.5 to 5 μm.

  The first main surface 13 and the second main surface 15 extend in a direction parallel to the stacking direction and perpendicular to the first and second inner electrodes 23 and 33. The stacking direction is a direction parallel to the facing direction of the first internal electrode 23 and the second internal electrode 33, and is a direction perpendicular to the first and second internal electrodes 23 and 33.

  As shown in FIGS. 3 and 5, each of the connection conductors 41 includes the first inner electrode 23 included in the two internal electrode pairs positioned in the stacking direction among the four internal electrode pairs. It is formed on the 1st main surface 13 so that the part pulled out by 1 main surface 13 may be covered. A portion of the first internal electrode 23 drawn out to the first main surface 13 is physically and electrically connected to the corresponding connection conductor 41. As a result, the connection conductor 41 electrically connects the first internal electrodes 23 included in the two internal electrode pairs positioned side by side in the stacking direction.

  Each connection conductor 41 has a substantially rectangular shape (in this embodiment, a substantially rectangular shape). For example, the connecting conductor 41 has a long side length of about 0.8 mm, a short side length of about 0.4 mm, and a thickness of about 2 μm. The long side direction of the connection conductor 41 is parallel to the stacking direction.

  The connection conductor 41 includes Pt. The connection conductor 41 is formed by baking a conductive paste as will be described later. As the conductive paste, a mixture of metal powder containing Pt particles as a main component and glass frit, an organic binder, and an organic solvent is used.

  As shown in FIGS. 2 and 4, each terminal electrode 51 is provided on the second main surface 15 in correspondence with each second internal electrode 33, and has n rows and n columns (parameter n is equal to n). 2 is an even number of 2 or more). In the present embodiment, the terminal electrodes 51 are two-dimensionally arranged in 2 rows and 2 columns. The terminal electrode 51 has a substantially rectangular shape (in the present embodiment, a substantially square shape). In the terminal electrode 51, for example, the length of each side is set to about 0.4 mm, and the thickness is set to about 2 μm.

  As shown in FIGS. 3 and 5, each terminal electrode 51 is formed on the second main surface 15 so as to cover a portion drawn out to the second main surface 15 of the corresponding second internal electrode 33. Is formed. The portion of the second internal electrode 33 that is drawn out to the second main surface 15 is physically and electrically connected to the corresponding terminal electrode 51. As a result, the terminal electrode 51 is electrically connected to the corresponding second internal electrode 33.

  The terminal electrode 51 contains Pt. The terminal electrode 51 is formed by baking a conductive paste as will be described later. As the conductive paste, a mixture of metal powder containing Pt particles as a main component and glass frit, an organic binder, and an organic solvent is used. A solder bump 53 is formed on each terminal electrode 51.

  As described above, the first internal electrode 23 and the second internal electrode 33 are positioned so that at least some of them face each other and overlap each other when viewed from the stacking direction. Therefore, the region of the varistor layer that overlaps the first internal electrode 23 and the second internal electrode 33 functions as a region that develops varistor characteristics.

  In the multilayer chip varistor 1 having the above-described configuration, as shown in FIG. 6, two sets of two varistors B connected in series are included. Each varistor B is composed of a first internal electrode 23, a second internal electrode 33, and a region overlapping the first and second internal electrodes 23, 33 in the varistor layer.

  As described above, the long side direction of the connection conductor 41 is substantially parallel to the stacking direction, that is, the connection conductor 41 is formed to extend in the stacking direction. One terminal electrode 51 and the other terminal electrode 51 of two varistors B connected in series are juxtaposed in the stacking direction. Therefore, two varistors B connected in series exist between the pair of terminal electrodes 51 that are juxtaposed in the long side direction of the connection conductor 41.

  Subsequently, a manufacturing process of the multilayer chip varistor 1 having the above-described configuration will be described with reference to FIGS. FIG. 7 is a flowchart for explaining the manufacturing process of the multilayer chip varistor according to the present embodiment. FIG. 8 is a view for explaining the manufacturing process of the multilayer chip varistor according to the present embodiment.

  First, after weighing ZnO, which is a main component constituting the varistor layer, and trace additives such as Pr, Co, Cr, Ca, Si, K, and Al metals or oxides so as to have a predetermined ratio. The varistor material is adjusted by mixing the components (step S101). Then, an organic binder, an organic solvent, an organic plasticizer, etc. are added to this varistor material, and it mixes and grinds for about 20 hours using a ball mill etc., and obtains a slurry.

  The slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 30 μm. The film thus obtained is peeled from the film to obtain a green sheet (step S103).

  Next, a plurality of electrode portions (numbers corresponding to the number of divided chips described later) corresponding to the first internal electrodes 23 are formed on the green sheet (step S105). Similarly, a plurality of electrode portions corresponding to the second internal electrode 33 (a number corresponding to the number of divided chips described later) are formed on different green sheets (step S105). The electrode portions corresponding to the first and second internal electrodes 23 and 33 are printed by a printing method such as screen printing with a conductive paste in which a metal powder mainly composed of Pd particles, an organic binder, and an organic solvent is mixed. It is formed by drying.

  Next, a sheet laminate is formed by stacking each green sheet on which electrode portions are formed and a green sheet on which electrode portions are not formed in a predetermined order (step S107). The sheet laminate thus obtained is cut into, for example, chips, to obtain a plurality of divided green bodies LS1 (see FIG. 8) (step S109). In the obtained green body LS1, a green sheet GS1 in which an electrode portion EL1 corresponding to the first internal electrode 23 is formed, a green sheet GS2 in which an electrode portion EL2 corresponding to the second internal electrode 33 is formed, A green sheet GS3 on which the electrode portions EL1 and EL2 are not formed is sequentially laminated. In addition, you may laminate | stack the green sheet GS3 in which electrode part EL1, EL2 is not formed in each part as needed.

  Next, the green body LS1 is subjected to heat treatment at 180 to 400 ° C. for about 0.5 to 24 hours to remove the binder, and then further fired at 850 to 1400 ° C. for about 0.5 to 8 hours. (Step S111) to obtain the varistor element body 11. By this firing, the green sheets GS1 to GS3 in the green body LS1 become varistor layers. The electrode portion EL <b> 1 becomes the first internal electrode 23. The electrode portion EL <b> 2 becomes the second internal electrode 33.

  Next, the connection conductor 41 and the terminal electrode 51 are formed on the outer surface of the varistor element body 11 (step S113). Here, a conductive paste is printed on the first main surface 13 of the varistor element body 11 so as to be in contact with the corresponding first internal electrode 23 by a screen printing method, and then dried, thereby connecting conductors 41. A conductor portion corresponding to is formed. In addition, the conductive paste is printed on the second main surface 15 of the varistor element body 11 so as to be in contact with the corresponding second internal electrode 33 by a screen printing method, and then dried, whereby the terminal electrode 51 is formed. Corresponding electrode portions are formed. And the formed electrode part (conductive paste) is baked at 500-850 degreeC, and the varistor element | base_body 11 with which the connection conductor 41 and the terminal electrode 51 were formed is obtained. As described above, the conductive paste for the connection conductor 41 and the terminal electrode 51 may be a mixture of a metal powder containing Pt particles as a main component and a glass frit, an organic binder, and an organic solvent. The glass frit used for the conductive paste for the connection conductor 41 and the terminal electrode 51 contains at least one or more of B, Bi, Al, Si, Sr, Ba, Pr, Zn and the like.

  Through the process described above, the multilayer chip varistor 1 is obtained. In addition, you may diffuse an alkali metal (for example, Li, Na, etc.) from the surface of the varistor element | base_body 11 after baking. As a method for forming the solder bump 53, an existing forming method can be used, and a description thereof is omitted here.

  As a method for forming the sheet laminate, a method for manufacturing an aggregate substrate described in the specification of Japanese Patent Application No. 2005-201963, which is a prior application of the present application, may be used. In this case, the conductive paste for the connection conductor 41 and the terminal electrode 51 can be applied without dividing and baking the sheet laminate (aggregate substrate) into a plurality of green bodies LS2.

  As described above, according to the present embodiment, since the plurality of terminal electrodes 51 are formed on the second main surface 15 of the varistor element body 11, the second main surface 15 is mounted on a mounting component (for example, an electronic component). The multilayer chip varistor 1 can be mounted in a state of facing a component, a mounting substrate, etc., and a configuration corresponding to the BGA package is realized. Since the connection conductor 41 is formed on the first main surface 15 so as to electrically connect the first internal electrodes 23 included in the two internal electrode pairs positioned side by side in the stacking direction, In the element body 11, a region functioning as the varistor B exists at a position corresponding to the connection conductor 41. Therefore, the connection conductor 41 functions as a mark for identifying the mounting direction of the multilayer chip varistor 1, and the multilayer chip varistor 1 can be mounted appropriately and easily.

  When the varistor element body 11 is square when viewed from the direction perpendicular to the first and second main surfaces 13 and 15, the mounting direction of the multilayer chip varistor 1 is based on the outer shape of the varistor element body 11. Is particularly effective because it is difficult to identify.

  Further, according to the present embodiment, it is not necessary to newly provide a mark for identifying the mounting direction of the multilayer chip varistor 1 on the varistor element body 11, and the manufacturing cost of the multilayer chip varistor 1 does not increase.

  Further, in the present embodiment, the varistor element body 11 includes Pr and Ca, and the conductive paste for the connection conductor 41 and the terminal electrode 51 includes Pt. The connection conductor 41 and the terminal electrode are formed on the varistor element body 11. The connection conductor 41 and the terminal electrode 51 are formed by applying and baking a conductive paste for 51. Thereby, the joint strength of the varistor element body 11, the connection conductor 41, and the terminal electrode 51 can be improved.

  The effect of improving the bonding strength between the varistor element body 11, the connection conductor 41, and the terminal electrode 51 is considered to be caused by the following phenomenon when baking the conductive paste. When the conductive paste is baked on the varistor element body 11, Pr and Ca contained in the varistor element body 11 move near the surface of the varistor element body 11, that is, near the interface between the varistor element body 11 and the conductive paste. And Pr and Ca which moved to the interface vicinity of the varistor element | base_body 11 and an electrically conductive paste, and Pt contained in an electrically conductive paste mutually diffuse. When Pr, Ca, and Pt are interdiffused, a compound of Pr and Pt and a compound of Ca and Pt are formed in the vicinity (including the interface) between the varistor element body 11, the connection conductor 41, and the terminal electrode 51. May be. These compounds cause an anchor effect, and the bonding strength between the varistor element body 11, the connection conductor 41, and the terminal electrode 51 is improved.

  The terminal electrode 51 containing Pt is suitable mainly when the multilayer chip varistor 1 is mounted on an external substrate or the like by solder reflow, and can improve solder erosion resistance and solderability.

  Subsequently, a configuration of a multilayer chip varistor according to a modification of the present embodiment will be described with reference to FIGS. FIG. 9 is a perspective view showing a modification of the multilayer chip varistor according to the present embodiment. FIG. 10 is a diagram illustrating a cross-sectional configuration along the line XX in FIG. FIG. 11 is a diagram illustrating a cross-sectional configuration along the line XI-XI in FIG. 12 is a diagram for explaining a cross-sectional configuration along the line XII-XII in FIG.

  In the multilayer chip varistor 1 according to the modified example, as shown in FIGS. 9 to 12, each connection conductor 41 has a direction perpendicular to the lamination direction (that is, parallel to the varistor layer) among the four internal electrode pairs. Formed on the first main surface 13 so as to cover a portion drawn to the first main surface 13 of each first internal electrode 23 included in the two internal electrode pairs positioned side by side in the direction). .

  The long side direction of the connection conductor 41 is substantially perpendicular to the stacking direction, that is, the connection conductor 41 is formed to extend in a direction perpendicular to the stacking direction. Further, as shown in FIG. 13, one terminal electrode 51 and the other terminal electrode 51 of two varistors B connected in series are juxtaposed in a direction perpendicular to the stacking direction. Therefore, two varistors B connected in series exist between the pair of terminal electrodes 51 that are juxtaposed in the long side direction of the connection conductor 41.

  The preferred embodiments of the present invention have been described above. However, the present invention is not necessarily limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  For example, the number of internal electrode pairs is not limited to four. The number of internal electrode pairs may be two or four or more, but is preferably an even number.

  In the embodiment described above, one connection conductor 41 is provided for two internal electrode pairs, but the present invention is not limited to this. For example, one connection conductor 41 may be provided for three internal electrode pairs. In this case, the connection conductor 41 electrically connects the first internal electrodes 23 included in the three internal electrode pairs positioned side by side in the stacking direction or in a direction perpendicular to the stacking direction.

  In the multilayer chip varistor 1 described above, each varistor B has a configuration in which one first internal electrode 23 and one second internal electrode 33 sandwich a varistor layer. However, the present invention is not limited to this. Each varistor B may have a configuration in which a plurality of first internal electrodes 23 and a plurality of second internal electrodes 33 each sandwich a varistor layer.

It is a perspective view which shows the multilayer chip varistor concerning this embodiment. It is a perspective view which shows the multilayer chip varistor concerning this embodiment. It is a figure explaining the cross-sectional structure along the III-III line of FIG. It is a figure explaining the cross-sectional structure along the IV-IV line of FIG. It is a figure explaining the cross-sectional structure along the VV line of FIG. It is a figure for demonstrating the equivalent circuit of the multilayer chip varistor concerning this embodiment. It is a flowchart for demonstrating the manufacturing process of the multilayer chip varistor concerning this embodiment. It is a figure for demonstrating the manufacturing process of the multilayer chip varistor concerning this embodiment. It is a perspective view which shows the modification of the multilayer chip varistor which concerns on this embodiment. It is a figure explaining the cross-sectional structure along the XX line of FIG. It is a figure explaining the cross-sectional structure along the XI-XI line of FIG. It is a figure explaining the cross-sectional structure along the XII-XII line | wire of FIG. It is a figure for demonstrating the equivalent circuit of the modification of the multilayer chip varistor concerning this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Multilayer chip varistor, 11 ... Varistor element body, 13 ... 1st main surface, 15 ... 2nd main surface, 23 ... 1st internal electrode, 33 ... 2nd internal electrode, 41 ... Connection conductor, 51 ... Terminal electrode, 53 ... Solder pump, B ... Varistor.

Claims (5)

A varistor element body having first and second principal surfaces facing each other;
A plurality of internal electrode pairs each having first and second internal electrodes disposed in the varistor element body so that at least some of them face each other;
The predetermined internal electrode pair is formed on the first main surface so as to electrically connect said first internal electrodes to each other, each having between predetermined internal electrode pair of the plurality of internal electrode pairs A connecting conductor;
A plurality of terminal electrodes provided corresponding to the second internal electrodes of the plurality of internal electrode pairs and formed on the second main surface so as to be electrically connected to the second internal electrodes; , equipped with a,
A varistor element, wherein varistors respectively configured in the predetermined internal electrode pair are connected in series through the connection conductor .   The varistor element according to claim 1, wherein the varistor element body has a square shape when viewed from a direction perpendicular to the first and second main surfaces.   2. The varistor element according to claim 1, wherein the plurality of terminal electrodes are two-dimensionally arranged in n rows and n columns (n is an even number of 2 or more). The first internal electrode is drawn out to the first main surface, and a portion drawn out to the first main surface is physically and electrically connected to the connection conductor;
2. The second internal electrode is drawn out to the second main surface, and a portion drawn out to the second main surface is physically and electrically connected to the terminal electrode. The varistor element described in 1. In the varistor element body, a varistor layer in which the first internal electrode is formed and a varistor layer in which the second internal electrode is formed are laminated,
The said 1st and 2nd main surface is extended in the direction parallel to the lamination direction of the said varistor layer, and a perpendicular | vertical direction to the said 1st and 2nd internal electrode. Varistor element.

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