JP4277572B2 - Solid-state imaging device and method for manufacturing solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and a method for manufacturing the solid-state imaging device, and more particularly to a solid-state imaging device employing a horizontal overflow drain structure and a method for manufacturing the solid-state imaging device.
[0002]
[Prior art]
One phenomenon unique to solid-state imaging devices is blooming. In this blooming, when strong light exceeding the saturation light quantity enters the light receiving part (pixel), excess charge overflows from the light receiving part photoelectrically converted by the light receiving part, and the overflowed charge is transferred to the vertical transfer part. If the light leaks into the surrounding light-receiving part, for example, leaks into the vertical transfer part, it means a phenomenon in which the image quality deteriorates due to white streaks (stripes) in the vertical direction (up and down direction) from where the light is strong.
[0003]
In order to suppress the occurrence of blooming, a solid-state image pickup device represented by a CCD (Charge Coupled Device) type image pickup device has long formed an overflow drain portion adjacent to the light receiving portion, and the light receiving portion and the overflow drain. A horizontal overflow drain structure in which an overflow control gate portion is disposed between the two portions is employed (see, for example, Patent Document 1).
[0004]
In the solid-state imaging device adopting this horizontal overflow drain structure, since the overflow drain part and the overflow control gate part are arranged beside the light receiving part, when the area of the unit cell is constant, the overflow drain part and An extra space for the overflow control gate portion must be secured, and the area of the light receiving portion is reduced accordingly, which is disadvantageous in improving sensitivity.
[0005]
From this point of view, in recent years, in solid-state imaging devices, for example, a P-type well region is formed as an overflow barrier region at a deep position inside a semiconductor substrate such as an N-type silicon substrate, and excess is passed through the overflow barrier region. The mainstream has adopted a vertical overflow drain structure that sweeps away a large amount of charge into the substrate (see, for example, Patent Document 2).
[0006]
[Patent Document 1]
JP-A-5-335546 (in particular, FIG. 1, FIG. 3 and paragraph 0020)
[Patent Document 2]
JP 2002-57318 A (particularly FIGS. 2, 5 and paragraph 0031)
[0007]
[Problems to be solved by the invention]
By the way, in the solid-state imaging device having the vertical overflow drain structure, the potential of the overflow barrier region is modulated by the signal charge accumulated in the light receiving portion. Therefore, as shown in FIG. Has a so-called knee characteristic in which the amount of charge handled (signal output voltage value) increases. In general, a solid-state imaging device that employs a vertical overflow drain structure has this knee characteristic. Therefore, it is necessary to consider the following two points in device design.
1) The width of the read gate portion is increased to enhance the blooming resistance of the read gate portion.
2) Give a margin to the amount of charge handled by the vertical transfer unit.
[0008]
However, since the width of the vertical transfer unit and the area of the light receiving unit are in a trade-off relationship, increasing the width of the vertical transfer unit and increasing the amount of charge handled leads to a decrease in the area of the light receiving unit. This means a reduction in the amount of charge handled and a reduction in the opening area of the light receiving portion.
[0009]
In the vertical overflow drain structure, an electronic shutter operation is realized by applying a shutter voltage to the semiconductor substrate, deepening the potential of the overflow barrier region, and discarding unnecessary charges inside the substrate. However, in a multi-pixel high-density solid-state imaging device, as the unit cell size decreases, the P-type well region that is the overflow barrier region is more easily affected by the impurity concentration of the nearby P-type impurity region, If a high voltage is not applied to the semiconductor substrate, unnecessary charges cannot be discarded, and there is a problem that the shutter voltage is generally increased.
[0010]
The present invention has been made in view of the above problems, and the object of the present invention is to provide a solid-state imaging device having a light receiving portion with a low knee characteristic and excellent blooming controllability in the relationship between the incident light amount and the accumulated charge amount, and The object is to provide a method of manufacturing the solid-state imaging device.
[0011]
[Means for Solving the Problems]
A solid-state imaging device having a lateral overflow drain structure according to the present invention is formed between a light receiving unit including a photoelectric conversion region of the same conductivity type as the substrate formed on an substrate via an epitaxial layer, and the adjacent light receiving unit. A drain portion provided in the trench portion in a state of being electrically connected to the substrate at the bottom of the same conductivity type as the substrate of the trench portion, and discharging the charge from the light receiving portion to the semiconductor substrate; It is characterized by having prepared.
[0012]
In the solid-state imaging device having the above-described configuration, the drain portion electrically connected to the substrate has a trench structure, so that the potential of the overflow channel region is less likely to be modulated by the signal charge accumulated in the light receiving portion. As a result, it is possible to obtain a light receiving portion with a low knee characteristic and excellent blooming controllability in the relationship between the amount of incident light and the amount of accumulated charge of the light receiving portion.
[0013]
A method of manufacturing a solid-state imaging device having a lateral overflow drain structure according to the present invention includes a method of forming a surface of an epitaxial layer between light receiving portions including a photoelectric conversion region of the same conductivity type as the substrate to be formed on the substrate via an epitaxial layer. A first step of forming a trench portion so as to enter the substrate; a second step of forming an impurity layer having a conductivity type opposite to that of the substrate so as to surround a side wall of the trench portion; and the side wall surrounded by the impurity layer. And a third step of forming a layer of the same conductivity type as that of the substrate so as to fill the trench portion and electrically connecting to the substrate at the bottom of the layer .
[0014]
By forming the drain portion in the above steps, a lateral overflow drain structure having a trench structure can be formed. By adopting this lateral overflow drain structure having a trench structure, the potential of the overflow channel region is less likely to be modulated by the signal charge accumulated in the light receiving portion. As a result, it is possible to obtain a light receiving portion with a low knee characteristic and excellent blooming controllability in the relationship between the amount of incident light and the amount of accumulated charge of the light receiving portion.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
FIG. 1 is a plan view showing an outline of a configuration of a unit cell (unit pixel and a vertical transfer unit corresponding to the unit cell) of a CCD solid-state imaging device having a lateral overflow drain structure according to an embodiment of the present invention. It is sectional drawing which shows the cross-section of AA'1 of 1 view. Here, as an example, a case where the first conductivity type is N-type and the second conductivity type is P-type will be described as an example, but the present invention is not limited to this.
[0017]
1 and 2, a semiconductor substrate 11 on which a CCD solid-state imaging device according to this embodiment is formed includes, for example, an N-type semiconductor substrate 12 having an N ⁺ layer 13 formed by ion implantation on the substrate surface, An N-type epitaxial layer (hereinafter abbreviated as “epi layer”) 14 formed on the substrate 12 is formed. The semiconductor substrate 11 is not limited to this configuration, and may be configured from an N ⁺ type semiconductor substrate and an N type epi layer formed on the substrate.
[0018]
On the surface layer portion of the semiconductor substrate 11, a light receiving portion 15, a vertical transfer portion 16, and a readout gate portion 17 are formed. Specifically, the light receiving unit (pixel) 15 includes an N-type photoelectric conversion region (signal charge storage region) 18 formed in the N-type epi layer 14 and a P ⁺ type positive charge formed thereon. The storage region 19 is arranged on the semiconductor substrate 11 in a matrix.
[0019]
The vertical transfer unit 16 includes an N-type transfer channel 20 formed in the epi layer 14, a P-type well region 21 formed under the transfer channel 20, and a gate on the substrate surface above the transfer channel 20. It is composed of transfer electrodes 22 formed through an insulating film 23, and the light receiving portions 15 are arranged for each vertical column with respect to a pixel arrangement in which the light receiving portions 15 are arranged in a matrix. As is apparent from FIG. 1, the transfer electrode 22 includes a first-layer transfer electrode (indicated by a one-dot chain line) 22-1 and a second-layer transfer electrode (indicated by a two-dot chain line in the figure) 22. -2 has a two-layer structure.
[0020]
In the electrode structure of the vertical transfer unit 16, the transfer electrode 22 to which a transfer clock of a specific phase is applied extends to the vicinity of the light receiving unit 15, and the electrode of this extended part is the readout gate unit 17. The gate electrode is also used. That is, the read gate portion 17 is configured by a gate electrode that also serves as a part of the transfer electrode 22 and a channel region under the gate electrode.
[0021]
In particular, as is apparent from FIG. 1, under the transfer electrodes 22-1 and 22-2 between adjacent light receiving portions (pixels) 15 and 15 in the transfer direction (vertical direction) of the transfer channel 20 of the vertical transfer portion 17 The N ⁺ type drain portion 24 having a trench-like structure, which is a characteristic part of the present invention, is formed. As is apparent from FIG. 2, the N ⁺ -type drain portion 24 includes a trench portion 25 formed so as to enter the N ⁺ layer 13 on the semiconductor substrate 12 from the surface of the epi layer 14, and a sidewall of the trench portion 25. Is formed of a P-type impurity layer 26 formed so as to surround and an N ⁺ layer 27 serving as a drain region formed in the trench portion 25.
[0022]
In the N ⁺ type drain part 24, the bottom part of the trench part 25 is a high concentration N ⁺ layer that can cancel the P layer of the P type impurity layer 26. The P-type impurity layer 26 is formed to a desired thickness, and becomes a channel (overflow channel) region between the N-type photoelectric conversion region 18 and the N ⁺ -type drain portion 24 of the light receiving unit 15. Also, the N ⁺ -type drain region 24, since the N ⁺ layer 27 is sufficiently-enriched than P-type impurity layer 26 covering the N ⁺ layer 27, a drain portion 24 to the N ⁺ layer 13 on the semiconductor substrate 12 And become electrically connected. Thereby, a lateral overflow drain structure having an N ⁺ type drain portion 24 having a trench structure electrically connected to the semiconductor substrate 12 is formed.
[0023]
The region excluding the upper region of the light receiving unit 15, that is, the top of the vertical transfer unit 16 and the readout gate unit 17 is covered with a light shielding film 29 made of aluminum, tungsten, or the like via an interlayer insulating film 28. As a result, the upper region of the light receiving unit 15 that is not covered by the light shielding film 29 becomes the opening 30, and incident light is taken into the light receiving unit 15 through the opening 30.
[0024]
In the CCD solid-state imaging device having the above configuration, incident light from the outside is taken into the light receiving unit 15 through the opening 30 and is photoelectrically converted by the light receiving unit 15. The photoelectrically converted minority carriers (here, electrons), that is, signal charges are accumulated in the photoelectric conversion region (signal charge accumulation region) 18. The accumulated signal charges are read to the transfer channel 20 of the vertical transfer unit 16 by the read gate unit 17 and are vertically transferred by applying a transfer clock to the transfer electrode 22.
[0025]
Here, when strong light exceeding the saturation light quantity is incident on the light receiving unit 15, excessive charge out of the signal charge photoelectrically converted by the light receiving unit 15 overflows from the light receiving unit 15, and the overflowed charge is transferred to the vertical transfer unit or the surrounding area. Blooming occurs by leaking into the pixels. In order to suppress the occurrence of blooming, the CCD solid-state imaging device according to the present embodiment employs a lateral overflow drain structure having an N ⁺ -type drain portion 24 having a trench-like structure electrically connected to the semiconductor substrate 12. .
[0026]
The operation principle of the lateral overflow drain structure having the trench-like N ⁺ -type drain portion 24 will be described below.
[0027]
Since the N ⁺ -type drain portion 24 is electrically connected to the semiconductor substrate 12, the potential of the N ⁺ -type drain portion 24 becomes the substrate potential by applying a positive bias voltage to the semiconductor substrate 12. The amount of charge handled by the light receiving unit 15 is defined by the potential barrier of the P-type impurity layer 26, which is an overflow channel region between the light receiving unit 15 and the N ⁺ type drain unit 24. Excess charge exceeding this potential barrier is N It is discharged to the semiconductor substrate 12 through the ⁺ type drain part 24.
[0028]
Here, by adjusting the bias voltage (substrate voltage) applied to the semiconductor substrate 12, the potential of the potential barrier of the P-type impurity layer 26 that defines the amount of charge handled by the light receiving unit 15 changes. Handling charge amount and blooming can be controlled. Also in the electronic shutter operation, by applying a large positive shutter voltage to the semiconductor substrate 12 at a desired timing, unnecessary charges accumulated in the light receiving unit 15 are applied to the semiconductor substrate 12 through the N ⁺ type drain unit 24. Discharged.
[0029]
FIG. 3 is a potential diagram of the light-receiving unit 15, the P-type impurity layer 26, and the N ⁺ -type drain unit 24. In FIG. 3, A indicates the overflow control time and B indicates the electronic shutter time.
[0030]
As described above, in the CCD solid-state imaging device according to this embodiment, the N ⁺ -type drain portion 24 electrically connected to the semiconductor substrate 12 has a trench-like structure, so that a P-type impurity layer serving as an overflow channel region is formed. 26 is less susceptible to modulation by the signal charge accumulated in the light receiving portion 15, so that the light receiving portion 15 having a low knee characteristic in the relationship between the incident light amount and the output signal amount of the light receiving portion 15 and excellent in blooming controllability can be obtained. Can do. Compared with the vertical overflow drain structure, since the knee characteristic of the incident light quantity versus the output signal quantity can be reduced, it is not necessary to provide a margin for the knee characteristic in the amount of charge handled by the vertical transfer unit 16, and thus higher sensitivity. It is possible to provide a CCD solid-state imaging device having low smear characteristics.
[0031]
Further, in the horizontal overflow drain structure having the N ⁺ type drain portion 24 having a trench structure, even if the size of the unit cell is reduced with the increase in the number of pixels and the density of the CCD solid-state imaging device, the trench structure is used. As a result, the P-type impurity layer 26 is not easily affected by the impurity concentration in other regions, so that it is not necessary to apply a high voltage to the semiconductor substrate 12, thereby realizing a low-voltage-driven electronic shutter operation.
[0032]
Further, since the N ⁺ -type drain portion 24 has a trench-like structure electrically connected to the semiconductor substrate 12, the amount of charge handled by the light-receiving portion 15 and blooming can be controlled by a bias voltage applied to the semiconductor substrate 12. Unlike the conventional horizontal overflow drain structure, since it is not necessary to provide a control gate electrode on the substrate surface side, a small footprint overflow drain structure and shutter drain structure can be formed.
[0033]
In addition, since the N ⁺ -type drain portion 24 is provided under the transfer electrode 22 (22-1 and 22-2) between adjacent pixels in the vertical direction, it is not necessary to secure a special arrangement space. Since the light receiving area of the light receiving portion 15 is not affected at all, the N ⁺ type drain portion 24 is not lowered in sensitivity even though it has a horizontal overflow drain structure. By exhibiting such operational effects, a CCD solid-state imaging device having a good dynamic range and sensitivity characteristics can be realized, although it is of higher density and higher definition.
[0034]
In this embodiment, the N ⁺ type drain part 24 is provided between pixels (light receiving parts) adjacent in the vertical direction. However, the present invention is not limited to this, and the N ⁺ type drain part 24 is very compact. Since it can be configured, it can be provided between adjacent pixels in the horizontal direction or in a channel stop region for pixel separation as long as an arrangement space can be secured.
[0035]
Next, the procedure of the method for manufacturing the CCD solid-state imaging device according to this embodiment having the above-described configuration will be described with reference to the process diagrams of FIGS.
[0036]
First, as shown in FIG. 4A, an N-type semiconductor substrate (or N ⁺ -type semiconductor substrate) 12 having an N ⁺ layer 13 formed by ion implantation on the substrate surface is prepared. Next, as shown in FIG. 4B, an epi layer 14 having a thickness of about 5 to 8 μm is formed on the N-type semiconductor substrate 12. Next, as shown in FIG. 4C, a trench portion 25 is formed by dry etching so as to enter the N ⁺ layer 13 on the semiconductor substrate 12 from the surface of the epi layer 14. At this time, the trench 25 is formed so that the bottom of the trench 25 stops in the N ⁺ layer 13.
[0037]
Next, as shown in FIG. 4D, a P-type impurity layer 26 is formed so as to surround the sidewall of the trench portion 25 by implanting boron using a photoresist 31 as a mask and using a high energy ion implanter. . At this time, multi-stage implantation with different implantation energy is performed. As an example, when the epi layer 14 is 5 μm,
(1) Boron implantation energy: 4 MeV, dose: 5 × 10 ¹² cm ^-2
(2) Boron implantation energy: 3 MeV, dose: 5 × 10 ¹² cm ^-2
(3) Boron implantation energy: 2 MeV, dose: 5 × 10 ¹² cm ^-2
(4) Boron implantation energy: 1 MeV, dose: 5 × 10 ¹² cm ^-2
[0038]
Note that heat treatment may be performed to obtain a desired width profile for the P-type impurity layer 26 after high-energy ion implantation. After that, since the diffusion is performed by the heat treatment, the heat treatment here may not be essential. Further, it is also possible to form the P-type impurity layer 26 by performing oblique ion implantation without using a high energy ion implantation machine.
[0039]
Next, as shown in FIG. 5A, a silicon oxide film 32 is formed on the wafer surface (substrate surface) by CVD (Chemical Vapor Deposition) or thermal oxidation, and a photoresist (not shown) is used as a mask. The silicon oxide film 32 on the trench portion 25 is selectively etched and removed. Next, as shown in FIG. 5B, a doped polysilicon 33 containing phosphorus is formed so as to fill the trench portion 25, thereby forming an N ⁺ layer 27. Next, as shown in FIG. 5C, the unnecessary surface polysilicon layer 33 and the silicon oxide film 32 used as a mask are removed by CMP (Chemical Mechanical Polish).
[0040]
In the step of forming the N ⁺ -type drain portion 24, as a method not using the doped polysilicon 33, a diffusion source containing N-type impurities such as phosphorus is deposited on the trench portion 25, and the sidewall of the trench portion 25 is formed. There is also a method of forming the N ⁺ layer 27 on the surface. In this case, the diffusion source is removed after the diffusion, and unnecessary film on the surface is removed using CMP as described above.
[0041]
Next, as shown in FIG. 6A, the light receiving unit 15 (N-type photoelectric conversion region 18 and P ⁺ -type positive charge storage region 19) and vertical transfer unit 16 (N-type transfer channel 20 and P-type well). An in-silicon profile such as region 21) is formed. In this case, it is possible to form each profile after forming the gate insulating film 23, or it is possible to form a sacrificial oxide film that may be removed later and perform various ion implantations thereon. is there.
[0042]
Next, as shown in FIG. 6B, a gate insulating film 23 is formed on the wafer surface, and a transfer electrode (gate electrode) 22 is formed using appropriate polysilicon or the like. Then, as shown in FIG. 6C, an interlayer insulating film 28 is formed on the transfer electrode 22, and a light shielding film 29 is formed using aluminum, tungsten, or the like. Thereafter, although not shown, a planarization film, a passivation film, a color filter, an on-chip microlens, and the like are sequentially formed by a known method.
[0043]
By forming the drain part in the above steps, a lateral overflow drain structure having a trench structure can be formed. By adopting the lateral overflow drain structure of this trench structure, the potential of the P-type impurity layer 26 serving as the overflow channel region is less likely to be modulated by the signal charge accumulated in the light receiving unit 15. It is possible to obtain the light receiving unit 15 having a low knee characteristic in terms of the accumulated charge amount and excellent in blooming controllability.
[0044]
In the above embodiment, the case where the present invention is applied to the pixel portion of the CCD solid-state imaging device has been described as an example. However, the present invention is not limited to this application example, and the present invention is not limited to the CCD solid-state imaging device. The present invention can be applied to pixel portions of all solid-state image sensors, such as solid-state image sensors, and XY address type solid-state image sensors represented by CMOS solid-state image sensors.
[0045]
【The invention's effect】
As described above, according to the solid-state imaging device according to the present invention, by adopting the lateral overflow drain structure of the trench-like structure, the potential of the overflow channel region is less likely to be modulated by the signal charge accumulated in the light receiving portion. It is possible to obtain a light-receiving part having a low knee characteristic and excellent blooming controllability in the relationship between the amount of incident light and the amount of accumulated charge of the light-receiving part.
[0046]
Further, according to the method for manufacturing a solid-state imaging device according to the present invention, a trench portion is formed between the light receiving portions to be formed on the substrate via the epitaxial layer so as to enter the substrate from the surface of the epitaxial layer. An impurity layer having a conductivity type opposite to that of the substrate is formed so as to surround the side wall of the substrate, and a layer having the same conductivity type as that of the substrate is formed so as to fill the trench portion. Therefore, it is possible to form a lateral overflow drain structure having a trench structure that can obtain a light receiving portion with less knee characteristics and excellent blooming controllability.
[Brief description of the drawings]
FIG. 1 is a plan view schematically showing the configuration of a unit cell of a CCD solid-state imaging device having a lateral overflow drain structure according to an embodiment of the present invention.
2 is a cross-sectional view showing a cross-sectional structure taken along the line AA ′ of FIG. 1;
FIG. 3 is a potential diagram for explaining operations during overflow control A and electronic shutter B;
FIG. 4 is a process diagram (part 1) illustrating a procedure of a method for manufacturing a CCD solid-state imaging device according to an embodiment of the present invention;
FIG. 5 is a process diagram (part 2) illustrating the procedure of the method for manufacturing the CCD solid-state imaging device according to the embodiment of the present invention.
FIG. 6 is a process diagram (part 3) illustrating the procedure of the method for manufacturing the CCD solid-state imaging device according to the embodiment of the present invention;
FIG. 7 is a characteristic diagram illustrating a relationship between an incident light amount and a signal output voltage value in a light receiving unit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Semiconductor base | substrate, 12 ... Semiconductor substrate, 13, 27 ... N ⁺ layer, 14 ... Epitaxial layer, 15 ... Light-receiving part, 16 ... Vertical transfer part, 17 ... Read-out gate part, 18 ... Photoelectric conversion area | region (Signal charge accumulation | storage) Region), 20 ... transfer channel, 22, 22-1, 22-2 ... transfer electrode, 24 ... N ⁺ type trench part, 25 ... trench part, 26 ... P type impurity layer

Claims (5)

A light receiving portion including a photoelectric conversion region of the same conductivity type as the substrate formed on the substrate via an epitaxial layer;
In the trench part formed between the adjacent light receiving parts, the bottom part of the same conductivity type as the substrate of the trench part is provided in a state of being electrically connected to the substrate, and the charge from the light receiving part is A solid-state imaging device having a horizontal overflow drain structure, comprising: a drain portion that discharges to the semiconductor substrate. The light receiving parts are formed in a matrix,
The solid-state imaging device according to claim 1, wherein the drain part is formed between the light receiving parts adjacent in the vertical direction. The light receiving parts are formed in a matrix,
The solid-state imaging device according to claim 1, wherein the drain part is formed between the light receiving parts adjacent in the horizontal direction. The drain portion includes an impurity layer having a conductivity type opposite to that of the substrate formed so as to surround a sidewall of the trench portion, and the substrate formed so as to fill the trench portion surrounded by the impurity layer. The solid-state imaging device according to claim 1, further comprising a layer of the same conductivity type. A first step of forming a trench portion so as to enter the substrate from the surface of the epitaxial layer between light receiving portions including a photoelectric conversion region of the same conductivity type as the substrate to be formed on the substrate via an epitaxial layer;
A second step of forming an impurity layer having a conductivity type opposite to that of the substrate so as to surround a sidewall of the trench part;
Horizontal including at least a third step of connecting with said substrate and electrically at the bottom of the form a substrate and a layer of the same conductivity type the layer to fill the trench portion sidewalls surrounded by the impurity layer A method for manufacturing a solid-state imaging device having an overflow drain structure .

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