JP4282137B2 - Manufacturing method of semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor memory having a capacitive element.EquipmentIt relates to a manufacturing method.
[0002]
[Prior art]
The document “Proceedings of Symp. VLSI Tech., 1998, pp. 126-127” discloses a 1T-1C (single-transistor / single-capacitor) type ferroelectric memory. In this example, it is 4.5μm by the rule of 0.5μm² The cell size is realized. The cell structure is a stack type, and the arrangement of cells is devised. The ferroelectric capacitor has a laminated structure of Pt (50 nm) / PZT (150 nm) / Pt (200 nm) / TiN (50 nm), and is processed by dry etching so that no residue remains on the pattern side wall. According to this dry etching, a capacitor having a shape in which the pattern side wall is largely inclined with respect to the upper surface of the substrate is formed.
[0003]
[Problems to be solved by the invention]
However, in the above conventional structure, the pattern side wall is inclined with respect to the substrate, so that it is difficult to increase the degree of integration.
[0004]
Further, as the element becomes finer, the shape of the element is greatly influenced by the pattern edge of the ferroelectric film. However, dry etching or milling is usually used for processing of the ferroelectric material, and these methods tend to damage the pattern edge.
[0005]
  Therefore, conventionally, the structure where the pattern side wall is perpendicular to the upper surface of the substrate.As a result, the area occupied by the capacitive element is reduced, and improvement in integration can be expected.The advent of a semiconductor memory device and the advent of a manufacturing method that hardly damages the pattern edge of a ferroelectric material have been desired.
[0013]
[Means for Solving the Problems]
ThisAccording to the method for manufacturing a semiconductor memory device of the invention, the step of depositing the first conductive layer on the base, the step of depositing the insulating layer on the upper surface of the first conductive layer, and the stopper layer on the upper surface of the insulating layer. A step of depositing, a step of forming a hole having a depth such that the upper surface of the first conductive layer is exposed in the capacitance region of the stopper layer and the insulating layer, and a ferroelectric layer being embedded in the hole of the stopper layer and the insulating layer Polishing the upper portion of the ferroelectric layer, matching the height of the upper surface of the ferroelectric layer with the height of the upper surface of the stopper layer, and conducting second conductive on the upper surfaces of the stopper layer and the ferroelectric layer. A step of depositing a layer, a step of forming a mask having a predetermined pattern at a position including the capacitance region on the upper surface of the second conductive layer, and the pattern of the mask on the second conductive layer, the stopper layer, the insulating layer, and the first conductive layer. And a transferring step.
[0014]
Thus, since the ferroelectric layer is embedded in the hole formed in the stopper layer and the insulating layer, the pattern edge shape of the ferroelectric layer is determined by the shape of the hole. Therefore, it is not necessary to perform pattern processing by etching, so that the ferroelectric layer is not damaged.
[0015]
Further, the side surface of the insulating layer serving as the side wall can be easily formed perpendicular to the upper surface of the base by a normal processing technique. Therefore, the occupied area is reduced and the degree of integration is improved.
[0016]
Furthermore, since the mask pattern may be transferred to the second conductive layer, the insulating layer, and the first conductive layer, the processing process is simplified.
[0017]
Further, since the stopper layer is provided on the insulating layer, there is no fear of excessive polishing of the ferroelectric layer.
[0018]
In the method of manufacturing a semiconductor memory device according to the present invention, it is preferable that the stopper layer and the second conductive layer are formed of the same material.
[0019]
Since the remaining second conductive layer and stopper layer constitute the upper electrode of the capacitive element, the area of the upper electrode can be increased.
[0020]
Further, as the material of the stopper layer, it is preferable to select a material having a low polishing rate and hardly reacting with the ferroelectric material when the ferroelectric layer is processed by a chemical mechanical polishing method. For example, the stopper layer may be an Ir layer, IrO₂ Layer, Pt layer, Ru layer, RuO₂ Layer, La_0.5 Sr_0.5 CoO_Three Layer, SrRuO_Three Layer and YBa₂ Cu_Three O_x (X is a positive integer) It is preferable to be constituted by a single-layer thin film of any one layer selected from the layers, or a laminated thin film of a plurality of layers arbitrarily selected from these layers. Further, the same material as the stopper layer may be used for the first and second conductive layers.
[0021]
In the method for manufacturing a semiconductor memory device according to the present invention, the step of polishing the upper portion of the ferroelectric layer is preferably performed by a chemical mechanical polishing method.
[0022]
In the method for manufacturing a semiconductor memory device of the present invention, the ratio of the hole diameter to the hole depth is preferably set to 1 or more.
[0023]
In this way, it is easy to embed a ferroelectric material in the hole.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. It should be noted that the drawings only schematically show the shape, size, and arrangement relationship to the extent that the present invention can be understood. In addition, the conditions and materials such as numerical values described below are merely examples. Therefore, the present invention is not limited to this embodiment.
[0025]
  [First reference example]
  First,First reference exampleThe configuration of the semiconductor memory device will be described. FIG.First reference exampleIt is sectional drawing which shows the principal part structure of this semiconductor memory device. This semiconductor memory device includes a capacitive element 10 that utilizes the characteristics of a ferroelectric substance. The capacitive element 10 is provided on the upper surface 12 a of the base 12. An interlayer insulating film 14 is deposited on the base 12, and the capacitive element 10 is covered with the interlayer insulating film 14. A wiring 16 is formed on the interlayer insulating film 14 to realize a required electrical wiring. In order to protect the wiring 16, a surface protective layer 18 is laminated on the interlayer insulating film 14.
[0026]
The base 12 is mainly composed of a Si substrate 20, p.^- Conductive Si layer (hereinafter referred to as p^- -It is called a Si layer. ) 22 and the interlayer insulating film 24. p^- The -Si layer 22 is formed on the top of the Si substrate 20. This p^- A predetermined region on the upper surface of the Si layer 22 is oxidized to form SiO₂ An element isolation oxide film 26 is formed. In each region partitioned by the element isolation oxide film 26, p^- N separated from each other on the upper surface of the Si layer 22⁺ Conductive Si layer (hereinafter n⁺ -It is called a Si layer. ) 28 and 30 are formed. These n⁺ P to bridge Si layers 28 and 30^- SiO on the upper surface of the Si layer 22₂ A gate electrode 32 is formed through the film. As the material of the gate electrode 32, for example, polysilicon is used.
[0027]
N mentioned above⁺ The -Si layers 28 and 30 function as a drain electrode and a source electrode of the transistor, respectively. Thus, the gate electrode 32 as the control electrode and the n as the main electrode⁺ A MOS transistor having Si layers 28 and 30 is formed on the Si substrate 20. This MOS transistor functions as a so-called selection transistor.
[0028]
In addition, this selection transistor is made of SiO.₂ Is covered with an interlayer insulating film 24 made of A through hole is formed at a predetermined position of the interlayer insulating film 24, and an appropriate conductor material is buried in the hole, and a wiring 34 for realizing electrical wiring between the selection transistor and the upper portion is formed. Yes.
[0029]
  Like thisFirst reference exampleThe capacitor element 10 is assumed to be used together with a control element such as the selection transistor described above. The capacitive element 10 has a structure called a stack structure.
[0030]
The capacitive element 10 is formed by laminating a lower electrode 36, a ferroelectric film 38 and an upper electrode 40 in this order on a base 12. The lower electrode 36 is provided in contact with the wiring 34 extending to the upper surface 12a of the base 12, and electrical coupling with the selection transistor is realized. In this example, the material of the lower electrode 36 is IrO.₂ Is used. The material of the ferroelectric film 38 is SrBi.₂ Ta₂ O₉ (Hereinafter abbreviated as SBT). As the upper electrode 40, IrO₂ A two-layer structure in which a TiN layer 44 is laminated on the upper surface of the layer 42 is employed.
[0031]
Then, the side surface (pattern edge) 36a of the lower electrode 36 and the side surface (pattern edge) 40a of the upper electrode 40 (that is, IrO₂ The side surfaces (pattern edges) of the layer 42 and the TiN layer 44 are located outside the side surfaces (pattern edges) 38 a of the ferroelectric film 38. That is, the ferroelectric film 38 is smaller in size in the direction parallel to the upper surface 12 a of the base 12 than the lower electrode 36 and the upper electrode 40. Therefore, when the pattern of each film is projected onto a plane perpendicular to the stacking direction of each film, the pattern of the ferroelectric film 38 is included in the pattern of the lower electrode 36 and the upper electrode 40. Note that the patterns of the lower electrode 36 and the upper electrode 40 are the same.
[0032]
  The side surface 38 a of the ferroelectric film 38 has a side surface 46 a substantially perpendicular to the upper surface 12 a of the base 12.The insulating layer portion 52b and the stopper layer portion 68b.Covered by side walls 46. Therefore, the side wall 46 includes the side surface 38 a of the ferroelectric film 38, the lower surface of the upper electrode 40 that protrudes from the pattern of the ferroelectric film 38, and the lower electrode 36 that protrudes from the pattern of the ferroelectric film 38. They are provided in contact with the upper surface. As the side wall 46, SiO₂An insulating film such as a film, a SiN film, or a SiON film is used.
[0033]
Further, the side surface (pattern edge) 46a of the side wall 46, the side surface 36a of the lower electrode 36, and the side surface 40a of the upper electrode 40 are substantially at the same position. Therefore, the pattern composed of the ferroelectric film 38 and the side wall 46 is the same as the pattern of the upper electrode 40 and the lower electrode 36. Since these patterns are overlapped with each other, the side surface of the capacitive element 10 is substantially perpendicular to the upper surface 12 a of the base 12. Therefore, the area occupied by the capacitive element 10 is reduced, and improvement in integration can be expected.
[0034]
In addition, since the area of the upper electrode 40 and the lower electrode 36 is larger than the area of the ferroelectric film 38, there is an advantage that the electric field applied to the ferroelectric film 38 tends to be uniform.
[0035]
The structure of the capacitive element 10 described above is covered with the interlayer insulating film 14. A through hole is formed above the upper electrode 40 of the interlayer insulating film 14, and an appropriate conductive material is embedded in the hole to form a wiring 48. The wiring 48 realizes electrical coupling between the upper electrode 40 and the wiring 16.
[0036]
As described above, the capacitor element 10 is connected in series to the source or drain of the MOS transistor formed in the base 12 and used as a memory element. The ferroelectric material has spontaneous polarization due to a bistable crystal structure, and can function as a memory element by electrically controlling the spontaneous polarization from the outside.
[0037]
  [Second Reference Example]
  Next, the manufacturing method of the present inventionSecond reference exampleWill be described with reference to FIG. 2, FIG. 3 and FIG. 2, FIG. 3 and FIG.Second reference exampleIt is sectional drawing which shows this manufacturing process. 2, 3, and 4, the configuration of the base 12 is omitted.
[0038]
First, the first conductive layer 50 is deposited on the base 12 (FIG. 2A). The first conductive layer 50 is shaped later and corresponds to the lower electrode 36 described above. In order to form the first conductive layer 50, IrO having a thickness of 0.1 μm is formed by sputtering.₂ Deposit layers.
[0039]
Next, an insulating layer 52 is deposited on the upper surface of the first conductive layer 50 (FIG. 2B). For this reason, a 0.2 μm thick insulating film (SiO 2₂ Film, SiN film, or SiON film) is formed by a CVD method.
[0040]
Subsequently, a hole 56 having a depth such that the upper surface of the first conductive layer 50 is exposed is formed in the capacitor region 54 of the insulating layer 52 (FIG. 2C). For this reason, the insulating layer 52 is perforated by a known photolithography method and dry etching method to partially expose the first conductive layer 50. The capacitance region 54 is defined at a position including the predetermined wiring 34 formed in the base 12. The inner wall surface of the hole 56 is substantially perpendicular to the upper surface of the base 12. The insulating layer in which the hole 56 is formed is represented by reference numeral 52a.
[0041]
Next, the ferroelectric layer 58 is embedded in the hole 56 of the insulating layer 52a (FIG. 3A). As a ferroelectric material, SBT (SrBi₂ Ta₂ O₉ ) Is used. This SBT is applied on the insulating layer 52a by a sol-gel method or the like so that the inside of the hole 56 is sufficiently filled with the SBT. Therefore, when the hole 56 is formed, it is important that the ratio of the diameter of the hole 56 to the depth of the hole 56 is 1 or more. The SBT film (ferroelectric layer 58) formed by the sol-gel method is subjected to heat treatment in oxygen at a temperature of 450 ° C. for one hour as temporary baking. Since the inner wall surface of the hole 56 is perpendicular to the upper surface of the base 12, the pattern edge of the ferroelectric layer 58 is also perpendicular to the upper surface of the base 12.
[0042]
Next, the upper portion of the ferroelectric layer 58 is polished, so that the height of the upper surface of the ferroelectric layer 58 matches the height of the upper surface of the insulating layer 52a (FIG. 3B). In the state where the previous step is completed, the ferroelectric layer 58 is deposited on the upper surface of the insulating layer 52a. Therefore, this extra portion of the ferroelectric layer 58 is removed by chemical mechanical polishing (CMP). Remove with. When polishing is performed by CMP until the upper surface of the insulating layer 52a is exposed, the height of the upper surface of the ferroelectric layer 58a remaining in the hole 56 matches the height of the upper surface of the insulating layer 52a.
[0043]
This processing method by CMP is an application of the damascene process used in the LSI wiring process. As an example of CMP, an ammonia-based slurry containing silica fine particles is used as a slurry.
[0044]
Thereafter, as the main firing of the SBT film (ferroelectric layer 58a), heat treatment is performed in oxygen at a temperature of, for example, 750 ° C. for 1 hour.
[0045]
Next, a second conductive layer is deposited on the top surfaces of the insulating layer 52a and the ferroelectric layer 58a (FIG. 3C). As the second conductive layer, IrO₂ The layer 60 and the TiN layer 62 are formed by sputtering in this order. IrO₂ The film thickness of the layer 60 is 0.1 μm. Since the TiN layer 62 is used as an etching mask in a later process, its film thickness is determined from the etching conditions. In this example, the thickness is set to 0.2 μm.
[0046]
Next, a mask 64 having a predetermined pattern is formed at a position including the capacitor region 54 on the upper surface of the second conductive layer (FIG. 4B). For this reason, SiO₂ An insulating film 66 made of a film, SiN film or SiON film is formed on the upper surface of the TiN layer 62 (FIG. 4A). The insulating film 66 is formed by a CVD method to a thickness of 0.5 μm. Then, the insulating film 66 is patterned by a known photolithography method and dry etching method to form a mask 64 (FIG. 4B). When the pattern of the mask 64 is projected on the lower layer side, the ferroelectric layer 58a is included in the projected pattern.
[0047]
Then, the pattern of the mask 64 is applied to the second conductive layer (IrO₂ The layer 60, the TiN layer 62), the insulating layer 52a, and the first conductive layer 50 are transferred (FIG. 4C). For this reason, first, the second conductive layer is etched using the mask 64. Here, Cl₂ And O₂ A dry etching method using a mixed gas is used. As a result, IrO₂ The layer 60a and the TiN layer 62a are processed, and the laminated structure is used as the above-described upper electrode.
[0048]
Subsequently, using the upper electrode as an etching mask, the insulating layer 52a is processed by a dry etching method using an F-based gas. The patterned edge (side surface) of the processed insulating layer 52 b is substantially perpendicular to the upper surface of the base 12. This insulating layer 52b functions as a side wall of the ferroelectric layer 58a.
[0049]
Next, using the upper electrode as an etching mask, Cl₂ And O₂ The first conductive layer 50 is processed by the dry etching method using the mixed gas. The processed first conductive layer 50a functions as a lower electrode. After processing the lower electrode, the TiN layer 62a of the upper electrode may be left, or may be removed by wet etching with ammonia water.
[0050]
Incidentally, the SBT film formed by the sol-gel method or the like is usually subjected to a low temperature treatment called temporary firing and a high temperature treatment called main firing to induce ferroelectric characteristics. In this embodiment, temporary baking is performed immediately after applying SBT by a sol-gel method or the like, and main baking is performed after polishing by CMP. However, the main baking may be performed continuously after the temporary baking.
[0051]
  As explained above, thisSecond reference exampleAccording to this manufacturing method, the shape of the pattern edge of the ferroelectric layer 58a is determined by the shape of the hole 56 formed in the insulating layer 52a. The inner wall surface of the hole 56 can be easily processed perpendicularly to the substrate by a known processing technique. Therefore, the pattern edge of the ferroelectric layer 58a can also be perpendicular to the substrate. Also, the pattern edge of the insulating layer 52b can be easily processed perpendicularly to the substrate by a known processing technique. Therefore, the area occupied by the capacitive element is reduced, and miniaturization is possible.
[0052]
  In addition, thisSecond reference exampleIn this manufacturing method, since the processing of the ferroelectric material by dry etching or milling is unnecessary, the pattern edge is not damaged. Therefore, the capacitor element can be miniaturized.
[0053]
  [First embodiment]
  next,First embodimentNow, a method for manufacturing a semiconductor memory device according to the present invention will be described with reference to FIGS. FIG. 5, FIG. 6 and FIG.First embodimentIt is sectional drawing which shows this manufacturing process.First embodimentThe structure of the semiconductor memory device created by the manufacturing method ofFirst reference exampleThis is the configuration of the semiconductor memory device described in 1. above. The same components as those shown in FIGS. 1 to 4 will be described with the same reference numerals. In FIGS. 5, 6, and 7, the configuration of the base 12 is omitted.
[0054]
First, the first conductive layer 50 is deposited on the base 12 (FIG. 5A). The first conductive layer 50 is shaped later and corresponds to the lower electrode. In order to form the first conductive layer 50, IrO having a thickness of 0.1 μm is formed by sputtering.₂ Deposit layers.
[0055]
Next, an insulating layer 52 is deposited on the upper surface of the first conductive layer 50 (FIG. 5B). For this reason, a 0.2 μm thick insulating film (SiO 2₂ Film, SiN film, or SiON film) is formed by a CVD method.
[0056]
Next, a stopper layer 68 is deposited on the upper surface of the insulating layer 52 (FIG. 5B). For this reason, IrOm with a thickness of 0.05 μm₂ A layer is formed by sputtering.
[0057]
Subsequently, a hole 74 having a depth such that the upper surface of the first conductive layer 50 is exposed is formed in the capacitor region 54 of the stopper layer 68 and the insulating layer 52 (FIG. 6A).
[0058]
For this reason, the upper surface of the stopper layer 68 is made of SiO.₂ An insulating film 70 made of a film, SiN film or SiON film is formed to a thickness of 0.1 μm by CVD (FIG. 5B). Then, an opening is formed at a position corresponding to the capacitance region 54 of the insulating film 70 by a known photolithography method and dry etching, and the upper surface of the stopper layer 68 is exposed. The capacitance region 54 is defined at a position including the predetermined wiring 34 formed in the base 12.
[0059]
Subsequently, using the pattern of the remaining insulating film 70a as a mask, Cl₂ And O₂ The stopper layer 68 is processed by the dry etching method using the mixed gas. As a result, an opening 72 is formed at a position corresponding to the capacitor region 54 of the remaining stopper layer 68a and insulating film 70a (FIG. 5C).
[0060]
Next, using the remaining stopper layer 68a and insulating film 70a as a mask, a hole is formed in the insulating layer 52 by a known dry etching method, and the first conductive layer 50 is partially exposed. As a result, a hole 74 is formed in the stopper layer 68a and the insulating layer 52a (FIG. 6A). The inner wall surface of the hole 74 is substantially perpendicular to the upper surface of the base 12.
[0061]
Next, the ferroelectric layer 58 is embedded in the holes 74 of the stopper layer 68a and the insulating layer 52a (FIG. 6B). SBT is used as the ferroelectric material. This SBT is applied onto the insulating film 70a by a sol-gel method or the like, so that the inside of the hole 74 is sufficiently filled with SBT. For this purpose, when the hole 74 is formed, it is important that the ratio of the diameter (diameter) of the hole 74 to the depth of the hole 74 is 1 or more. The SBT film (ferroelectric layer 58) formed by the sol-gel method is subjected to heat treatment in oxygen at a temperature of 450 ° C. for one hour as temporary baking. Since the inner wall surface of the hole 74 is perpendicular to the top surface of the base 12, the pattern edge of the ferroelectric layer 58 is also perpendicular to the top surface of the base 12.
[0062]
Next, the upper part of the ferroelectric layer 58 is polished, and the height of the upper surface of the ferroelectric layer 58 is made to coincide with the height of the upper surface of the stopper layer 68a (FIG. 6C). In the state where the previous step is completed, the ferroelectric layer 58 is deposited on the upper surface of the insulating film 70a. This extra portion of the ferroelectric layer 58 and the insulating film 70a are removed by CMP. At this time, the stopper layer 68a functions as a processing stopper in the CMP process. When polishing is performed by CMP, the polishing automatically stops at a position where the upper surface of the stopper layer 68a is exposed. Therefore, the height of the upper surface of the ferroelectric layer 58a remaining in the hole 74 coincides with the height of the upper surface of the stopper layer 68a. The CMP step here is performed using an ammonia-based one containing silica fine particles as a slurry.
[0063]
Thereafter, as the main firing of the SBT film (ferroelectric layer 58a), heat treatment is performed in oxygen at a temperature of, for example, 750 ° C. for 1 hour.
[0064]
Next, a second conductive layer is deposited on the upper surfaces of the stopper layer 68a and the ferroelectric layer 58a (FIG. 7A). As the second conductive layer, IrO₂ The layer 60 and the TiN layer 62 are formed by sputtering in this order. IrO₂ The film thickness of the layer 60 is 0.1 μm. Since the TiN layer 62 is used as an etching mask in a later process, its film thickness is determined from the etching conditions. In this example, the thickness is set to 0.2 μm.
[0065]
Next, a mask 64 having a predetermined pattern is formed at a position including the capacitor region 54 on the upper surface of the second conductive layer (FIG. 7B). For this reason, SiO₂ An insulating film 66 made of a film, SiN film or SiON film is formed on the upper surface of the TiN layer 62. The insulating film 66 is formed by a CVD method to a thickness of 0.5 μm. Then, the insulating film 66 is patterned by a known photolithography method and dry etching method to form a mask 64. When the pattern of the mask 64 is projected onto the lower layer, the ferroelectric layer 58a is included in the projected pattern.
[0066]
Then, the pattern of the mask 64 is applied to the second conductive layer (IrO₂ Layer 60, TiN layer 62), stopper layer 68a, insulating layer 52a, and first conductive layer 50 (FIG. 7C). For this reason, first, the second conductive layer and the stopper layer 68 a are etched using the mask 64. Here, Cl₂ And O₂ A dry etching method using a mixed gas is used. As a result, the stopper layer (IrO₂ Layer) 68b, IrO₂ The layer 60a and the TiN layer 62a are processed to obtain a laminated structure corresponding to the upper electrode.
[0067]
  Subsequently, using the upper electrode as an etching mask, the insulating layer 52a is processed by a dry etching method using an F-based gas. The patterned edge (side surface) of the processed insulating layer 52 b is substantially perpendicular to the upper surface of the base 12. This insulating layer 52bAnd stopper layer 68bFunctions as a sidewall of the ferroelectric layer 58a.
[0068]
Next, using the upper electrode as an etching mask, Cl₂ And O₂ The first conductive layer 50 is processed by the dry etching method using the mixed gas. The processed first conductive layer 50a functions as a lower electrode. After processing the lower electrode, the TiN layer 62a of the upper electrode may be left, or may be removed by wet etching with ammonia water.
[0069]
Incidentally, the SBT film formed by the sol-gel method or the like is usually subjected to a low temperature treatment called temporary firing and a high temperature treatment called main firing to induce ferroelectric characteristics. In this embodiment, temporary baking is performed immediately after applying SBT by a sol-gel method or the like, and main baking is performed after polishing by CMP. However, the main baking may be continuously performed after the temporary baking.
[0070]
As described above, according to the manufacturing method of this embodiment, the shape of the pattern edge of the ferroelectric layer 58a is determined by the shape of the hole 74 formed in the insulating layer 52a and the stopper layer 68a. The inner wall surface of the hole 74 can be easily processed perpendicularly to the substrate by a known processing technique. Therefore, the pattern edge of the ferroelectric layer 58a can also be perpendicular to the substrate. Also, the pattern edge of the insulating layer 52b can be easily processed perpendicularly to the substrate by a known processing technique. Therefore, the area occupied by the capacitive element is reduced, and miniaturization is possible.
[0071]
Further, in the manufacturing method of this embodiment, the processing of the ferroelectric material by dry etching or milling is unnecessary, so that the pattern edge is not damaged. Therefore, the capacitor element can be miniaturized.
[0072]
Also, as a processing stopper for CMP of a ferroelectric material, IrO having a slow polishing rate is used.₂ No worries about excessive polishing.
[0073]
The stopper layer 68b and IrO as the second conductive layer₂ Layer 60a is formed of the same material. Since the upper electrode is composed of the stopper layer 68b and the second conductive layer, the area of the upper electrode becomes larger. Therefore, a uniform electric field is easily applied to the ferroelectric layer 58a, and the characteristics are stabilized.
[0074]
The material of the stopper layer 68 (68a, 68b) is IrO₂ The conductive material may be any conductive material that has a low polishing rate and hardly reacts with the ferroelectric material when the ferroelectric layer is processed by the chemical mechanical polishing method. For example, the stopper layer may be an Ir layer, IrO₂ Layer, Pt layer, Ru layer, RuO₂ Layer, La_0.5 Sr_0.5 CoO_Three Layer, SrRuO_Three Layer and YBa₂ Cu_Three O_x (X is a positive integer) A single-layer thin film of any one layer selected from the layers, or a laminated thin film of a plurality of layers arbitrarily selected from these layers may be used.
[0075]
【The invention's effect】
According to the semiconductor memory device of the present invention, the capacitor element in which the lower electrode, the ferroelectric film, and the upper electrode are sequentially laminated on the base is provided, and the side surfaces of the lower electrode and the upper electrode are formed from the side surfaces of the ferroelectric film. The side surface of the ferroelectric film, which is located outside, is covered with a side wall having a side surface substantially perpendicular to the upper surface of the base, and the side surface of the side wall and the side surfaces of the lower electrode and the upper electrode are In substantially the same position.
[0076]
Thus, the side surface of the side wall and the side surfaces of the lower electrode and the upper electrode constitute the side surface of the capacitive element. Since the side surface of the side wall is substantially perpendicular to the upper surface of the base, the area occupied by the capacitor element is reduced as compared with the conventional case, and the degree of integration is improved. Therefore, it is suitable for miniaturization.
[0077]
Further, since the area of the upper electrode and the lower electrode is larger than the area of the ferroelectric film, the electric field applied to the ferroelectric film tends to be uniform.
[Brief description of the drawings]
[Figure 1]First reference example1 is a diagram showing a configuration of a semiconductor memory device of FIG.
[Figure 2]Second reference exampleIt is a figure which shows the manufacturing process of this.
FIG. 3 continues from FIG.Second reference exampleIt is a figure which shows the manufacturing process of this.
FIG. 4 continues from FIG.Second reference exampleIt is a figure which shows the manufacturing process of this.
[Figure 5]First embodimentIt is a figure which shows the manufacturing process of this.
FIG. 6 continues to FIG.First embodimentIt is a figure which shows the manufacturing process of this.
FIG. 7 continues from FIG.First embodimentIt is a figure which shows the manufacturing process of this.
[Explanation of symbols]
  10: Capacitance element 12: Base
  12a: upper surface 14, 24: interlayer insulating film
  16, 34, 48: Wiring
  18: Surface protective layer 20: Si substrate
  22: p⁻ -Si layer 26: oxide film for element isolation
  28, 30: n⁺ -Si layer
  32: Gate electrode 36: Lower electrode
  38: Ferroelectric film 40: Upper electrode
  42, 60, 60a: IrO₂ layer
  44, 62, 62a: TiN layer
  36a, 38a, 40a, 46a: side
  46: Side wall 50, 50a: First conductive layer
  52, 52a, 52b: Insulating layer
  54: Capacity region 56, 74: Hole
  58, 58a: Ferroelectric layer
  64: Mask 66, 70, 70a: Insulating film
  68, 68a, 68b: stopper layer
  72: Opening

Claims (5)

Depositing a first conductive layer on a base;
Depositing an insulating layer on the top surface of the first conductive layer;
Depositing a stopper layer on the top surface of the insulating layer;
Forming a hole having a depth such that an upper surface of the first conductive layer is exposed in a capacitance region of the stopper layer and the insulating layer;
Embedding a ferroelectric layer in the holes of the stopper layer and the insulating layer;
Polishing the upper portion of the ferroelectric layer and matching the height of the upper surface of the ferroelectric layer to the height of the upper surface of the stopper layer;
Depositing a second conductive layer on top of the stopper layer and the ferroelectric layer;
Forming a mask having a predetermined pattern at a position including the capacitance region on the upper surface of the second conductive layer;
And transferring the pattern of the mask to the second conductive layer, the stopper layer, the insulating layer, and the first conductive layer. The method of manufacturing a semiconductor memory device according to claim 1 ,
A method of manufacturing a semiconductor memory device, wherein the stopper layer and the second conductive layer are formed of the same material. In the manufacturing method of the semiconductor memory device according to claim 2 ,
The stopper layer includes an Ir layer, an IrO ₂ layer, a Pt layer, a Ru layer, a RuO ₂ layer, a La _0.5 Sr _0.5 CoO ₃ layer, a SrRuO ₃ layer, and a YBa ₂ Cu ₃ O _x (x is a positive integer) (1) A method for manufacturing a semiconductor memory device, comprising a single-layer thin film of any one layer selected from the layers, or a laminated thin film of a plurality of layers arbitrarily selected from these layers. The method of manufacturing a semiconductor memory device according to claim 1 ,
A method of manufacturing a semiconductor memory device, wherein the step of polishing the upper portion of the ferroelectric layer is performed by a chemical mechanical polishing method. The method of manufacturing a semiconductor memory device according to claim 1 ,
A method of manufacturing a semiconductor memory device, wherein a ratio of a diameter of the hole to a depth of the hole is 1 or more.

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