JP4282895B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor integrated circuit device such as a semiconductor memory.
[0002]
[Prior art]
FIG. 6 shows a general layout of the semiconductor memory 1. The memory 1 has a rectangular shape having a short side X and a long side Y, and a memory cell region 2 is provided on the inside thereof. The memory cell region 2 occupies about 80% of the entire area. Reference numerals 3A and 3B denote control areas in which circuits for controlling memory cells are provided. Outside the control areas 3A and 3B, there are input / output areas 4A and 4B. In the input / output areas 4A and 4B, pads 5 and transistors P and N are provided along the short side X.
[0003]
The input / output regions 4A and 4B are provided with an output circuit and an input circuit. Among them, the output circuit has a P-channel MOS transistor and an N channel between the power supply line VDD and the reference potential point 8, as shown in FIG. The channel MOS transistors N are connected as shown in the figure, and their drains are connected to the pad PAD. On the other hand, the pad PAD is connected to the gates of the P channel MOS transistor P and the N channel MOS transistor N as shown in FIG. 5, and the drain is connected to the buffer 9 in the control regions 3A and 3B.
[0004]
FIG. 7 shows the arrangement of pads and MOS transistors in the input / output circuit in FIG. 6. For example, P2 and N2 arranged on the left and right of the pad PAD2 are the P channels of the circuit shown in FIG. A MOS transistor and an N-channel MOS transistor are shown. Thus, the pads PAD2, P2, and N2 constitute one set. Similarly, PAD3, P3, and N3 form one set.
[0005]
In this case, in order to avoid latch-up (two parasitic PNP and NPN bipolar transistors formed in an IC using a CMOS transistor are in a thyristor operation state), a P-channel MOS transistor and an N-channel MOS transistor Are separated from each other and are arranged so that adjacent transistors of the same type are adjacent (P1 and P2, N2 and N3, P3 and N3).
[0006]
[Problems to be solved by the invention]
In the conventional memory layout structure, the integrated circuit density is determined by the size L in the X direction for each output circuit (or input circuit) shown in FIG. 7, and an integrated circuit density higher than that cannot be realized. . For this reason, the size of the main part of the chip (particularly the size in the X direction) cannot be reduced despite the fact that the size of the main part of the chip can be reduced as in a small-capacity memory using a fine process. There was a problem that the miniaturization could not be sufficiently achieved.
[0007]
The same is true for a multi-output memory having a larger number of pads than the chip size. Such a problem stems from the fact that although the technology for reducing the size of transistor elements has been advanced, the size of the pad itself cannot necessarily be reduced due to the problem of bonding of connection lines. Incidentally, the size of the pad is 110 μm × 110 μm.
[0008]
It is an object of the present invention to provide a semiconductor integrated circuit device in which the entire chip is miniaturized by devising the arrangement structure of pads and transistors of an input / output circuit.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, a memory cell region formed so as to form a rectangle having a long side and a short side, a short side of the memory cell region, and outside the memory cell region, A pad arranged along the short side so that the outer edge of the short side of the memory cell region and the end of the pad substantially coincide with each other, and a P-channel MOS transistor and an N-channel MOS transistor connected to the pad A plurality of sets of transistors, wherein the set of transistors is arranged between the memory cell region and the pad, and the set of transistors includes a P-channel MOS transistor, and an N-channel transistor. The MOS transistors are arranged in a row with the order reversed so that two MOS transistors are arranged adjacent to each other.
[0011]
Further, according to the present invention, the pair of transistors is arranged such that the P-channel MOS transistor and the N-channel MOS transistor are arranged along the short side direction between the outer side and the inner side across the pad row. Are arranged so as to be two columns of a P channel MOS transistor column and an N channel MOS transistor column .
[0012]
[Action]
According to such a configuration, the arrangement area of the input / output circuit is increased in the long side direction of the chip, and accordingly, the size in the short side direction can be reduced, and the entire semiconductor integrated circuit can be made a small chip. .
[0013]
【Example】
Embodiments shown in the drawings will be described below. In FIG. 1 in which the present invention is implemented, reference numeral 1 denotes an SRAM semiconductor memory, and reference numeral 2 denotes a memory cell region occupying an area of about 80% of the whole. A control area 3 is provided with a control circuit for controlling the memory cells. Reference numeral 4 denotes an input / output circuit area. In this input / output circuit area, pads PAD1, PAD2, PAD3,... Are arranged in a line along the short side X, and MOS transistors forming a pair with these pads are arranged inside. Is arranged.
[0014]
That is, a P-channel MOS transistor P1 that forms a pair with the pad PAD1 is disposed on the left end, and an N-channel MOS transistor N1 is disposed on the right side thereof. An N-channel MOS transistor N2 that forms a pair with the pad PAD2 is disposed adjacent to N1, and a P-channel MOS transistor P2 is disposed on the right side thereof. In this way, two N-channel MOS transistors and two P-channel MOS transistors are arranged adjacent to each other. The reason why the same conductivity type is adjacent is to prevent latch-up as much as possible.
[0015]
FIG. 2 shows a variation of the arrangement of pads and MOS transistors. (A) shows that the transistors P1 to P3 and N1 to N3 in FIG. 1 are vertically long, whereas the transistors P1 to P3 and N1 to N3 are horizontally long. It has become. The transistors are arranged in two rows in the Y direction. That is, N-channel MOS transistors N1, N2, and N3 are arranged closer to the row of pads PAD1, PAD2, and PAD3, and P-channel MOS transistors P1, P2, and P3 are arranged closer to the row. A pair of a pad and a transistor exists corresponding to the Y direction. For example, PAD1, N1, and P1 are arranged in the Y direction.
[0016]
Next, (b) provides a first pad PAD1 and a second pad PAD2 on one diagonal of the virtual rectangle, and N-channel MOS transistors N1, N2 and P-channel MOS transistors P1, P2 on the other diagonal. Provided. In this case, N1 and P1 are arranged at positions close to the first pad PAD1, and N2 and P2 are arranged at positions close to the second pad PAD2. The form (b) is similarly applied to the arrangement of third and fourth pads (not shown) and the corresponding MOS transistors.
[0017]
In (c), N-channel MOS transistors N1, N2, and N3 are arranged on the outside of the chip across the rows of pads PAD1, PAD2, and PAD3, and P-channel MOS transistors P1, P2, and P3 are arranged on the inside. It has become a shape.
[0018]
In each of the four modes shown in FIGS. 1 and 2A, 2B, and C, the size of the short side X is reduced. Accordingly, the chip size of the semiconductor memory 1 is reduced. That is, even if the size of the long side Y is slightly increased, the entire chip is reduced as the short side X is shortened. In these embodiments, the positions of the P channel MOS transistor and the N channel MOS transistor may be interchanged.
[0019]
FIG. 3 conceptually shows this, (a) is a conventional example, and (b) is a case according to the present invention. According to the present invention, the shaded portion 30 in (a) decreases and the shaded portion 31 in (b) increases, but it can be seen that the decrease amount 30 is larger than the increase amount 31. Incidentally, by forming the transistors of the input / output circuit in the control region 3, it is not necessary to increase the long side. In that case, the size can be further reduced. In this case, only transistors can be formed in the control region 3, and pads cannot be formed. Accordingly, this embodiment can be implemented in FIGS. 1 and 2 (a) and (c). In (c), a transistor row located inside the pad may be formed in the control region 3.
[0020]
The advantages and disadvantages other than the common advantage that the chip size is reduced in the four modes of FIGS. 1 and 2 (a), (b), and (c) are first described in terms of preventing latch-up. C) is excellent. Next, FIG. 1 and FIG. 2 (a) are preferable regarding the point which bonds a connection line with respect to a pad. Next, (c) is the order.
[0021]
【The invention's effect】
As described above, according to the present invention, it is possible to reduce the size of the semiconductor integrated circuit device in the short side direction, thereby reducing the overall size.
[Brief description of the drawings]
FIG. 1 is a diagram showing a layout pattern of essential parts of a semiconductor memory embodying the present invention.
FIG. 2 is a diagram showing a layout pattern of main parts according to another embodiment of the present invention.
FIG. 3 is a diagram for explaining the effect of reducing the chip size according to the present invention.
FIG. 4 is a circuit diagram showing an input circuit portion of an input / output circuit.
FIG. 5 is a circuit diagram showing an output circuit portion of an input / output circuit.
FIG. 6 is a view showing a layout pattern of a conventional semiconductor memory.
FIG. 7 is a diagram showing the configuration of the main part.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor memory 2 Memory cell 3 Control area 4 Input / output area X Short side Y Long side PAD1, PAD2, PAD3 Pad P1, P2, P3 P channel MOS transistor N1, N2, N3 N channel MOS transistor

Claims (1)

A memory cell region formed so as to form a rectangle having a long side and a short side; and a short side of the memory cell region, and an outer edge of the short side of the memory cell region and a pad outside the memory cell region A pad arranged along the short side so as to substantially coincide with the end of the transistor, and a plurality of transistors each including a P-channel MOS transistor and an N-channel MOS transistor connected to the pad. And
The transistors forming the set are arranged between the memory cell region and the pad,
Transistors forming the said set, the semiconductor integrated circuit, characterized in that are arranged and P-channel MOS transistor, in a row by inverting one set at a time order so that the N-channel MOS transistor arranged adjacent twos apparatus.

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