JP4284205B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit including a memory cell array.

In recent years, with the advancement of semiconductor technology, the era of system LSIs in which the entire system is mounted on a single chip has come. Most system LSIs are equipped with many memory macros each having a memory cell array. However, as the power supply voltage decreases, the threshold voltage of the transistors constituting the memory cell decreases, and the source-drain leakage current ( In the following, an increase in simply the leakage current has become remarkable. Since the standby current increases due to an increase in the leakage current, various companies are developing technologies for reducing the leakage current during standby. Attempts have also been made to improve the charge retention characteristics of DRAM (dynamic random-access memory) cells when the leakage current increases, such as the semiconductor memory device disclosed in Patent Document 1.
Japanese Patent Laid-Open No. 7-307091

  However, in a memory macro in which a large number of memory cells are connected to one bit line, when the leakage current from the memory cell increases, the potential of the bit line changes from the precharge level. Then, the change in the potential of the bit line due to the leak current becomes larger than the change in the potential of the bit line due to the read current from the original memory cell, and reading of data stored in the memory cell may fail. It becomes a problem. In particular, this is likely to occur when data stored in a plurality of memory cells connected to the same bit line is biased to one of two values.

  An object of the present invention is to stably read data from a memory cell without error in a semiconductor integrated circuit in which a large number of memory cells are connected to the same bit line.

In order to solve the above-mentioned problems, the means of the invention of claim 1 is a semiconductor integrated circuit comprising a plurality of bit lines, a plurality of word lines intersecting with these bit lines, and any one of the bit lines and the word A plurality of memory macros each having a memory cell array in which a plurality of memory cells respectively connected to any one of the lines are arranged in a matrix, and the first and second memory macros are formed on the same substrate, A main power supply circuit block that generates and outputs a voltage; and a plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros, wherein each of the plurality of local power supply circuit blocks includes the first negative voltage And generating a second negative voltage having an absolute value smaller than the first negative voltage and supplying the second negative voltage to a corresponding memory macro, The plurality of memory macros hold each of the plurality of word lines at the second negative voltage when not selected, and the second negative voltage is connected to one of the plurality of bit lines. The sum of leak currents between the unselected memory cell among the plurality of memory cells and the bit line is read from the selected memory cell among the plurality of memory cells connected to the bit line. Ri negative voltage der as smaller than the current, the plurality of local power supply circuit block, respectively, that the gate and drain a first negative voltage is applied, the source is the second negative voltage A PMOS transistor and a switching element connected between the drain and source of the PMOS transistor and conducting in response to a power-on signal indicating that the power is turned on are further updated. Those having.

  According to the first aspect of the present invention, the leakage current between the memory cell connected to the non-selected word line and the bit line can be reduced. Since the bit line potential after the precharge hardly changes due to the leak current, reading from the memory cell connected to the selected word line can be performed without error.

  In addition, since each memory macro has a local power supply circuit block, disturbances that occur in the output voltage from the main power supply circuit block when current is consumed by other memory macros are caused to unselected word lines in each memory macro. It can be prevented from transmitting. In addition, since the absolute value of the second negative voltage is set to a small value, power consumption in each memory macro can be suppressed, and occurrence of reliability problems can be suppressed.

Furthermore, after the power is turned on, the second negative voltage can be quickly set to a predetermined voltage.

In the invention of claim 2, in the semiconductor integrated circuit according to claim 1, wherein the plurality of local power supply circuit block, respectively, when the power-on signal is a logic low level signal, the power-on signal The level shifter further converts and outputs the first negative voltage signal, and the switch element is supplied with the first negative voltage as a substrate voltage and the gate is supplied with the output of the level shifter. The PMOS transistor is connected to the drain and source of the PMOS transistor, respectively.

According to a third aspect of the present invention , a semiconductor integrated circuit includes a plurality of bit lines, a plurality of word lines crossing the bit lines, and a plurality of bit lines connected to any one of the bit lines and the word lines. A plurality of memory macros each having a memory cell array in which memory cells are arranged in a matrix, and a main power supply circuit block that is formed on the same substrate as the plurality of memory macros and generates and outputs a first negative voltage And a plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros, wherein each of the plurality of local power supply circuit blocks is based on the first negative voltage and based on the first negative voltage. Generating a second negative voltage having a small absolute value and supplying the second negative voltage to the corresponding memory macro, wherein the plurality of memory macros Each of the write lines is held at the second negative voltage when not selected, and the second negative voltage is the one of the plurality of memory cells connected to one of the plurality of bit lines. A negative voltage such that the sum of leakage currents between the unselected memory cell and the bit line is smaller than the read current of the selected memory cell among the plurality of memory cells connected to the bit line , and the plurality of memory macros, respectively, further comprising a row decoder for driving the plurality of word lines, the local power supply circuit block further includes a mesh wire, and the corresponding memory macro row It is arranged adjacent to the decoder and applies the second negative voltage to the adjacent row decoder via the mesh-like wiring.

According to the invention of claim 3 , since the resistance of the mesh wiring is small, the second negative voltage can be supplied to the row decoder almost as it is.

According to a fourth aspect of the present invention , a semiconductor integrated circuit includes a plurality of bit lines, a plurality of word lines crossing the bit lines, and a plurality of bit lines connected to any one of the bit lines and the word lines. A plurality of memory macros each having a memory cell array in which memory cells are arranged in a matrix, and a main power supply circuit block that is formed on the same substrate as the plurality of memory macros and generates and outputs a first negative voltage And a plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros, wherein each of the plurality of local power supply circuit blocks is based on the first negative voltage and based on the first negative voltage. Generating a second negative voltage having a small absolute value and supplying the second negative voltage to the corresponding memory macro, wherein the plurality of memory macros Each of the write lines is held at the second negative voltage when not selected, and the second negative voltage is the one of the plurality of memory cells connected to one of the plurality of bit lines. A negative voltage such that the sum of leakage currents between the unselected memory cell and the bit line is smaller than the read current of the selected memory cell among the plurality of memory cells connected to the bit line Each of the plurality of memory macros further includes a row decoder for driving the plurality of word lines, and the row decoder decodes a predecode signal indicating which word line is selected, A decoding circuit for outputting the obtained decoding result; and when the decoding result is a low logic level signal, the second negative voltage is output, and the decoding result is high logic When the signal is a bell signal, the level shifter that outputs a power supply voltage is connected to one of the plurality of word lines, and the power supply voltage or the second negative voltage is determined according to the output of the level shifter. a drive circuit for outputting a word line, the repair signal indicating that a word line connected to the drive circuit is faulty is inputted, have a ground means for applying a ground voltage to the word line, wherein The level shifter is configured to cause the drive circuit to block a path for applying a voltage to the word line when the relief signal is input.

According to the fourth aspect of the present invention, since the drive circuit outputs the second negative voltage to the word line according to the decoding result, the leakage current between the memory cell and the bit line can be reduced. Further, the failed word line can be brought into a floating state from a power supply circuit that supplies a power supply voltage or a negative voltage, and can be fixed to the ground voltage.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the fourth aspect , the grounding means has a source to which a ground voltage is applied, a drain connected to a word line connected to the drive circuit, and a gate to the relief circuit. It is a high threshold transistor to which a signal is given.

According to the fifth aspect of the present invention, since the high threshold transistor is used, even if the relief signal is a signal of a normal logic level, the leakage current passing through the high threshold transistor can be suppressed.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the fourth aspect , the decode circuit includes a first NAND circuit that receives the predecode signal and obtains and outputs the decode result, The level shifter includes a first inverter that inverts and outputs the logic level of the output of the first NAND circuit, a second inverter that inverts and outputs the logic level of the relief signal, and the first inverter A second NAND circuit that calculates and outputs a logical product of the output of the second inverter and the output of the second inverter, and calculates a logical sum of the output of the first NAND circuit and the relief signal, and the result is low logic. And a NOR circuit that outputs the second negative voltage, the drive circuit is provided with the power supply voltage at the source and the drain at the level. A PMOS transistor to which one of a plurality of word lines is connected, an output of the second NAND circuit is applied to a gate, the second negative voltage is applied to a source, and the word line is connected to a drain. And an NMOS transistor whose gate is supplied with the output of the NOR circuit.

7. The semiconductor integrated circuit according to claim 7 , wherein a plurality of bit lines, a plurality of word lines crossing these bit lines, and a plurality of memory cells respectively connected to any one of the bit lines and the word lines are provided. A plurality of memory macros each having a memory cell array arranged in a matrix; a main power supply circuit block that is formed on the same substrate as the plurality of memory macros and generates and outputs a first negative voltage; A plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros, wherein each of the plurality of local power supply circuit blocks is supplied with the first negative voltage at its gate and drain, and its source is the second Is connected between the PMOS transistor drain and source, and the power is turned on. And a switch element that is turned on in response to a power-on signal indicating that the second negative voltage has a smaller absolute value than the first negative voltage based on the first negative voltage. The plurality of memory macros hold each of the plurality of word lines at the second negative voltage when not selected.

According to the seventh aspect of the present invention, the second negative voltage can be quickly set to a predetermined voltage after the power is turned on.

According to an eighth aspect of the present invention, in the semiconductor integrated circuit according to the seventh aspect , each of the plurality of local power supply circuit blocks receives the power-on signal when the power-on signal is a low logic level signal. The level shifter further converts and outputs the first negative voltage signal, and the switch element is supplied with the first negative voltage as a substrate voltage and the gate is supplied with the output of the level shifter. The PMOS transistor is connected to the drain and source of the PMOS transistor, respectively.

The semiconductor integrated circuit according to claim 9 , wherein a plurality of bit lines, a plurality of word lines intersecting these bit lines, and a plurality of memory cells respectively connected to any one of the bit lines and the word lines are provided. A plurality of memory macros each having a memory cell array arranged in a matrix; a main power supply circuit block that is formed on the same substrate as the plurality of memory macros and generates and outputs a first negative voltage; A plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros, each of the plurality of memory macros further comprising a row decoder for driving the plurality of word lines, and each of the plurality of word lines The non-selected voltage is held at the second negative voltage, and the plurality of local power supply circuit blocks are provided with mesh-like wiring. And the second negative voltage, which is arranged adjacent to the row decoder of the corresponding memory macro, has a smaller absolute value than the first negative voltage, based on the first negative voltage, The second negative voltage is applied to the adjacent row decoder via the mesh-like wiring.

According to the ninth aspect of the invention, since the resistance of the mesh-like wiring is small, the second negative voltage can be supplied to the row decoder almost as it is.

The semiconductor integrated circuit according to claim 10 includes a plurality of bit lines, a plurality of word lines intersecting these bit lines, and a plurality of memory cells respectively connected to any one of the bit lines and the word lines. A plurality of memory macros each having a memory cell array arranged in a matrix; a main power supply circuit block that is formed on the same substrate as the plurality of memory macros and generates and outputs a first negative voltage; A plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros, each of the plurality of local power supply circuit blocks being based on the first negative voltage and having an absolute value greater than the first negative voltage. Generates a second negative voltage having a small value, and supplies the second negative voltage to a corresponding memory macro, wherein the plurality of memory macros include the plurality of word lines. Each of the plurality of word lines is held at the second negative voltage when not selected, and the row decoder determines which word line is selected. A decoding circuit that decodes the predecode signal shown and outputs the obtained decoding result; and when the decoding result is a low logic level signal, the second negative voltage is output and the decoding result is a high logic level Is connected to one of the plurality of word lines, and the power supply voltage or the second negative voltage is supplied to the word in accordance with the output of the level shifter. When a driving circuit for outputting to a line and a relief signal indicating that a word line connected to the driving circuit is faulty are input, the word line is grounded. And a grounding means for applying said level shifter, when the repair signal is input is intended to cut off the path that gives voltage to the word line to the drive circuit.

According to the invention of claim 10 , since the drive circuit outputs the second negative voltage to the word line according to the decoding result, the leakage current between the memory cell and the bit line can be reduced. Further, the failed word line can be brought into a floating state from a power supply circuit that supplies a power supply voltage or a negative voltage, and can be fixed to the ground voltage.

According to an eleventh aspect of the present invention, in the semiconductor integrated circuit according to the tenth aspect , in the grounding means, a ground voltage is applied to a source, a word line connected to the drive circuit is connected to a drain, and the relief is connected to a gate. A high threshold transistor given a signal.

According to the eleventh aspect of the invention, since the high threshold transistor is used, even if the relief signal is a signal having a normal logic level, the leakage current passing through the high threshold transistor can be suppressed.

According to a twelfth aspect of the present invention, in the semiconductor integrated circuit according to the tenth aspect , the decode circuit includes a first NAND circuit that receives the predecode signal and obtains and outputs the decode result, The level shifter includes a first inverter that inverts and outputs the logic level of the output of the first NAND circuit, a second inverter that inverts and outputs the logic level of the relief signal, and the first inverter A second NAND circuit that calculates and outputs a logical product of the output of the second inverter and the output of the second inverter, and calculates a logical sum of the output of the first NAND circuit and the relief signal, and the result is low logic. And a NOR circuit that outputs the second negative voltage, the drive circuit is supplied with the power supply voltage at the source and connected to the drain. One of the plurality of word lines is connected, the PMOS transistor having the gate supplied with the output of the second NAND circuit, the second negative voltage applied to the source, and the word line connected to the drain And an NMOS transistor whose gate is supplied with the output of the NOR circuit.

  According to the present invention, it is possible to suppress a change in the bit line potential after precharging due to a leakage current, so that reading from the memory cell can be performed stably without error. Since it is not necessary to increase the access time in order to secure the operation margin, reading from the memory cell can be performed at high speed.

  In addition, since the operation margin can be increased, a semiconductor integrated circuit that is resistant to characteristic variations caused by process variations and power supply voltage variations can be obtained. Furthermore, since the operation margin can be increased, a semiconductor integrated circuit that operates at high speed can be easily designed, and the design period can be shortened.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. A semiconductor integrated circuit 100 of FIG. 1 is a system LSI, and includes a main power supply circuit block (MPC) 2, memory macros 10 and 30, and local power supply circuit blocks (LPC) 12 and 32. The memory macro 10 includes a memory cell array 14, a row decoder 15, a data input / output circuit 16, and a control circuit 17. Similarly, the memory macro 30 includes a memory cell array 34, a row decoder 35, a data input / output circuit 36, and a control circuit 37. The main power supply circuit block 2 is also called a main power supply macro, and the local power supply circuit blocks 12 and 32 are also called local power supply macros.

  The main power supply circuit block 2 generates the first negative voltage VBB1 from the supplied power supply and supplies it to the local power supply circuit blocks 12 and 32. Local power supply circuit blocks 12 and 32 are arranged adjacent to row decoders 15 and 35, respectively. The local power supply circuit blocks 12 and 32 generate a second negative voltage VBB2 from the supplied first negative voltage VBB1 and supply the second negative voltage VBB2 to the row decoders 15 and 35, respectively. The main power supply circuit block 2 is formed on the same substrate as the memory macros 10 and 30. In the following description, the memory macro 10 will be mainly described, but the memory macro 30 can be similarly described.

  FIG. 2 is a circuit diagram of the local power supply circuit block 12 of FIG. The local power supply circuit block 12 includes a P-channel MOS (metal oxide semiconductor) transistor (hereinafter referred to as a PMOS transistor) 122, an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) 124, and a level shifter 126. Yes. The PMOS transistor 122 has its gate and drain connected, and operates as a diode. A first negative voltage VBB1 (for example, -0.5V) is supplied to the drain of the PMOS transistor 122, and a second negative voltage VBB2 (for example, -0.1V) is generated at the source. The substrate voltage of the PMOS transistor 122 is equal to its source voltage. The NMOS transistor 124 constitutes a switch element.

  In the following, the high logic level and the low logic level are represented by “H” and “L”, respectively. Unless otherwise indicated, “H” is the power supply voltage VDD (for example, 5 V), and “L” is the ground voltage VSS (for example, for example). 0V).

  The level shifter 126 receives the power-on signal PON with the level “H” or “L” as an input signal, converts the input signal with the level “L” into a signal with the level being the first negative voltage VBB1, and outputs the signal. Then, the input signal whose level is “H” is output as it is. The output of the level shifter 126 is given to the gate of the NMOS transistor 124. First and second negative voltages VBB1 and VBB2 are applied to the source and drain of the NMOS transistor 124, respectively. The NMOS transistor 124 is supplied with a first negative voltage VBB1 as its substrate voltage.

  Here, the second negative voltage VBB2 is higher than the first negative voltage VBB1 by a voltage corresponding to the threshold value of the PMOS transistor 122. That is, the local power supply circuit block 12 generates the second negative voltage VBB2 having a smaller absolute value based on the first negative voltage VBB1.

  The second negative voltage VBB2 is used as a word line standby voltage in each of the memory macros 10 and 30. The reason why the absolute value of the second negative voltage VBB2 is set to a small value in this way is that it is not necessary to set the voltage when the word line is not selected (standby) to an unnecessarily low voltage. When the second negative voltage VBB2 is used, it is possible to suppress power consumption in each of the memory macros 10 and 30 and to prevent occurrence of a reliability problem.

  In this embodiment, since the local power supply circuit block 12 is disposed adjacent to the memory macro 10, the wiring for supplying a minute voltage (−0.1 V) is shortened to reduce noise from other wiring. The impact can be avoided. In addition, since each memory macro has a local power supply circuit block, the disturbance generated in the output voltage from the main power supply circuit block 2 when a current is consumed in another memory macro is held by a minute voltage. It is possible to prevent transmission to unselected word lines in each memory macro. Note that the memory macro 10 may include the local power supply circuit block 12.

  FIG. 3 is a graph showing the voltage in the local power supply circuit block 12 of FIG. In the following, the high potential and low potential of the logic level are represented by “H” and “L”, respectively, and “H” is the power supply voltage VDD and “L” is the ground voltage VSS unless otherwise indicated. The power-on signal PON is a signal that becomes “H” only for a predetermined period immediately after the time TL when the semiconductor integrated circuit 100 is powered on.

  If the local power supply circuit block 12 does not include the NMOS transistor 124, the second negative voltage decreases slowly like the voltage VBBN in FIG. 3, so that it reaches the target voltage (−0.1 V). It takes a long time. In contrast, in the local power supply circuit block 12, when the power-on signal PON becomes “H”, the NMOS transistor 124 is turned on, so that the second negative voltage VBB2 quickly reaches the target voltage and the setup is completed. Can do.

  Since it is necessary to apply the first negative voltage VBB1 as the substrate voltage to the NMOS transistor 124, it is desirable that the NMOS transistor 124 has a triple well structure in which the substrate can be separated for each transistor.

  FIG. 4 is a circuit diagram showing a configuration example of the row decoder 15 of FIG. FIG. 4 shows a circuit diagram of a portion for driving the word line WL0. The circuit in FIG. 4 includes a NAND circuit 152 as a decode circuit, a level shifter 154, a PMOS transistor 157, and an NMOS transistor 158. The PMOS transistor 157 and the NMOS transistor 158 constitute a drive circuit 156.

  The NAND circuit 152 is supplied with a predecode signal PDS output from a predecoder (not shown) and indicating which word line is selected. The NAND circuit 152 decodes the predecode signal PDS and outputs the obtained decoding result. That is, NAND circuit 152 sets the output level to “L” only when predecode signal PDS for selecting word line WL0 is input.

  The level shifter 154 has a well-known configuration, and receives an input signal at a level between the power supply voltage VDD and the ground voltage VSS as a level between the power supply voltage VDD and the second negative voltage VBB2. Is converted into a signal and output. For example, the level shifter 154 outputs the power supply voltage VDD when the input signal is “H”, and outputs the second negative voltage VBB2 when the input signal is “L”.

  The output of the level shifter 154 is given to the gates of the PMOS transistor 157 and the NMOS transistor 158. The source of the PMOS transistor 157 is supplied with the power supply voltage VDD, and the source of the NMOS transistor 158 is supplied with the second negative voltage VBB2. The drains of the PMOS transistor 157 and the NMOS transistor 158 are connected to the word line WL0. Therefore, the drive circuit 156 outputs the power supply voltage VDD to the word line WL0 when the word line WL0 is selected, and the second negative voltage VBB2 to the word line WL0 when the word line WL0 is not selected.

  FIG. 5 is a circuit diagram showing a configuration example of the memory cell array 14 of FIG. The memory cell array 14 has a plurality of bit lines, a plurality of word lines intersecting these bit lines, and memory cells arranged in a matrix. Each memory cell is connected to one of the bit lines and one of the word lines. FIG. 5 shows memory cells for one column of the memory cell array 14. These cells are SRAM (static random-access memory) cells.

  The memory cell array 14 includes memory cells 141, 142, 143,..., A precharge circuit 112, a sense amplifier 114, and paired bit lines BL and XBL for the column shown in FIG. . The memory cells 141 to 143 and the like are arranged in an array in the vicinity of the intersections between the word lines WL0, WL1, WL2,. The other columns are configured similarly to the circuit of FIG.

  The memory cell 141 includes NMOS transistors 131, 132, 135, 136 and PMOS transistors 133, 134. The NMOS transistors 131 and 132 operate as access transistors. The memory cells 142, 143 and the like are configured in the same manner as the memory cell 141.

  Here, the potential of the first node N1 that is a connection point between the NMOS transistors 131 and 135 is “L”, and the potential of the second node N2 that is a connection point between the NMOS transistors 132 and 136 is “H”. Suppose it is kept. Further, the potentials of the first and second nodes of the memory cell 142 are maintained at “H” and “L”, respectively, and the memory cells 143 other than the memory cell 141 have the same potential as the memory cell 142. Suppose you hold it. That is, a case where the memory cell 141 and other memory cells belonging to the same column store different values will be described.

  The precharge circuit 112 precharges the bit lines BL and XBL to “H”. For example, when data is read from the memory cell 141, the selected word line WL0 is set to “H” and the NMOS transistors 131 and 132 are turned on, so that charges are transferred from the bit line BL to the NMOS transistors 131 and 135. As a result, the potential of the bit line BL decreases. The sense amplifier 114 amplifies the potential difference between the bit line BL and the bit line XBL and outputs the amplified signal to the outside of the memory macro. Therefore, data stored in the memory cell 141 can be read.

  However, when the ground voltage VSS is applied to the unselected word line, the leakage current from the bit line may not be ignored. FIG. 6 is a graph showing changes in the bit line potential when the ground voltage VSS is applied to the unselected word lines.

  In this case, when precharge by the precharge circuit 112 is completed at time TP in FIG. 6, the bit line precharged to “H” to the unselected memory cells 142, 143,. Leakage current LI flows from XBL, and the potential of bit line XBL decreases. In particular, as shown in FIG. 5, when there are many memory cells that hold data different from the data held by the memory cell 141 to be read, the potential of the bit line XBL decreases quickly. Thereafter, when the word line WL0 becomes “H” in order to read the data of the selected memory cell 141, the read current RI flows into the memory cell 141, and the potential of the bit line BL starts to decrease.

  In order to correctly read data in the memory cell 141, the potential of the bit line BL must be lower than the potential of the bit line XBL at the time TS when the sense amplifier 114 starts operation. On the other hand, as shown in FIG. 6, when the potential of the bit line XBL is lower than the potential of the bit line BL at time TS, the data in the memory cell 141 cannot be read correctly. That is, the memory macro 10 malfunctions.

  In order to perform reading normally, it is necessary to delay the operation timing of the sense amplifier largely backward. However, this makes the access time for the memory cell longer.

  Therefore, in the semiconductor integrated circuit of FIG. 1, in order to reduce the leakage current LI, the row decoder 15 applies the second negative voltage VBB2 to the unselected word lines. Then, since the gate voltage of the access transistor of each memory cell connected to the bit lines BL and XBL becomes negative, the leakage current LI to the unselected memory cells is suppressed, and the bit lines BL and XBL caused by the leakage current LI are suppressed. The decrease in the potential is suppressed.

  FIG. 7 is a graph showing a change in the bit line potential when the second negative voltage VBB2 is applied to the unselected word line. As shown in FIG. 7, at the time TS when the sense amplifier 114 starts operation, the potential of the bit line BL is lower than the potential of the bit line XBL, so that the data in the memory cell 141 can be read correctly.

  As described above, the row decoder 15 has at least the leakage current LI between the unselected memory cells 142, 143 and the like among the memory cells in the same column connected to the bit lines BL, XBL and the bit line XBL. A negative voltage whose sum is smaller than the read current RI of the selected memory cell 141 is applied to the unselected word lines WL1, WL2, etc. connected to the unselected memory cells 142, 143, etc. .

  More specifically, the row decoder 15 selects a memory cell in the same column connected to the bit lines BL and XBL from the time TP at which precharging ends to the time TS at which the sense amplifier 114 starts operating. The change in the potential of the bit line XBL due to the leakage current LI between the memory cells 142, 143 and the like that have not been performed and the bit line XBL is more than the change in the potential of the bit line BL caused by the read current RI of the selected memory cell 141. A negative voltage that decreases is applied to the unselected word lines WL1, WL2, and the like.

  By reducing the gate voltage by 0.1 V, it is usually possible to reduce the leakage current of the transistor from one digit to a value that is one and a half digits smaller, so there is no need to supply a large negative voltage. Supplying a negative voltage having the minimum necessary magnitude is advantageous for reducing power consumption and maintaining reliability.

  FIG. 8 is a layout diagram showing the arrangement of the memory macro 10 and the local power supply circuit block 12 of FIG. Since the difference between the first negative voltage VBB1 and the second negative voltage VBB2 is small, the gate widths of the PMOS transistor 122 and the NMOS transistor 124 constituting the local power supply circuit block 12 must be large. In particular, the PMOS transistor 122 is required to have a large gate width. Therefore, as shown in FIG. 8, the shape of the local power supply circuit block 12 is rectangular.

  Normally, in the memory macro, the data input / output circuit 16 inputs / outputs data DATA, and the control signal INPUT and ADD signals are input to the control circuit 17. is there. For this reason, it is difficult to arrange the local power supply circuit block 12 adjacent to these circuits. Further, as described with reference to FIG. 4, the row decoder 15 uses a negative voltage. Therefore, the local power supply circuit block 12 is arranged so that the longer side is adjacent to the row decoder 15 of the memory macro 10.

  The local power supply circuit block 12 includes wirings 127 and 128. The PMOS transistor 122 and the NMOS transistor 124 are supplied with the first negative voltage VBB 1 via the wiring 127, and these transistors apply the second negative voltage VBB 2 to the row decoder 15 via the wiring 128. . As shown in FIG. 8, the wiring 128 is a mesh-shaped wiring and has a plurality of paths between the local power supply circuit block 12 and the row decoder 15. Since the resistance of the wiring 128 is small, almost no voltage is generated in the wiring 128 and the second negative voltage can be supplied to the row decoder 15 almost as it is. Since the local power supply circuit block 12 is arranged adjacent to the row decoder 15, such a mesh-like wiring 128 can be used.

  FIG. 9 is a circuit diagram showing another configuration example of the row decoder of FIG. FIG. 9 shows a circuit diagram of a portion for driving the word line WL0. The circuit of FIG. 9 includes a NAND circuit 252 as a decoding circuit, a level shifter 254, a driving circuit 256, and a high threshold transistor (NMOS transistor) 259 as a grounding means.

  The level shifter 254 includes inverters 282 and 283, a NAND circuit 284, and a NOR circuit 285. The drive circuit 256 includes a PMOS transistor 257 and an NMOS transistor 258. The NAND circuit 252 is similar to the NAND circuit 152 in FIG. The high threshold transistor 259 has the source supplied with the ground voltage VSS, the drain connected with the word line WL0, and the gate supplied with the relief signal SPE. The high threshold transistor 259 is a transistor that is turned on when the gate voltage is greater than or equal to a predetermined value that is greater than the source voltage.

  FIG. 10 is a circuit diagram showing a configuration of NOR circuit 285 of FIG. The NOR circuit 285 includes PMOS transistors 291 and 292 and NMOS transistors 293 and 294.

  Usually, an SRAM memory macro includes spare bit lines and uses memory cells connected to these bit lines as memory cells for defect relief. This is because the memory macro handles analog signals with bit lines. However, when a negative voltage is supplied to a non-selected word line as in the semiconductor integrated circuit of FIG. 1, the robustness of the word line is reduced, so that it is necessary to repair the defect of the word line.

  The row decoder shown in FIG. 9 is used to repair a defect of a word line. When a negative voltage is supplied to a non-selected word line, the word line is short-circuited with the adjacent word line, power supply wiring, bit line, etc., and if a failure occurs, a negative voltage is supplied to the local power supply circuit block etc. The burden on the power circuit increases. Then, problems such as an increase in power consumption and a lack of power circuit capability occur. Therefore, the row decoder shown in FIG. 9 disconnects the failed word line to be repaired from the negative voltage power line.

  In FIG. 9, the relief signal SPE is used to stop the circuit operation of the row decoder that drives the word line WL0 when the corresponding word line WL0 fails. First, a case where the relief signal SPE is “L” will be described. In this case, the level shifter 254 causes the drive circuit 256 to drive the word line WL0. That is, the level shifter 254 outputs “H” to the PMOS transistor 257 and the NMOS transistor 258 if the output of the NAND circuit 252 is “H”, and the PMOS transistor 257 if the output of the NAND circuit 252 is “L”. Is output with the ground voltage VSS and the NMOS transistor 258 with the second negative voltage VBB2.

  Next, a case where the relief signal SPE is “H” will be described. It is impossible to separate a failed word line from a wiring that applies a negative voltage simply by stopping the operation of the row decoder. Therefore, when a relief signal indicating that the word line WL0 is faulty is input, that is, when the relief signal SPE becomes “H”, the level shifter 254 provides a path for applying a voltage to the word line WL0 to the drive circuit 256. The word line WL0 that is cut off and short-circuited is brought into a floating state from the power supply circuit that supplies the power supply voltage VDD and the negative voltage VBB2. Specifically, the level shifter 254 provides the power supply voltage VDD to the PMOS transistor 257 and the negative voltage VBB2 to the NMOS transistor 258.

  At this time, the high threshold transistor 259 to which the relief signal SPE is input is turned on, so that the voltage of the word line WL0 is fixed to the ground voltage VSS. The reason for fixing the voltage of the word line is to prevent the memory cells connected to the failed word line from interfering with other memory cells when reading.

  In the row decoder of FIG. 9, since the high threshold transistor 259 is used, even if the relief signal SPE is a signal of a normal logic level at the voltage VDD or VSS, a leak current passing through the high threshold transistor 259 is not generated. Can be suppressed. For this reason, when the word line is not out of order, the leakage current from the word line to the local power supply circuit block 12 that supplies the second negative voltage VBB2 can be suppressed. When the high threshold transistor 259 is used, it is not necessary to convert the relief signal SPE so that the logic level becomes the power supply voltage VDD or the second negative voltage VBB2, so that a circuit for converting the signal level is not necessary. An increase in area can be avoided.

  While the second negative voltage VBB2 is supplied to the sources of the NMOS transistors 293 and 294 in FIG. 10, the level of the relief signal SPE and the node A becomes the voltage VDD or VSS, and the second negative voltage VBB2 It will not be. For this reason, a leakage current may flow through the NMOS transistors 293 and 294.

  The level of the node A is “L” only when the word line corresponding to the circuit of FIG. 9 is selected. In this case, if the relief signal SPE is “L”, a leak current flows through the NMOS transistors 293 and 294.

  However, the level of node A is “H” in most cases. In this case, since the NMOS transistor 294 is turned on, it is not necessary to consider the leakage current of the NMOS transistor 293. That is, in most cases, it is not necessary to consider the leakage current of the NMOS transistors 293 and 294.

  At the time of designing the semiconductor integrated circuit of FIG. 1, the compiler first generates layout data of the memory macros 10 and 30 based on the data in the design data library, and then layout data of the main power supply circuit block (main power supply macro) 2. Further, layout data of the local power supply circuit blocks (local power supply macro) 12 and 32 is generated in accordance with the configuration of the memory macro, and the generated data is output.

  That is, the compiler adjusts the height of the local power supply circuit blocks 12 and 32 to the height of the corresponding memory macros 10 and 30 (for example, the length of the side where the row decoders 15 and 35 are in contact). At this time, it is desirable for the compiler to make the widths of the local power supply circuit blocks 12 and 32 as narrow as possible while securing a necessary area.

  As described above, according to the semiconductor integrated circuit of FIG. 1, the fluctuation of the bit line potential due to the leak current can be prevented and the bit line potential at the time of reading data from the memory cell can be kept at a normal value. The resulting malfunction can be prevented. In addition, since it is not necessary to set a long access time to the memory cell in order to ensure an operation margin, it is possible to configure a memory macro that operates at high speed.

  In the above embodiment, the case where the SRAM cell is used as the memory cell has been described. However, the change in the bit line potential due to the leak current can be prevented similarly when the DRAM cell is used.

  As described above, the memory macro and the semiconductor integrated circuit according to the present invention can be stably read without error and are useful as a semiconductor integrated circuit including a memory cell array.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a local power supply circuit block in FIG. 1. It is a graph which shows the voltage in the local power supply circuit block of FIG. FIG. 2 is a circuit diagram illustrating a configuration example of a row decoder in FIG. 1. FIG. 3 is a circuit diagram illustrating a configuration example of a memory cell array in FIG. 2. It is a graph which shows the change of the bit line electric potential when giving a ground voltage to an unselected word line. It is a graph which shows the change of the bit line electric potential when giving a 2nd negative voltage to an unselected word line. FIG. 2 is a layout diagram illustrating an arrangement of memory macros and local power supply circuit blocks in FIG. 1. FIG. 7 is a circuit diagram illustrating another configuration example of the row decoder in FIG. 1. FIG. 10 is a circuit diagram showing a configuration of the NOR circuit of FIG. 9.

Explanation of symbols

2 Main power circuit block 10, 30 Memory macro 12, 32 Local power circuit block 14, 34 Memory cell array 15, 35 Row decoder 16, 36 Data input / output circuit 17, 37 Control circuit 100 Semiconductor integrated circuit 122 PMOS transistor 124 NMOS transistor ( Switch element)
126, 154, 254 Level shifter 152 NAND circuit (decode circuit)
156, 256 Drive circuit 252 First NAND circuit 257 PMOS transistor 258 NMOS transistor 259 High threshold transistor (grounding means)
282 First inverter 283 Second inverter 284 Second NAND circuit 285 NOR circuit VBB1 First negative voltage VBB2 Second negative voltage

Claims (12)

A memory cell array in which a plurality of bit lines, a plurality of word lines crossing these bit lines, and a plurality of memory cells respectively connected to any one of the bit lines and the word lines are arranged in a matrix A plurality of memory macros each having
A main power supply circuit block which is formed on the same substrate as the plurality of memory macros and generates and outputs a first negative voltage;
A plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros,
Each of the plurality of local power circuit blocks is
Based on the first negative voltage, a second negative voltage having a smaller absolute value than the first negative voltage is generated and given to a corresponding memory macro,
The plurality of memory macros are:
Each of the plurality of word lines is held at the second negative voltage when not selected.
The second negative voltage is
The sum of leakage currents between unselected memory cells among the plurality of memory cells connected to one of the plurality of bit lines and the bit line is the plurality of memories connected to the bit line. It is a negative voltage that is smaller than the read current of the selected memory cell among the cells,
Each of the plurality of local power circuit blocks is
A PMOS transistor whose gate and drain are supplied with the first negative voltage and whose source is the second negative voltage;
Which is connected between the drain and source of the PMOS transistor, a semiconductor integrated circuit, wherein the power supply is one that further comprises a switch element which conducts in response to the power-on signal indicating that it has been turned on. The semiconductor integrated circuit according to claim 1 ,
Each of the plurality of local power circuit blocks is
When the power-on signal is a low logic level signal, the power-on signal further includes a level shifter that converts the power-on signal into the first negative voltage signal and outputs the signal.
The switch element is
The first negative voltage is applied as the substrate voltage, the output of the level shifter is applied to the gate, and the drain and source of the PMOS transistor are connected to the source and drain, respectively. A semiconductor integrated circuit. A memory cell array in which a plurality of bit lines, a plurality of word lines crossing these bit lines, and a plurality of memory cells respectively connected to any one of the bit lines and the word lines are arranged in a matrix A plurality of memory macros each having
A main power supply circuit block which is formed on the same substrate as the plurality of memory macros and generates and outputs a first negative voltage;
A plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros,
Each of the plurality of local power circuit blocks is
Based on the first negative voltage, a second negative voltage having a smaller absolute value than the first negative voltage is generated and given to a corresponding memory macro,
The plurality of memory macros are:
Each of the plurality of word lines is held at the second negative voltage when not selected.
The second negative voltage is
The sum of leakage currents between unselected memory cells among the plurality of memory cells connected to one of the plurality of bit lines and the bit line is the plurality of memories connected to the bit line. It is a negative voltage that is smaller than the read current of the selected memory cell among the cells,
Each of the plurality of memory macros is
A row decoder for driving the plurality of word lines;
The local power supply circuit block includes:
It further comprises a mesh-like wiring, and is arranged adjacent to the row decoder of the corresponding memory macro, and applies the second negative voltage to the adjacent row decoder via the mesh-like wiring. A semiconductor integrated circuit characterized by the above. A memory cell array in which a plurality of bit lines, a plurality of word lines crossing these bit lines, and a plurality of memory cells respectively connected to any one of the bit lines and the word lines are arranged in a matrix A plurality of memory macros each having
A main power supply circuit block which is formed on the same substrate as the plurality of memory macros and generates and outputs a first negative voltage;
A plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros,
Each of the plurality of local power circuit blocks is
Based on the first negative voltage, a second negative voltage having a smaller absolute value than the first negative voltage is generated and given to a corresponding memory macro,
The plurality of memory macros are:
Each of the plurality of word lines is held at the second negative voltage when not selected.
The second negative voltage is
The sum of leakage currents between unselected memory cells among the plurality of memory cells connected to one of the plurality of bit lines and the bit line is the plurality of memories connected to the bit line. It is a negative voltage that is smaller than the read current of the selected memory cell among the cells,
Each of the plurality of memory macros is
A row decoder for driving the plurality of word lines;
The row decoder
A decoding circuit that decodes a predecode signal indicating which word line is selected, and outputs the obtained decoding result;
A level shifter that outputs the second negative voltage when the decoding result is a low logic level signal, and that outputs a power supply voltage when the decoding result is a high logic level signal;
A drive circuit connected to one of the plurality of word lines and outputting the power supply voltage or the second negative voltage to the word line in accordance with an output of the level shifter;
When repair signal indicating that a word line connected to the drive circuit is faulty is inputted, it has a ground means for applying a ground voltage to the word line,
The level shifter is
A semiconductor integrated circuit characterized in that, when the relief signal is input, the drive circuit blocks a path for applying a voltage to the word line. The semiconductor integrated circuit according to claim 4 ,
The grounding means is
A semiconductor integrated circuit, characterized in that a ground voltage is applied to a source, a word line connected to the drive circuit is connected to a drain, and the relief signal is applied to a gate. The semiconductor integrated circuit according to claim 4 ,
The decoding circuit includes:
A first NAND circuit that receives the predecode signal and obtains and outputs the decode result;
The level shifter is
A first inverter that inverts and outputs the logic level of the output of the first NAND circuit;
A second inverter that inverts and outputs the logic level of the relief signal;
A second NAND circuit for obtaining and outputting a logical product of the output of the first inverter and the output of the second inverter;
A logical sum of the output of the first NAND circuit and the relief signal, and when the result is a low logic level, the NOR circuit that outputs the second negative voltage;
The drive circuit is
A PMOS transistor having a source supplied with the power supply voltage, a drain connected to one of the plurality of word lines, and a gate supplied with the output of the second NAND circuit;
A semiconductor integrated circuit comprising: an NMOS transistor to which the second negative voltage is applied to a source, the word line is connected to a drain, and an output of the NOR circuit is applied to a gate. A memory cell array in which a plurality of bit lines, a plurality of word lines crossing these bit lines, and a plurality of memory cells respectively connected to any one of the bit lines and the word lines are arranged in a matrix A plurality of memory macros each having
A main power supply circuit block which is formed on the same substrate as the plurality of memory macros and generates and outputs a first negative voltage;
A plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros,
Each of the plurality of local power circuit blocks is
A PMOS transistor whose gate and drain are supplied with the first negative voltage and whose source is a second negative voltage;
A switching element connected between a drain and a source of the PMOS transistor and conducting in response to a power-on signal indicating that the power is turned on;
Based on the first negative voltage, the second negative voltage having a smaller absolute value than the first negative voltage is generated and given to the corresponding memory macro,
The plurality of memory macros are:
Each of the plurality of word lines is held at the second negative voltage when it is not selected. The semiconductor integrated circuit according to claim 7 ,
Each of the plurality of local power circuit blocks is
When the power-on signal is a low logic level signal, the power-on signal further includes a level shifter that converts the power-on signal into the first negative voltage signal and outputs the signal.
The switch element is
The first negative voltage is applied as the substrate voltage, the output of the level shifter is applied to the gate, and the drain and source of the PMOS transistor are connected to the source and drain, respectively. A semiconductor integrated circuit. A memory cell array in which a plurality of bit lines, a plurality of word lines crossing these bit lines, and a plurality of memory cells respectively connected to any one of the bit lines and the word lines are arranged in a matrix A plurality of memory macros each having
A main power supply circuit block which is formed on the same substrate as the plurality of memory macros and generates and outputs a first negative voltage;
A plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros,
The plurality of memory macros are:
Each further comprising a row decoder for driving the plurality of word lines;
Each of the plurality of word lines is held at a second negative voltage when not selected.
The plurality of local power supply circuit blocks are:
The second wiring is provided with a mesh-like wiring and is disposed adjacent to the row decoder of the corresponding memory macro, and has an absolute value smaller than the first negative voltage based on the first negative voltage. The semiconductor integrated circuit is characterized in that the second negative voltage is applied to the adjacent row decoder via the mesh-like wiring. A memory cell array in which a plurality of bit lines, a plurality of word lines crossing these bit lines, and a plurality of memory cells respectively connected to any one of the bit lines and the word lines are arranged in a matrix A plurality of memory macros each having
A main power supply circuit block which is formed on the same substrate as the plurality of memory macros and generates and outputs a first negative voltage;
A plurality of local power supply circuit blocks corresponding to each of the plurality of memory macros,
Each of the plurality of local power circuit blocks is
Based on the first negative voltage, a second negative voltage having a smaller absolute value than the first negative voltage is generated and given to a corresponding memory macro,
The plurality of memory macros are:
Each further comprising a row decoder for driving the plurality of word lines;
Each of the plurality of word lines is held at the second negative voltage when not selected.
The row decoder
A decoding circuit that decodes a predecode signal indicating which word line is selected, and outputs the obtained decoding result;
A level shifter that outputs the second negative voltage when the decoding result is a low logic level signal, and that outputs a power supply voltage when the decoding result is a high logic level signal;
A drive circuit connected to one of the plurality of word lines and outputting the power supply voltage or the second negative voltage to the word line in accordance with an output of the level shifter;
When a relief signal indicating that a word line connected to the drive circuit is faulty is input, grounding means for applying a ground voltage to the word line,
The level shifter is
A semiconductor integrated circuit characterized in that, when the relief signal is input, the drive circuit blocks a path for applying a voltage to the word line. The semiconductor integrated circuit according to claim 10 ,
The grounding means is
A semiconductor integrated circuit, characterized in that a ground voltage is applied to a source, a word line connected to the drive circuit is connected to a drain, and the relief signal is applied to a gate. The semiconductor integrated circuit according to claim 10 ,
The decoding circuit includes:
A first NAND circuit that receives the predecode signal and obtains and outputs the decode result;
The level shifter is
A first inverter that inverts and outputs the logic level of the output of the first NAND circuit;
A second inverter that inverts and outputs the logic level of the relief signal;
A second NAND circuit for obtaining and outputting a logical product of the output of the first inverter and the output of the second inverter;
A logical sum of the output of the first NAND circuit and the relief signal, and when the result is a low logic level, the NOR circuit that outputs the second negative voltage;
The drive circuit is
A PMOS transistor having a source supplied with the power supply voltage, a drain connected to one of the plurality of word lines, and a gate supplied with the output of the second NAND circuit;
A semiconductor integrated circuit comprising: an NMOS transistor to which the second negative voltage is applied to a source, the word line is connected to a drain, and an output of the NOR circuit is applied to a gate.

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