JP4288209B2 - システム・オン・チップのためのセキュリティ・アーキテクチャ - Google Patents
システム・オン・チップのためのセキュリティ・アーキテクチャ Download PDFInfo
- Publication number
- JP4288209B2 JP4288209B2 JP2004184034A JP2004184034A JP4288209B2 JP 4288209 B2 JP4288209 B2 JP 4288209B2 JP 2004184034 A JP2004184034 A JP 2004184034A JP 2004184034 A JP2004184034 A JP 2004184034A JP 4288209 B2 JP4288209 B2 JP 4288209B2
- Authority
- JP
- Japan
- Prior art keywords
- apu
- load
- local storage
- area
- image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
- G06F21/53—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow by executing in a restricted environment, e.g. sandbox or secure virtual machine
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3226—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using a predetermined code, e.g. password, passphrase or PIN
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/56—Financial cryptography, e.g. electronic payment or e-cash
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
Description
110 ローカル記憶域(LS)
111 非隔離(汎用アクセス)部、汎用アクセス領域、汎用アクセス・メモリ
112 隔離部、隔離領域
115 LSバス
120 付加プロセッサ・ユニット(APU)
127 バス
130 MPU
133 バス
135 バス
138 APU制御バス
140 バス・インターフェース・ユニット(BIU)
145 ロード/終了状態マシーン(LESM)
150 オンチップ・プロセッサ・バス
180 付加プロセッサ複合体(APC)
Claims (8)
- ローカル記憶域に動的に割り振られた区分内でロード・イメージ(コードまたはデータ)を認証するためのシステムであって、
非隔離領域と付加プロセッサ(APU)によってのみアクセス可能な隔離領域に区分される前記ローカル記憶域と、
前記ロード・イメージを前記隔離領域にロードし、マスタ・キーを使用して前記隔離領域にロードされたイメージの少なくとも一部分から少なくとも1つの暗号化された鍵を暗号解除し、前記隔離領域内で使用した前記マスタ・キーを消去した後、暗号解除された前記鍵を使用して前記ロード・イメージを認証し、前記ロード・イメージの実行が終了したことに応答して、前記隔離領域中の前記ロード・イメージをクリアし、前記ロード・イメージのクリア後、前記隔離領域を開放して、前記ローカル記憶域全体を前記非隔離領域に戻すロードおよび終了状態マシーンと、
前記ローカル記憶域中で前記認証されたロード・イメージを実行するように構成され、前記ローカル記憶域に結合された前記APUとを備えるシステム。 - 前記APUが、ローカル記憶域隔離解除コマンドを発行するようにさらに構成される、請求項1に記載のシステム。
- 前記APUが、前記隔離領域中の前記ロード・イメージをクリアするための消去コマンドを発行するようにさらに構成される、請求項1に記載のシステム。
- 前記ローカル記憶域に間接的に結合され前記非隔離領域のみにアクセス可能な主演算処理装置(MPU)をさらに備える、請求項1に記載のシステム。
- 前記APUが、前記ローカル記憶域の前記隔離領域内にある標識(indicia)に前記MPUがアクセスすることを拒否するように構成される、請求項4に記載のシステム。
- コンピュータ・システム中にあるロード・イメージ(コードまたはデータ)を認証するためにローカル記憶域を動的に区分するためのコンピュータ可読なプログラムであって、前記プログラムが、
前記ローカル記憶域を非隔離領域と付加プロセッサ(APU)によってのみアクセス可能な隔離領域に区分するステップと、
前記ロード・イメージを前記隔離領域にロードするステップと、
マスタ・キーを使用して前記隔離領域にロードされたイメージの一部から少なくとも1つの暗号化された鍵を暗号解除し、前記隔離領域内で使用した前記マスタ・キーを消去した後、暗号解除された前記鍵を使用して前記ロード・イメージを認証するステップと、
前記ロード・イメージの認証に成功した場合、前記ロード・イメージを実行するステップと、
前記ロード・イメージの実行が終了した後、前記隔離領域中の前記ロード・イメージをクリアするステップと、
前記ロード・イメージのクリア後、前記隔離領域を開放して、前記ローカル記憶域全体を前記非隔離領域に戻すステップとを前記コンピュータ・システムに実行させる、プログラム。 - 前記ロード・イメージの認証に失敗した場合、前記APUを停止させるステップと、認証の失敗を、前記ローカル記憶域に間接的に結合され前記非隔離領域のみにアクセス可能な主演算処理装置(MPU)に知らせるステップとをさらに実行させる、請求項6に記載のプログラム。
- 前記APU上のデバッグ、検査および診断用インタフェースへの前記MPUによるアクセスをディセーブルすることによって、隔離を実施するステップをさらに実行させる、請求項6に記載のプログラム。
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/601,374 US8838950B2 (en) | 2003-06-23 | 2003-06-23 | Security architecture for system on chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2005018770A JP2005018770A (ja) | 2005-01-20 |
| JP4288209B2 true JP4288209B2 (ja) | 2009-07-01 |
Family
ID=34079539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004184034A Expired - Fee Related JP4288209B2 (ja) | 2003-06-23 | 2004-06-22 | システム・オン・チップのためのセキュリティ・アーキテクチャ |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8838950B2 (ja) |
| JP (1) | JP4288209B2 (ja) |
| CN (1) | CN100375422C (ja) |
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| US8336085B2 (en) | 2004-11-15 | 2012-12-18 | Microsoft Corporation | Tuning product policy using observed evidence of customer behavior |
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| JP4596247B2 (ja) * | 2005-01-31 | 2010-12-08 | ソニー株式会社 | データ処理回路、データ処理装置、データ処理方法、データ処理制御方法、データ処理プログラム及びデータ処理制御プログラム |
| JP4600750B2 (ja) * | 2005-01-31 | 2010-12-15 | ソニー株式会社 | データ処理回路、データ処理装置、データ処理方法、データ処理制御方法、データ処理プログラム及びデータ処理制御プログラム |
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-
2004
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- 2004-06-22 JP JP2004184034A patent/JP4288209B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005018770A (ja) | 2005-01-20 |
| US20050021944A1 (en) | 2005-01-27 |
| US8838950B2 (en) | 2014-09-16 |
| CN100375422C (zh) | 2008-03-12 |
| CN1574730A (zh) | 2005-02-02 |
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