JP4291919B2 - Method for remotely constructing networked devices - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to integrated and methods of causing integrated circuits to execute instructions.
[0002]
[Prior art]
Control units used in embedded systems, such as network peripherals that control various functions in a computer network, include a CPU (Central Processing Unit) and other essential units that work with the CPU, such as a cache memory. A processing circuit having an integrated circuit (IC) is formed. The processing circuit often also includes a number of external units such as external memory units that are connected to and communicate with the integrated circuit via a number of ports.
[0003]
Various types of processing circuit designs can be achieved by equipping a specific design of the integrated circuit with various external units and loading different software into the processing units thus formed. This allows one IC design to be used for a wide range of applications.
[0004]
Often in connection with the manufacturing process, when the processing circuit is first loaded with the software required for its function, it is equipped with one or more memory units and a start-up program is loaded for the function of the processing circuit. It is necessary to provide the integrated circuit with external memory means providing a memory space for receiving additional software programs.
[0005]
Accordingly, the processing circuitry is permanently equipped with external units necessary for initial software loading, or such external units are temporarily connected to the integrated circuit during the software loading phase of the manufacturing process.
[0006]
The cost of the processing circuit increases in an undesired manner since this circuit must be equipped with units that are not preferred or necessary for its subsequent use.
[0007]
If the external unit for initial software loading is connected to the integrated circuit only at the loading stage, this stage of manufacturing is disadvantageously time consuming.
[0008]
The testing of software test versions at the time of development often involves replacing, erasing and reloading memory units, which makes such tests time consuming.
[0009]
[Problems to be solved by the invention]
An object of the present invention is to simplify the loading of necessary software into a processing circuit.
[0010]
Another object is to provide an integrated circuit that can be used in a wide variety of applications.
[0011]
Yet another object of the present invention is to limit the costs associated with the processing circuit manufacturing process.
[0012]
[Means for Solving the Problems]
According to the present invention, these objects and other objects that will become apparent from the following description are achieved in accordance with claims 1 and 9 by an integrated circuit and a method for causing an integrated circuit to execute instructions.
[0013]
According to a first aspect of the invention, the integrated circuit comprises switching means for switching the circuit between a working mode and a start mode, in which the circuit essentially receives an external signal from a CPU on the circuit. The instruction is executed.
[0014]
In the manufacturing process, such an integrated circuit can be equipped with suitable external units for the creation of the desired processing circuit design. There is no need to consider special external unit requirements for the initial software loading of the processing circuitry. Furthermore, the software loading stage can be performed quickly because the processing circuit can be loaded without an auxiliary device during the loading stage.
[0015]
For example, the manufacturing process can be simplified here because software loading can be done at an optional stage in connection with the testing of the final product.
[0016]
Also, an integrated circuit according to the present invention can reload new and different software in the same simple manner as initial loading at any time during its future lifetime.
[0017]
Another advantage is that it allows simple software testing during the development of new software.
[0018]
Yet another advantage of such an integrated circuit is that it can be made to perform limited instructions such as switching external systems without having to load additional software on itself at the start stage.
[0019]
In the context of the present invention, an integrated circuit (IC) means a piece or electronic circuit in a chip having conductors and elements integrated therewith.
[0020]
According to a preferred embodiment of the present invention, the IC is programmed to receive a signal and cause the CPU to execute an instruction. This can be accomplished by logic elements formed in the IC by the hardware itself (hard coded instructions). However, the memory means of the circuit preferably comprises a first memory unit storing the internal instructions for receiving the signals and executing external instructions. The first memory unit preferably includes a ROM that stores the internal command. Thereby, the programming is achieved in a compact and low cost.
[0021]
In another preferred embodiment of the present invention, the memory means of the IC comprises a second memory unit that stores external instructions as executed by the CPU. This second memory unit and the first memory unit described above can be integrated into one and the same unit. However, according to the present invention, it is preferable that the second memory unit is constituted by a cache memory unit. Preferably, the cache memory unit is provided for the CPU anyway and is intended to be used during the subsequent life of the circuit so that the use of the cache memory unit avoids the auxiliary memory unit. The cache memory unit preferably comprises random access memory (RAM), which is switched to a mode that can be used for storage of external instruction storage.
[0022]
According to another preferred embodiment of the present invention, the IC comprises interface control means connected to at least one of the ports, the interface control means for recognizing and receiving the signal in a start mode. Has been. Thereby, this IC can be made to actively intercept signals, for example in a network.
[0023]
According to a second aspect of the present invention, it includes a method in which the IC is put into a start mode to receive an external start signal comprising an external start command. The IC then receives the external signal and uses the integrated CPU to execute the instruction. With the method according to this second feature, the same advantages are achieved as with the integrated circuit according to the first feature.
[0024]
When bringing the integrated circuit into the start mode, the method according to the preferred embodiment includes the act of causing the interface control means of the integrated circuit to receive an external signal. Thereby, the integrated circuit preferably enables the external signal to be recognized among other signals, for example in a network connected thereto. In a preferred manner, this can be accomplished by giving the integrated circuit a predetermined starting address. This address is temporary and unique to the start mode and is recognized by the interface means for receiving an external signal.
[0025]
Thereafter, the method according to the preferred embodiment includes the act of sending an external signal to the integrated circuit, whereby the signal is preferably addressed to a predetermined starting address and preferably has a predetermined size.
[0026]
According to another preferred embodiment of the method, the external instruction is stored in memory means, preferably a cache memory unit, which forms part of the integrated circuit before it is executed when it is received. . Thereby, bringing the IC into the start mode preferably includes an operation that causes the cache memory unit to act as a RAM for storing external instructions.
[0027]
According to another feature of the invention, a first small startup program is permanently stored in the IC and is activated to cause the IC to receive a second, somewhat larger startup program in the start mode. . Thereafter, this second program starts the actual loading of the IC and the external unit connected to it.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1-4 show the various phases of interaction between a configuration server and a plurality of network attached peripherals that need to be built. In the illustrated embodiment, the network attached peripheral device is not manufactured with a unique (unique) network address or basic operating capability. Even when they are attached to the network, they are not built in both network and operational sense. This greatly reduces manufacturing costs on the assumption that peripheral devices can be configured with a unique network address and device-dependent operational capabilities throughout the network, and each processor-like component of the peripheral device is single. To be made from chips.
[0029]
FIG. 1 shows a server 102, a workstation 112, and a plurality of peripheral devices 120A-B, 122 and 124 connected to each other through a network 100. The storage device 104 includes a plurality of applications, an operating system, a transit code, and a storage code in the file 106, and includes program code 108 that configures the server to function as a configuration server. It is out. Each of the peripheral devices 120A-B, 122, and 124 includes two identifiers (IDs) in an embodiment of the present invention, one for the device itself and the other being part of the device. For possible multimode chips. These IDs are not unique to each device, but instead identify the device type, eg, printer / camera type and model number. There may be many peripheral devices with the same ID. The peripheral device IDs of the devices 120A-B are IDs 130A-B, respectively. The peripheral device ID of the printer 122 is a printer ID 132. The ID of the card reader 124 is a card reader ID 134. Each of the peripheral devices is shown in dotted lines in FIG. 1 because all of them are not capable of functioning as printers, card readers or cameras at this point. All of them lack the processing capabilities or operating system code (OS) necessary to function as either a printer, card reader or camera.
[0030]
Each peripheral device includes an attached multi-mode chip with an ID. The chip ID is not as unique as the device ID, but instead identifies the chip type and / or model number. There may be many chips with the same ID. Multimode chip 140A and associated ID 142A are part of peripheral device 120A. The other mode chip 140B and its ID 142B are part of the peripheral device 120B. The other mode chip 140C and its ID 142C are part of the peripheral device 122. The other mode chip 140D and its associated ID 142D are part of the peripheral device 124.
[0031]
In operation, the server 102 starts the processor 102A as a result of the program code 108 contained in the storage device 104. These processes assemble a packet 110 having a group ID (see FIG. 6) and send it through the network 100. Each of the multi-mode chips 140A-D implements a kernel BIOS 144A-D process (see FIG. 1) for a respective peripheral device 120A-B, 122, and 124. These minimal boot code processes that are part of the initial configuration of chips 140A-D allow these chips to accept packets from network 100 with a group ID corresponding to their own group ID. Accordingly, each multi-mode chip receives a packet having a single group ID and allows the processing thereof. Alternatively, one group ID can be for a chip connected to a printer and the other can be for a chip connected to a camera or the like. Even in this embodiment, the other mode chip of one camera may have the same group ID as the others. In one alternative embodiment of the present invention, the initial packet 110 can be broadcast over the network with an address that indicates that all peripheral devices should accept the packet.
[0032]
The operation of the next phase is shown in FIG. In FIG. 2, each of the multimode chips 140A to 140D receives an initial packet 110 having a group ID as a destination address. In this packet, the multi-mode chips 140A-D cause the temporary processes 160A-D to start with the temporary code sent by the server in the initial packet. The chip retrieves their identifiers and the identifiers of the peripheral devices to which they are attached. In response to this, the other mode chip sends response packets 150A to 150D to the server 102. In one embodiment of the invention, these packets include a source address that is a group address and a unique identifier generated by each of the chips 140A-D so that the server can distinguish one packet from the other. A payload may be included. This identifier is not a unique destination address as required in previous peripheral devices. Instead of building each of the multi-mode chips 140A-D in the factory with a unique network ID network, a unique network ID is assigned in the next process. In one embodiment of the invention, each of the chips generates a random number and stores it in the payload portion of the response packet sent to the server. In addition, the response packet sent by each of the multimode chips may include a chip ID and a device ID.
[0033]
Numerous benefits are realized by manufacturing multi-mode chips and peripheral devices that have neither application code nor operating system nor a unique network ID. Initially, the network ID can be dynamically assigned in the process described below. Second, the latest version of the OS and / or application code can be downloaded to the device during the actual build on the network. Third, the cost of the peripheral device can be reduced by implementing the peripheral device with a chip that can have both network interaction and capabilities that function as a basic processing unit for the external device. When the server 102 receives the packet (s) 150A-D from each of the multi-mode chips 140A-D, it begins the file 106 lookup process 102B.
[0034]
FIG. 3 shows the next phase of the download phase operation. As described above in FIG. 2, after the server receives a packet from one or more external devices, the server establishes process 102C. Process 102C utilizes the chip and device identifier of the incoming packet to find the appropriate OS or application code for the multimode chip and the application code for the peripheral device that embeds each multimode chip in file 106. . The server then sends packets 170A-D using the same group ID as the destination address. In another embodiment of the present invention, the server may include a broadcast address as a destination address.
[0035]
In either embodiment, the payload of each packet contains the random number sequence received in the incoming packet and the boot and application code for the corresponding device. In some embodiments of the invention, each packet may also include a corresponding chip and device identifier.
[0036]
Each multimode chip 140A-D of each peripheral device collects all group packets, but only the OS and / or application code from a packet containing a random number that matches the random number generated by a particular multimode chip. use. In this manner, each of the peripheral devices processes only its own unique packet even though they lack a unique network address at this stage. In addition, the payload of each unique packet from the server includes a unique network address assigned by the server for subsequent use by the peripheral device.
[0037]
FIG. 4 shows the final operation phase. At this point, each multimode chip has a unique network address. Multimode chips are beginning to function additionally as an integral processing unit for each peripheral component. The card reader 124, the configuration process 174 can now read the card 114. The printer 122 and the configuration process 172 can receive print jobs via the network 100. Cameras 120A-B, configuration process 176-B can take images and send them over the network. This latter function is achieved by the device specific OS and / or application code downloaded from the server 102 in FIG.
[0038]
FIG. 5 is a hardware block diagram of the multimode chip 140A and the peripheral device 120A (see FIGS. 1 to 4). Multimode chip 140A includes a central processing unit (CPU) 200, local memory 202, cache 204, direct memory access (DMA) controller 206, memory controller 208, address and data buffers 210A-B, and optional switch 212. The cache includes a cache controller 248 and a cache memory 250. In this case, the peripheral device that is the webcam 120A includes a main memory 220, a charge coupled device (CCD) controller 222, a CCD and lens assembly 224, a device ID 130, a volatile memory 226, and an external port 230 that connects the chip to the network. It is out.
[0039]
Multimode chip 140A includes a local data and address bus and control bus 218, indicated at 214-216, respectively. Local bus 214 couples CPU 200 to local memory 202, cache 204, DMA controller 206, and data buffer 210B. Local address bus 216 couples the CPU to local memory, cache and memory controller 208. The control bus couples the CPU to the local memory 202, cache 204 and DMA controller 206. Both the DMA controller and the memory controller are coupled to address buffer 210A. Optional switch 212 provides a switchable input to CPU 200. An external port 230 couples the CPU to the LAN (see FIGS. 1-4). In this embodiment of the invention, the network interface function is performed by either chip 140A or by CPU 200 or a separate on-chip media access controller (MAC) and packet processor. In another embodiment of the present invention, external port 230 couples the chip to the LAN via an external network interface (not shown). Peripherals and chips are coupled to each other via an interface port 258 that includes address, data and control signal lines.
[0040]
Within the peripheral device, the system bus 228 connects the main memory 220, the peripheral device ID 130, the volatile memory 226, and the CCD controller 222. The CCD controller is coupled to the CCD and lens coupling assembly 224. Between the multimode chip and peripheral devices, address and data connections from address and data buffers 210A-B respectively couple the two devices. Additional coupling is provided by a control bus 218 that couples the CCD controller 222 to the DMA controller 206. A multimode chip identifier 142A exists in the multimode chip 140A. The chip ID is organized in one embodiment of the invention as a read-only register that is part of the CPU of this chip. In other embodiments, the chip ID may be stored in the local memory 202. This chip identifier is used with the device identifier 130 to identify the multi-mode chip and device manufacture and / or model number to the server 102. In other words, this identifier need not be unique to a device except for groups of devices that have a common manufacturing and / or model number.
[0041]
There are three phases in the initialization of multimode chips and peripheral devices. These phases correspond to the packets 110, 150A-D and 170A-D shown in FIGS. The present invention provides a combination device that can be configured remotely over the network from the original configuration without a unique network address or operating system. In the first phase of operation, the local memory contains only the group identifier 242 and the kernel BIOS 144A. The kernel BIOS 144A can configure the local bus, determine whether it is in initialization or normal mode, and from the server 102 that has a group identifier rather than a unique network ID as the destination address. It can respond to the packet 110 (see FIG. 1).
[0042]
An additional feature of the kernel BIOS is that it disables the cache controller 248 to allow temporary use of the cache as normal volatile memory. In normal mode, the chip's cache subsystem has the function of checking for hit / miss, dirty bits, etc. In BIOS and transit phase operations, the cache memory acts as a “normal” random access memory (RAM) by disabling hit / miss checks and the like. Instead, the cache RAM is mapped with a fixed address. In the operation of the BIOS phase shown in FIG. 1, the server 102 sends out a packet 110 having a generic group identifier as a destination address. This packet is processed by any and all multimode chips 140A-D shown in FIG. Although each of these chips has a condition that the local memory 202 has a group identifier 242 corresponding to the group identifier in the packet. When a packet is received, its payload portion is extracted and a temporary code 252 is loaded. This temporary code provides random number generation, identification, packet transmission and packet reception capabilities.
[0043]
Next, the operation of the second or temporary phase starts in the multimode chip. The operation of this phase is illustrated in FIGS. In the temporary phase, temporary code 252 is executed. This code has several functions. First, it performs the function of sending a response packet with a payload containing the random number generated by the CPU 200 at runtime and the chip and device model IDs 142A, 130 when the multi-mode chip is executed. In one embodiment of the present invention, this random number may correspond to the time since a power-on reset, for example. This random number needs to have enough bits so that the risk of two peripheral devices generating the same number can be ignored. Even if several units or peripherals are turned on at the same time, they will generate different numbers because more than one unit cannot send packets over the network at the same time. By putting this number in a packet and temporarily storing this number in the cache memory 250, the multimode chip can identify the return packet from the server that contains this random number in the payload with these two simple comparisons. It becomes.
[0044]
A third or operational phase chip operation is shown in FIG. In this phase, storage from the server and OS / application code 254 are downloaded to the multi-mode chip and stored in the cache memory 250. Using the storage code, this operational process transfers the operating system to main memory. With the device constructed in this way, the multi-mode chip acts as a central processing unit for the webcam execution process 176A (see FIG. 4). The cache returns to its normal function of holding a copy of the newly used portion of main memory 220 for access by CPU 200.
[0045]
6 and 7A to C show an embodiment of a packet protocol in the local area network (LAN) 100 (see FIGS. 1 to 4). Information transferred through the network is processed by a wrapping protocol for the information being transferred. Each packet includes a plurality of headers and a payload. These headers contain information specific to one of the corresponding seven layers of the OSI model. The header and payload in the LAN are called a packet. The header and payload in an integrated services digital network (ISDN) are called a frame. Until recently, network traffic in LAN and ISDN networks consisted of packets / frames with up to seven headers and payloads. The header contained information specific to each of the seven layers of the OSI model. The payload contains the audio, video or data to be transferred. The structure of the header and payload in the LAN is defined by each IEEE LAN standard such as 802.3, 802.5, and the like. These standards are referred to below as 802. Call it X. On the ISDN side, the header and payload structure is defined by the Point-to-Point Protocol (PPP) or High Level Data Link Protocol (HDLC) popularized by the International Organization for Standardization (ISO).
[0046]
FIG. 6 shows a detailed view of one of the possible packet formats 320 that may be transmitted over the LAN 100 (see FIGS. 1-4). Details of wrappers for packet 320 are shown. In particular, the protocol for this packet conforms to the IEEE 802.3 standard. An 802.3 packet begins with a preamble 300. This preamble is 7 bytes in length, and each byte includes a bit pattern 10101010. This preamble allows the receiver clock to be synchronized with the sender. Next comes the start part 302 of the frame flag containing the binary sequence 10101011. Next is a destination address field 304 that is 6 bytes in length, followed by a source address field 306 that is also 6 bytes in length. Source address field 306 identifies the party sending the packet, and destination address field 304 identifies the party to which the packet is being sent. A length field 308 follows. This length field, which is 2 bytes in length, indicates how many bytes are present in the data / payload field from a minimum of 0 to a maximum of 1500 bytes. Headers 310-314 include a network layer header, a transport layer header, and a session layer header for payload field 316, respectively. The payload may include various types of information including modem session start commands, session parameters or data. The data may be audio, video or text. Immediately following the payload is a checksum field 318.
[0047]
7A to 7C show the packets 110, 150A, and 170A, respectively, sent between the server and the peripheral device as described above with reference to FIGS.
[0048]
FIG. 7A shows a packet 110 sent first from the server to all peripheral devices having a group identifier corresponding to the group ID in the packet destination address field (see FIG. 1). This packet includes a group identifier which is the same identifier (see number 242 in FIG. 5) as each of the multimode chips 140A to 140D as its destination address field 304. The portion of the source address field 306 of the packet contains the network address of the server 102. The payload field 316A includes a temporary code 252 (see FIG. 5). This code enables a receiving multimode chip with the ability to obtain both its peripheral device identifier and chip identifier. In addition, this code allows the chip to generate a random number and send a response packet to the server. Furthermore, this code allows the chip to receive a return packet and process it. Thereafter, this code is erased or rewritten by a normal cache operation.
[0049]
FIG. 7B shows a packet 150A sent from any peripheral device in response to the initial packet 110 of the server. Using the temporary code, the multimode chip places a random number 420, a chip model identifier 142A, and a camera identifier 130 (see FIG. 5) in the payload field 316B of the packet. A destination address field 304 is an address of the server 102. The multimode chip gets its address from the source address field 306 (see FIG. 7A) of the initial incoming packet 110 from the network 100.
[0050]
FIG. 7C shows a second packet 170A sent by the server 102 to the peripheral device (see FIG. 3). This packet has a group identifier as a destination address. This packet is received and processed by all multimode chips. The source address of this packet is the address of the server 102. In the payload field 316C, the server packages a random number 420 that was originally generated by the multimode chip and received by the server in packet 150A. This number is unique to each chip for the reasons described above in FIG. 5 and is used by the chip to identify one packet containing the same random number among packets 170A-D. In one embodiment of the present invention, the chip model ID 142A and the camera ID may also be included in the payload from the server to the chip. The next portion of the payload field 316C contains a unique network address 440 assigned by the server for the particular peripheral that generated the random number. Peripheral device addresses are global and are centrally managed by the server to ensure the specificity of each address. This unique network address is used by peripheral devices and multimode chips in subsequent network communications. Thus, in all subsequent communications over the network, packets sent to the peripheral device are not sent on a group basis, and the destination address field 304 of the LAN packet contains a unique network address, so a targeted basis. Sent based on The next portion 442 of the payload field 316C includes two code segments 254 and 450. The first of these code segments is the operating system and / or application for this particular peripheral that is networked. The second of these code segments, “store” code 450, contains the code necessary to write OS 254 and its image to main memory 220 and volatile memory 226 (see FIG. 5).
[0051]
FIG. 8 shows the data structure of the storage device 104 (see FIGS. 1 to 4) of the server 102. The device operating system of program code 108 and temporary code file 106 is illustrated. More particularly, the temporary code database device operating system includes a plurality of records for each of the peripheral devices 120A-B, 122, 124, as well as for all multi-mode chips 140A-D. Similarly, a record of each model and version number may be included. Each record includes a format identifier field 500, a product ID field 502, an address field 504, a temporary code field 506 and an operating system code field 508. In the illustrated example of this record, the webcams 120A-B include a product ID 130A-B in the product ID field 502 and the operating of the camera 254 so that the CPU 200 can program the main memory 220 (see FIG. 5). Includes both system and storage code 450. The records of the multimode chips 140A-D include a temporary code 252 (see FIG. 5) in the temporary code field 506. In order for the server to download the code to each peripheral device, it assigns the device a unique network ID that is first sent to the device in the payload of the packet with the group address as the destination address. That address is used by peripheral devices and associated multimode chips in subsequent network communications. To deal with this, the server records the address it assigned to the device in the network namespace and file 106. The entry “1234” in the address field 440 of the record of the peripheral device 120A is shown in the destination address field 440 of that record. They become individual records and individual network addresses of the peripheral device 120B.
[0052]
FIG. 9 illustrates a process 102A associated with the operation of the server 102 as described above in FIGS. The server process 600 begins at process 602 where a temporary code 252 (see FIGS. 5 and 7) is obtained from the file 106 of the storage device 104 (see FIGS. 1-4). Control is then passed to process 604. In process 604, the packet 110 is assembled using the destination address corresponding to the peripheral device group ID (see FIG. 7A, FIG. 1). Control is then passed to decision process 606. In decision process 606, the server responds to any one of the packets 159A-D of one or more multimode chips 140A-B (see FIG. 2). Control is then passed to process 608. In process 608, the server extracts the random number generated by the multi-mode chip from the payload field 316B (see FIG. 7B) and the chip and device ID represented by 142A and 130, respectively.
[0053]
In process 610, the server goes to the lookup table of file 106 to find the corresponding record of chip ID and peripheral device ID obtained in the incoming packet in process 608 described above. Using these IDs, a record with the corresponding chip and peripheral device ID is located in the lookup table of file 106. For example, a temporary code such as 252 (see FIG. 8) is obtained from the record having the corresponding chip ID. From the record with the corresponding peripheral device ID, for example, 120A / B, OS and / or application code and storage code are obtained at 254, 450, for example. The storage code is used to load the OS and / or application code for the peripheral device into the main memory. Control is then passed to process 612.
[0054]
In process 612, the server generates a unique network address for the peripheral device and includes that address in the payload portion of packet 170. That address is used by peripheral devices and associated multimode chips in subsequent network communications. To address this, the server records the unique network address that it assigned to the device in the network namespace and file 106. For example, the unique network address “1234” is shown in the network address field 440 that is part of the record of the peripheral device 120A.
[0055]
The device and chip ID, as described above, distinguishes only one type of peripheral device from other or preferably one model number peripheral device from others of the same type. However, the device and chip ID do not distinguish peripheral devices having the same model number from others. This distinction is achieved by a unique network address assigned by the server. The server passes the random number stamp in the packet from 1 to the server. The server keeps track of random numbers received in the incoming packet from the peripheral device and assigns the corresponding network address to the device. Control is then passed to process 614.
[0056]
In process 614, a payload similar to that described in FIG. 7C and described above is assembled by the server. The payload includes a generic group ID, which means that it is received by all peripheral devices, and a random number 420 received by the server from the corresponding peripheral device is included in the payload. The payload also contains the OS and storage code that make up the device. The payload also contains a random number originally generated by the device. This random number is used by the peripheral device to distinguish the packet from others that contain the same group address.
[0057]
Control is then passed to process 616 where the server sends the packet to the peripheral device over network 100 (see FIG. 3). Control is then passed to process 618. Here, the server completes the operation of detecting and configuring the peripheral device. As will be apparent to those skilled in the art, the server may then function as a repository or database for the peripheral device.
[0058]
FIGS. 10-11 illustrate one embodiment of a process with a multi-mode chip and attached peripherals to obtain a unique network ID and a suitable operating system. Processing for the bios subroutine 700 begins with a process 702 that occurs after power on. In process 702, kernel BIOS 144A begins execution (see FIG. 5). The local bus and associated elements, ie local memory 202, cache 204, DMA controller 206 and memory controller 208 are enabled (see FIG. 5). Control is then passed to process 704. In process 704, the BIOS attempts to determine the mode of the multimode chip. In one embodiment of the invention, the BIOS monitors a specific address or pin to determine its state. In one embodiment of the invention, the pins are connected to an optional switch 212 (see FIG. 5) that can be used to manually place the multi-mode chip 140A into either the normal runtime mode or the initialization mode. In another embodiment of the present invention, the address is an address in local memory that includes one bit sequence for initialization mode and another for runtime mode. For example, if a unique network ID 244 (see FIG. 5) does not exist in local memory, the BIOS is in initialization mode. Control is then passed to decision process 706.
[0059]
In a decision process 706, a determination is made as to which mode the chip is in. There are many ways that this determination can be achieved. Optional switch 212 can be manually set. Alternatively, a certain address in memory can be read by CPU 200 to determine its value. In one alternative embodiment of the present invention, each multimode chip and peripheral device initially operates in a start mode. The non-volatile programmable means (eg, PROM, FPGA, fuse, etc.) of the chip provides a switching signal to the switch when the optional switch 212 (see FIG. 5) is in its initial state (eg, the fuse is not blown). After the chip is initialized and the OS code is loaded into the main memory (see FIG. 5), the programmable device that controls the switching signal is changed so that the CPU boots from the main memory at the next time.
[0060]
For example, if a determination is made that the multi-mode chip is in runtime mode, control is passed to process 708. In process 708, the cache 204 is enabled to function as a cache with, for example, any number of cache policies, including, for example, “write-through” or “copy-back”. The Control is then passed to process 710 where the operating system 256 stored in the main memory 220 of the peripheral device (see FIG. 5) is loaded from the main memory into the RAM 226 to cause the peripheral device operation to start as a webcam. The In this mode, control is then passed to process 712 where the BIOS completes its operation. In another embodiment of the present invention, the OS is executed directly from main memory without being loaded into RAM.
[0061]
In one embodiment of the present invention, the CPU 200 acts as a processor for a packet assembler and deassembler (PAD) as well as a network interface including a medium access control (MAC) function. In another embodiment of the present invention, CPU 200 serves as a processor for a peripheral device, such as webcam 120A. At this time, the CPU 200 implements various image processing algorithms. In another embodiment of the present invention, CPU 200 serves as both a network interface processor including MAC and PAD functions and a processor for peripheral devices.
[0062]
Unlike the previous case, if decision process 706 reaches a decision that the chip is in initialization mode, control is passed to process 720. In process 720, cache controller 248 (see FIG. 5) is disabled, so that the cache functions as normal volatile memory. Control is then passed to process 722. In process 722, CPU 200 performs the simple network interface functions described in the following processes 724-742, either on its own or in conjunction with a dedicated MAC chip and PAD chip. Control is then passed to process 724. In process 724, the CPU 200 intercepts packets from the LAN 100. Control is then passed to decision process 726. In process 726, CPU 200 examines destination address field 304 (see FIG. 7A) to determine the destination address. If the destination address is a group ID corresponding to the group ID 242 stored in the local memory 202 (see FIG. 5), control is then passed to the decision process 728. If the destination address does not correspond to the group ID for this multimode chip, control returns to process 724 for retrieval of the next packet.
[0063]
When control is passed to the decision process 728, the packet received with the group ID in the destination address field 304 is in the first packet format, such as packet 110, sent by the server or as in 170, for example. A determination is made whether the packet is of a second packet type. In one embodiment of the invention, this determination is based on the number of sequences, for example 0 or 1, placed by the server in packets 110, 170 (see FIGS. 1 and 3). There are a number of different ways in which server packets with temporary codes can be distinguished from packets containing random numbers, network addresses and OS and storage codes. First, when the IP protocol is realized, the number of sequences is included in the transmission layer included in the transmission layer header (see FIG. 6) of the LAN packet. Alternatively, the sequence number can be placed in the payload by the server. Alternatively, the CPU 200 can examine the payload to see if there is something similar to the temporary code unlike the payload random number, network address and OS. If a determination is made that the received packet is not in the first packet format, it is a packet defined in some other peripheral device further in the initialization process. In this case, control is returned to the next packet fetch process 724. If a positive determination is reached as before, ie if the packet with the group ID is the first packet 110 rather than the second packet 170 sent by the server, control is passed to process 738.
[0064]
In process 738, the source address of the incoming packet, i.e., the unique network address of server 102, is stored at a particular location in the cache, and control is then passed to process 740. In process 740, temporary code 408 (see FIG. 7A) is extracted from the payload and stored in a particular portion of the cache. Control is then passed to process 742 where a jump from local memory kernel BIOS to temporary code is realized. Control is then passed to process 744 where the kernel BIOS completes its function.
[0065]
In FIG. 11, the process is executed from the code stored in the cache, not the BIOS. The temporarily disabled cache serves as volatile memory, which contains the temporary code received from the server (see FIG. 1) in the initial packet 110. Temporary mode 750 begins with a process 752 that begins with the portion of the cache where the temporary code is stored. Control is then passed to process 754. In process 754, the CPU 200 obtains the processor ID 142A and the peripheral device ID 130 from the function code segment of the temporary code. These device IDs can be determined in a number of ways. In the embodiment described above, device ID 142A is organized as part of the CPU, ie as its read-only register. Alternatively, the ID may be somewhere on the chip including a local memory such as an electrically programmable and electrically erasable read only memory (EEPROM) 202. Alternatively, the chip ID can be formed on an external series of DIP switches or fusible links. In one embodiment of the invention, this ID is part of the multimode chip at the time of manufacture. In another embodiment of the present invention, this ID is designed during installation. The same form can be given to the device ID 130. It can also be a dedicated memory, such as an EEPROM, a DIP switch or a fusible link. In another embodiment of the present invention, the device ID is not hard-coded, but is found by a process that is initialized with temporary code and executed by the CPU 200. The CPU may, for example, determine the type of response that is derived by continuing reading and writing to a particular location in the memory map or I / O space. Based on the response, the CPU can determine what type of peripheral device it is connected to and the characteristics of the multimode chip.
[0066]
In process 756, CPU 200 generates a random number that may be a function of time since bootup. As noted above, this random number does not match the random number generated by any other peripheral device that may be responding to the same packet 110 from the server 102 (see FIG. 1). It must be of a sufficient number of bits to Control is then passed to process 758. In process 758, the CPU 200 reads the group ID in the nonvolatile local memory 202. In another embodiment of the present invention, the group ID may be in a totally independent media access controller (MAC) connected to the CPU. Control is then passed to process 760. In process 760, the CPU 200 reads the portion of the cache memory that is executed by the kernel BIOS and includes the source address described above in FIG. The source address corresponds to the unique network address of the server 102 obtained from the initial packet 110 by the kernel BIOS. In process 762, simple network interface functions including media access control (MAC) and packet assembly and deassembly (PAD) are performed by the CPU. Control is then passed on to the first part of the function as performed in the next process 764.
[0067]
In process 764, the payload is assembled including the random number generated in process 756. A group ID 242 (see FIG. 5) and a source address field 306 (see FIG. 7A) are placed in the source and destination fields of the payload, respectively. The group ID 242 may be built into the chip at the time of manufacture. The destination address is obtained from the source address field 110 of the incoming packet 110. This packet is sent to server 102 in process 766.
[0068]
Control is then passed to process 768 for processing incoming packets from network 100. Each of these packets is analyzed in a continuous decision process 770-774. In process 770, a determination is made as to whether the packet includes a destination address corresponding to the group ID of the peripheral device. If so, control is passed to process 772. In process 772, the packet is of the first or second format, ie it is the first packet format (see FIGS. 1 and 7A) containing only a temporary code or the second packet format 170 (FIG. 3, A determination is made as to whether (see FIG. 7C). The second packet format includes a random number, OS and / or application and storage code as described above. If it is a second type packet and contains a random number, control is passed to decision process 774.
[0069]
In a decision process 774, a determination is made whether the random number in the packet payload matches the random number generated by the CPU 200. If the random number of the packet matches the random number generated by the CPU, control is passed to process 776. In process 776, the payload of incoming packet 170A is obtained and the unique network address 440, storage code 450 and OS code 454 are decomposed from the payload. The storage code is stored in a specific location in the cache, the operating system is stored elsewhere in the cache, and the network address field 440 is stored in the local memory 202 as a network ID 244. In another embodiment of the present invention, the network ID may be sent to a separate network interface device. Control is then passed to process 778. In process 778, CPU 200 jumps to the portion of the cache memory that contains the stored code and begins executing that code. Control is then passed to process 780.
[0070]
In process 780, the stored code causes CPU 200 to transfer a continuous line of operating system code from cache memory 250 (see FIG. 5) to main memory 220 (see FIG. 5). Further, the unique network ID is also transferred to the nonvolatile memory, for example, the main memory 220. In an alternative embodiment of the present invention, the unique network address can be stored in any non-volatile memory of either the chip or peripheral device or network interface. Once the entire operating system has been transferred, control is passed to process 782.
[0071]
In process 782, the OS image is loaded from the main memory into the RAM 226. The process then enables the cache in process 784, for example by allowing the CPU to write to a specific pin that has a connection to that cache controller that converts to runtime mode by enabling the cache controller 248. Is done. Control is then passed to process 786 where the temporary code is terminated and normal operation of the multimode chip and peripheral device begins.
[0072]
It will be apparent to those skilled in the art and the length of the operating system can be greater than 1500 bytes without departing from the teachings of the present invention. However, this is the case if an additional process is made to retrieve the packets followed by the temporary code and transfer them to the main memory.
[0073]
In an alternative embodiment of the invention in which only one peripheral device is connected to the network at a time, many of the procedures described and described above, together with the device connected to the network alone, Or it can work with multiple devices connected to the network simultaneously.
[0074]
It is also possible to use the method described above to send a simple command to the CPU and activate it to do simple things such as machine activation or light on / off switching.
[0075]
The processing circuit formed by the IC according to the present invention and the external unit connected to it are suitable for use in different network peripheral devices such as print servers and CD-ROM servers.
[0076]
The invention has been represented by way of example above and many modifications are possible within the scope of protection of the claims.
[0077]
In the preferred embodiment of the present invention, the CPU receives the first start program and then executes a command to switch the IC to the start mode. However, in an alternative embodiment, the NIC and / or cache memory can have the ability to switch itself to a start mode.
[0078]
By allowing the IC to receive a second startup program via the network port and actively receiving this second startup program, the IC can be used during the manufacturing process as well as during subsequent lifetimes. Easy to load. In particular, the last feature is a great advantage when the processing circuit is used in a network peripheral. This is because it can be upgraded or changed over the network when it is in start mode.
[0079]
However, the present invention is not limited to the second startup program being received via the network port. Other ports of the IC such as a parallel port, serial port or auxiliary loading port can be used for loading processing circuitry. In these cases, the program preferably has a predetermined size. Thereby, another interface control unit can be used, or the control unit may not be used at all, for example if the second startup program is immediately transferred to the cache memory unit.
[Brief description of the drawings]
FIG. 1 shows an overall network environment in which network attached peripheral devices are built from a central server.
FIG. 2 shows an overall network environment in which network attached peripheral devices are constructed from a central server.
FIG. 3 shows an overall network environment in which network attached peripheral devices are constructed from a central server.
FIG. 4 shows an overall network environment in which network attached peripheral devices are constructed from a central server.
FIG. 5 is a hardware block diagram of a dual mode chip and peripheral device according to an embodiment of the present invention.
FIG. 6 shows an IEEE 802.3 packet.
FIG. 7 shows packets sent between a server and a peripheral device at various layers of the configuration process.
FIG. 8 shows a data structure in a server.
FIG. 9 is a process flow diagram of a peripheral device construction process performed by a server.
FIG. 10 is a process flow diagram of a construction process performed by a peripheral device.
FIG. 11 is a process flow diagram of a construction process performed by a peripheral device.
[Explanation of symbols]
200 CPU
202 Local memory
204 cache
206 DMA controller
208 Memory controller

Claims (5)

A method of remotely constructing a network-connected device, wherein the network connection device is connected to a server by a network, the server is connected to a storage device including a program code segment, and each program code A method for remotely constructing the network connection device, wherein the segment is suitable to enable operation of the corresponding group of the network connection device,
An operation of receiving a first data packet from an unidentified network connection device among the network connection devices in the server (act), wherein the first data packet includes a device type identifier and an irregular identifier; The device type identifier corresponds to the group of unidentified network connection devices among the network connection devices, and the irregular identifier is the operation generated by the unidentified network connection device among the network connection devices. When,
In response to the operation of receiving the first data packet, an operation of sending a second data packet from the server, wherein the second data packet includes the irregular identifier, the program code segment, and a unique network address. The program code segment corresponds to the group of the unidentified network connection devices of the network connection devices, and the unique network address is assigned to the unidentified network connection device of the network connection devices. The above actions assigned by the server, and
An operation of processing the second data packet based on the irregular identifier included in the second data packet in the unidentified network connection device of the network connection devices;
In the non-identified network connection device of the network connection devices, an operation of assigning the unique network address assigned by the server during the operation of sending a second data packet as a network address;
A method comprising the steps of: The method of claim 1, wherein the act of receiving a first data packet is prior to the act of:
An operation of transmitting an initial data packet from the server to the network connection device;
Accepting the initial data packet in each of the network connection devices;
In response to the operation of accepting the initial data packet, an operation of sending the first data packet from an unidentified network connection device among the network connection devices, wherein the first data packet is a device type identifier. The device type identifier corresponds to the group of unidentified network connection devices of the network connection devices, and the irregular identifier is the unidentified network connection of the network connection devices. The above operations generated by the device;
A method comprising the steps of:   3. The method according to claim 2, wherein the initial data packet transmitted from the server in the operation of transmitting an initial data packet is generated by the unidentified network connection device among the network connection devices. A method characterized in that it further comprises temporary program code that allows the   3. The method according to claim 2, wherein the initial data packet transmitted from the server in the operation of transmitting an initial data packet is received by the unidentified network connection device among the network connection devices. A method, further comprising temporary program code that enables the second data packet to be detected in operation.   The method according to claim 1, wherein the initial data packet transmitted from the server in the operation of transmitting an initial data packet is determined by the unidentified network connection device among the network connection devices in the operation to be assigned. A method characterized in that it further comprises temporary program code that allows a unique network address to be assigned.

Images