JP4293103B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a thick Cu electrode formed on a device.

  Conventionally, a semiconductor device (IC chip) including a semiconductor device such as a relay that requires a large driving current (for example, 10 amperes or more), a power device such as an LDMOS, and a thick Cu electrode formed on these devices. is there.

  This device includes, for example, an element (such as an impurity region in a semiconductor substrate) constituting an LDMOS, a wiring layer formed on the surface of the semiconductor substrate and electrically connected to the element, and an uppermost part of the semiconductor substrate. A thick Cu electrode layer formed and electrically connected to the wiring layer, an organic resin film covering the Cu electrode layer, a bonding wire connecting the Cu electrode layer and the external terminal, and a mold resin for sealing them It has.

  Here, the Cu electrode layer is an electrode layer entangled in mounting (wire bonding, solder connection, etc.), and is an electrode layer made of Cu. Since the specific resistance of Cu is as low as 1.5 to 2.0 μmΩcm, Cu is used as an electrode material for reducing the on-resistance of the electrode. Further, in order to lower the on-resistance, the thickness of the Cu electrode layer is increased to, for example, 3 μm or more.

  Next, a method for manufacturing this semiconductor device (mainly a method for forming a thick Cu electrode layer having a thickness of 3 μm or more) will be described. 10 and 11 show the formation process of the Cu electrode layer.

[Step shown in FIG. 10A]
First, a semiconductor substrate on which the above-described element and the above-described wiring layer are formed is prepared. On the uppermost part of the semiconductor substrate, for example, as shown in the figure, a TEOS (Tetra Ethyl OrthoSilicate) film 53 as an interlayer insulating film, an Al wiring 54 as a wiring layer, and a P-SiN film as a protective film for an element (Plasma nitride film) 55 are sequentially formed. In the P-SiN film 55, an opening 55a is formed in a portion located above the Al wiring 54.

[Step shown in FIG. 10B]
Subsequently, a barrier / seed layer (a barrier metal layer such as Ti and a Cu seed layer) 61 is formed on the P-SiN film 55 and in the opening 55a. This seed layer is for forming a Cu electrode layer later by plating.

[Step shown in FIG. 10 (c)]
Subsequently, a thick positive photoresist 71 is formed on the barrier / seed layer 61. The film thickness of the photoresist 71 is, for example, 10 μm. Then, an opening 71a used as a mold when forming the Cu electrode layer is formed in the photoresist 71 above the Al wiring 54 by photolithography.

[Step shown in FIG. 10 (d)]
Subsequently, a Cu film is formed only inside the opening 71a of the photoresist 71 by electroplating. That is, the height of the Cu film to be formed is set so as not to exceed the upper surface of the photoresist 71. Thereby, for example, a thick Cu electrode layer 72 of 3 to 10 μm is formed.

[Step shown in FIG. 10 (e)]
Subsequently, the photoresist 71 is removed with a stripping solution. Thereafter, the barrier / seed layer 61 exposed from the Cu electrode layer 72 is removed by wet etching. This leaves the barrier / seed layer 61 only below the Cu electrode layer 72.

[Step shown in FIG. 11A]
Subsequently, the Cu electrode layer 72 is subjected to hydrogen reduction heat treatment (hereinafter referred to as hydrogen annealing). Thereby, the oxide film 73 formed on the surface of the Cu electrode layer 72 during the manufacturing process is removed. This is because when the oxide film 73 is present on the surface of the Cu electrode layer 72, the adhesion with the organic resin film 74 described later is lowered.

[Step shown in FIG. 11B]
Subsequently, an organic resin material such as polyimide is applied on the surface of the Cu electrode layer 72 and the P—SiN film 55 in order to ensure insulation between the Cu electrode layers. As a result, the surface of the Cu electrode layer 72 and the upper surface of the P—SiN film 55 are covered with the organic resin film 74. The film thickness 74a of the organic resin film 74 is usually 2 to 10 μm.

  As described above, the thick Cu electrode layer 72 is formed on the uppermost portion of the semiconductor substrate. Thereafter, the Cu electrode layer 72 is subjected to wire bonding with an external terminal.

  However, in the photolithography in the process shown in FIG. 10C, the side surface 71b of the resist 71 in the opening 71a has a forward tapered shape due to the exposure characteristic limit of the resist 71. Accordingly, in the Cu electrode layer 72 formed inside the opening 71a of the resist 71, the side surface 72a of the Cu electrode layer 72 is reversely tapered. Here, the forward taper shape refers to a shape in which the width gradually increases toward the bottom, and the reverse taper shape refers to a shape in which the width gradually narrows toward the bottom.

  For this reason, when an organic resin material is applied in the step shown in FIG. 11B, the film thickness 74b of the organic resin film 74 in the vicinity of the electrode upper surface corner portion is thinner than the film thickness 74a of other parts ( The problem of poor coverage occurs. Such a problem occurs because the viscosity of the organic resin material is low, so that when the organic resin material is applied, the surface of the organic resin material tends to be as low as possible.

  As a result, a moisture ingress path is formed by a crack or the like generated in this portion, and problems such as peeling of the organic resin film 74 and short-circuiting between electrodes occur. Such a problem tends to become more prominent as the film thickness (height) of the Cu electrode layer 72 is larger.

  Therefore, conventionally, as a method of suppressing such a problem, as shown in FIG. 12, for example, a method of increasing the total film thickness 81a of the organic resin film 81 to about 5 μm or more has been adopted. FIG. 12 shows a conventional countermeasure method. This method is intended to increase the thickness 81b of the organic resin film 81 in the vicinity of the upper corner portion of the Cu electrode by increasing the overall thickness 81a of the organic resin film 81.

  However, in this method, there is a limit to increasing the thickness of the organic resin film due to the viscosity of the organic resin material, and the organic resin film cannot be made a certain thickness or more. For this reason, depending on the thickness (height) of the Cu electrode layer, the above problem may not be solved.

  A method of increasing the thickness of the organic resin film by increasing the viscosity of the organic resin material is also conceivable. However, in this case, since the viscosity of the organic resin material is high, the organic resin material cannot be embedded in the fine pattern in the step of applying the organic resin material, which causes a problem that a void is generated. Absent.

  In view of the above, the present invention provides a semiconductor device capable of improving the coverage of the organic resin film at the upper corner portion of the Cu electrode layer without particularly increasing the thickness of the entire organic resin film, and a method for manufacturing the same. The purpose is to do.

  In order to achieve the above object, according to the first aspect of the present invention, the step of forming the Cu electrode layer (2) includes the Cu electrode layer (2) by isotropically growing the Cu film by a plating method. It is characterized by forming.

  Thereby, the shape of a Cu electrode layer can be made into the shape where an upper surface corner part is round. As a result, when an organic resin film is formed on the surface of the Cu electrode layer, the film thickness at the upper corner portion of the Cu electrode layer of the organic resin film can be increased. That is, according to the present invention, the coverage of the organic resin film at the upper corner portion of the Cu electrode layer can be improved without particularly increasing the thickness of the entire organic resin film.

  In the description of claim 1, forming Cu electrode layer (2) by growing Cu isotropically means that Cu is formed at least at the final stage of forming the outer shape of Cu electrode layer. It means that the Cu electrode layer is formed by isotropic growth.

  Specifically, for example, the Cu electrode layer can be formed by a method as shown in claim 2. That is, in the step of preparing the semiconductor substrate, the barrier metal layer (56) formed on the surface of the wiring layer (54), the wiring layer and the barrier metal layer (56) are covered, and the wiring layer (54) and the barrier are covered. A semiconductor substrate provided with a first insulating film (55) having a first opening (55a) formed above the metal layer (56) is prepared. Then, in the step of forming the Cu electrode layer (2), the position of the upper surface (2a) of the Cu electrode layer (2) in the first opening (55a) is the outermost position of the first insulating film (55). The Cu electrode layer (2) can be formed so as to be higher than the upper surface (55b).

  Further, for example, the Cu electrode layer can be formed by a method as shown in claim 3. That is, in the step of preparing the semiconductor substrate, the second insulating film (55) covering the wiring layer (54) and having the second opening (55a) formed above the wiring layer (54); The Cu plating seed layer (61) formed on the surface of the second insulating film (55) from the inner surface of the second opening (55a), and the second insulating film among the Cu plating seed layer (61) A second organic resin film (57) covering a portion formed on the surface of (55) and having a third opening (57a) formed above the second opening (55); A semiconductor substrate is prepared.

  Then, in the step of forming the Cu electrode layer (2), the position of the upper surface (2a) of the Cu electrode layer (2) in the third opening (57a) is the second insulating film and the second organic resin. The Cu electrode layer (2) is formed so as to be higher than the uppermost surfaces (55b, 57b) of the films (55, 57). Further, between the step of forming the Cu electrode layer (2) and the step of forming the first organic resin film (3), of the second organic resin film (57), the Cu electrode layer (2) The part (57d) except the lower part is removed.

  Further, the Cu electrode layer can be formed by a method as shown in claim 4. That is, in the step of preparing the semiconductor substrate, a third insulating film (55) that covers the wiring layer (54) and has the fourth opening (55a) above the wiring layer (54) is provided. A semiconductor substrate is prepared.

  Then, in the step of forming the Cu electrode layer (2), the fifth opening (71a) is provided on the third insulating film (55) in a portion located above the fourth opening (55a). A step of forming a photoresist (71), a step of forming a first Cu film (91) only by electrolytic plating within the fifth opening (71a), and a step of removing the photoresist (71) And forming the Cu electrode layer (2) by isotropically forming the second Cu film (92) on the surface of the first Cu film (91) by electroless plating. It can also be done.

The invention according to claim 5 is characterized in that the upper corner portion (2g) of the Cu electrode layer (2) is rounded.

  The present invention is manufactured by the invention described in claim 1. Therefore, the present invention has the same effect as that of the first aspect.

In the shape of the Cu electrode layer, as shown in claim 6 , the wiring layer (54) is covered with the first insulating film (55), and the Cu electrode layer (2) is covered with the first insulating film (55). In the case of being provided in the opening (55a) provided in the first insulating film (2h), the length (2h) in the direction perpendicular to the surface of the semiconductor substrate in the rounded portion (2g) 55) from the flat surface (55b) to the upper surface (2a) of the Cu electrode layer (2) is 1/3 or more of the length (2i) in the direction perpendicular to the surface of the semiconductor substrate. preferable.

  In addition, the code | symbol in the bracket | parenthesis of each said means is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

(First embodiment)
FIG. 1 is a sectional view of a semiconductor device according to the first embodiment of the present invention. In the present embodiment, a semiconductor device having LDMOS, CMOS, and bipolar transistors as elements will be described as an example.

The semiconductor device (IC chip) shown in FIG. 1 includes a power device 1, a thick Cu electrode layer 2 on the power device 1, an organic resin film 3 covering the Cu electrode layer 2, a bonding wire 4 and these. And a mold resin 5 to be stopped.
Here, the power device 1 means a structure part including both the element structure part 6 formed on the semiconductor substrate and the wiring structure part 7 formed on the semiconductor substrate in this specification. This element structure 6 corresponds to the element of the present invention.

First, the element structure 6 will be described. As a semiconductor substrate on which the element structure portion 6 is formed, an SOI substrate is used, and includes an Si substrate 11, a buried oxide film 12, and a semiconductor layer 13. The semiconductor layer 13 has an N ⁺ type layer 14 and an N ⁻ type layer 15. A trench oxide film 16 is formed in the semiconductor layer 13. The buried oxide film 12 and the trench oxide film 16 isolate elements such as LDMOS, CMOS, and bipolar transistors.

The LDMOS is composed of an N-type drain region 17, a P-type channel region 18, and an N ⁺ -type source region 19 that are located on the surface layer of the semiconductor layer 13 (N ⁻ -type layer 15). An N ⁺ -type contact layer 20 is formed on the surface layer of the N-type drain region 17, and a P-type contact layer 21 is formed on the surface layer of the P-type channel region 18. The N-type drain region 17 and the P-type channel region 18 are separated by a so-called LOCOS oxide film 22. A gate electrode 24 is disposed on the P-type channel region 18 via a gate insulating film 23.

The CMOS includes an N-type well layer 31 in the semiconductor layer 13 (N ⁻ -type layer 15), a P-type layer 32 on the surface of the N-type well layer 31, an N ⁺ -type source region 33 on the surface of the P-type layer 32, and An N ⁺ type drain region 34 is formed. Further, a gate electrode 36 is disposed on a region of the P-type layer 32 between the N ⁺ -type source region 33 and the N ⁺ -type drain region 34 with a gate insulating film 35 interposed therebetween. Although only an N-channel MOSFET is shown here, a P-channel MOSFET is also arranged.

The bipolar transistor is formed in the semiconductor layer 13 and connected to the N ⁺ type layer 14, an N ⁺ type collector region 41, a surface P type base region 42 of the semiconductor layer 13 (N ⁻ type layer 15), P The surface layer of the type base region 42 includes an N ⁺ type emitter layer 43 and a P ⁺ type contact layer 44.

  Next, the wiring structure portion 7 includes a BPSG film 51, a 1st Al film 52, a TEOS film 53, a 2nd Al film 54, and a P-SiN film 55 as a passivation film, which are sequentially formed on the semiconductor layer 13. have. The 1stAl film 52 and the 2ndAl film 54 are power lines for connecting elements such as LDMOS, CMOS, and bipolar transistors, ground lines, or wirings that electrically connect the elements, and correspond to the wiring layer of the present invention.

  The Cu electrode layer 2 is disposed on the top of the IC chip. Here, FIG. 2 shows an enlarged view of the region A in FIG. Specifically, as shown in FIG. 2, the Cu electrode layer 2 is disposed in an opening 55 a formed in the P-SiN film 55 above the 2ndAl film 54. The Cu electrode layer 2 is electrically connected to the 2ndAl film 54 through the barrier metal layer 56. In FIG. 1, the barrier metal layer 56 is omitted. The barrier metal layer 56 is formed only on the upper surface of the 2nd Al film 54. The barrier metal layer 56 is made of TiN, for example.

  Further, as shown in FIG. 2, the Cu electrode layer 2 is located above (outside) the portion 2 c located in the opening 55 a of the P—SiN film 55 and the opening 55 a of the P—SiN film 55. And a portion 2d exposed from the P-SiN film 55.

  The portion 2d of the Cu electrode layer 2 exposed from the P-SiN film 55 has an upper surface 2a and a side surface 2b, and the upper surface corner portion 2g between the upper surface 2a and the side surface 2b is rounded. It has a shape. Note that the length 2h in the height direction (direction perpendicular to the surface of the semiconductor substrate) of the rounded portion 2g is a flat surface 55b of the portion of the P-SiN film 55 that does not cover the 2ndAl film 54. To 1/3 or more of the height 2i from the Cu electrode layer 2 to the upper surface thereof.

  The Cu electrode layer 2 has a thickness of 3 to 10 μm, for example. The thickness of the Cu electrode layer 2 may be 10 μm or more. As shown in FIG. 1, the Cu electrode layer 2 is directly connected to a portion (for example, a portion of the region A) 2e directly connected to the bonding wire 4 via an Al-based film 62 as will be described later. 2f (for example, a central CMOS upper portion in FIG. 1) 2f.

  As shown in FIG. 1, the organic resin film 3 is arranged so as to reach the surface of the Cu electrode layer 2 and the P-SiN film 55 exposed from the Cu electrode layer 2 so as to cover the Cu electrode layer 2. Yes. The organic resin film 3 covers at least the upper surface corner portion 2g and the side surface 2b of the Cu electrode layer 2.

  The organic resin film 3 ensures insulation between the adjacent Cu electrode layers 2, protects the Cu electrode layer 2, and relieves stress between the mold resin 5 and the P-SiN film 55. Is for. As the organic resin film 3, for example, a polyimide film is used. The film thickness 3a of the organic resin film 3 on the P—SiN film 55 is, for example, 2 to 10 μm, and the film thickness 3b of the upper surface corner portion 2g of the Cu electrode layer 2 is, for example, about 1 to 2 μm. is there.

  As shown in FIGS. 1 and 2, an opening 3 c is formed in a portion of the organic resin film 3 located above a part of the Cu electrode layer 2. As shown in FIGS. 1 and 2, an Al-based film 62 such as an Al film or an Al alloy film is disposed on the bottom of the opening 3c. The Al-based film 62 is electrically connected to the Cu electrode layer 2.

  As shown in FIGS. 1 and 2, the bonding wire 4 electrically connects an Al-based film 62 and an external terminal, and is made of Au. As shown in FIG. 1, the mold resin 5 is disposed on the upper surface of the organic resin film 3 and in the opening 3 c of the organic resin film 3.

  Next, a method for manufacturing the semiconductor device having such a configuration will be described. 3A to 3C show a part of the manufacturing process of the semiconductor device in this embodiment. In the present embodiment, the steps shown in FIGS. 3A to 3C are performed.

[Step shown in FIG. 3 (a)]
First, a semiconductor substrate on which the above-described element structure 6 and the above-described wiring structure 7 are formed is prepared. This semiconductor substrate is in a wafer state. Further, as shown in the drawing, a TEOS film 53, a 2ndAl film 54, and a P-SiN film 55 in the wiring structure portion 7 are formed on the uppermost portion of the semiconductor substrate. A barrier metal layer 56 is formed only on the upper surface of the 2nd Al film 54. The barrier metal layer 56 is laminated on the 2ndAl film 54 and patterned simultaneously with the 2ndAl film 54.

  The P-SiN film 55 covers the 2nd Al film 54 and the barrier metal layer 56. The P-SiN film 55 has an opening 55 a formed in the upper part of the 2nd Al film 54. The barrier metal layer 56 is exposed from the P-SiN film 55 through the opening 55a. The element structure 6 corresponds to the element of the present invention, and the 2ndAl film 54 in the wiring structure 7 corresponds to the wiring layer of the present invention. The P-SiN film 55 corresponds to the first insulating film of the present invention, and the opening 55a of the P-SiN film 55 corresponds to the first opening of the present invention.

[Step shown in FIG. 3B]
In this step, the Cu electrode layer 2 is formed in the opening 55a of the P-SiN film 55 by plating. At this time, the Cu electrode layer 2 is formed so that the position of the upper surface 2 a of the Cu electrode layer 2 is higher than the upper surface 55 b in the vicinity of the opening 55 a of the P-SiN film 55. That is, the Cu electrode layer 2 is formed so that the thickness of the Cu electrode layer 2 is thicker than the thickness of the P-SiN film 55. The upper surface 55b of the P-SiN film 55 in the vicinity of the opening 55a corresponds to the uppermost surface of the first insulating film in the present invention.

The plating method at this time is an electroless plating method, and after the catalyst treatment and activation treatment, for example, plating is performed with the following composition.
Copper chloride: 20 g / liter Ethylenediamine: 30 g / liter Cobalt nitrate 100 g / liter Further, by forming the Cu electrode layer 2 in this way, the height direction of the rounded portion 2 g (relative to the surface of the semiconductor substrate) The length 2h in the vertical direction) is 1/3 or more of the height 2i from the flat surface 55b of the P-SiN film 55 that does not cover the 2ndAl film 54 to the upper surface of the Cu electrode layer 2.

[Step shown in FIG. 3 (c)]
After performing hydrogen annealing on the Cu electrode layer 2, an Al-based film 62 as a bonding pad is formed on the upper surface 2 a of the Cu electrode layer 2. Then, similarly to the step shown in FIG. 11B, an organic resin material is applied from the surface of the Cu electrode layer 2 to the P-SiN film 55 exposed from the Cu electrode layer 2. A polyimide raw material is used as the organic resin material. Thereby, the organic resin film 3 is formed.

  Thereafter, an opening 3 c is formed in the upper portion of the organic resin film 3 above the Al-based film 62. Subsequently, wire bonding is performed on the Al film 62, the bonding wire 4 is bonded to the Al film 62, and the Cu electrode layer 2 and the external terminal are electrically connected. Then, the semiconductor device shown in FIGS. 1 and 2 is manufactured through a sealing step using a mold resin (not shown).

  Next, features of the present embodiment will be described. As described above, in this embodiment, in the step shown in FIG. 3B, the position of the upper surface 2a of the Cu electrode layer 2 is higher than the upper surface of the P-SiN film 55 by plating. The Cu electrode layer 2 is formed. That is, unlike the process shown in FIG. 10D, the Cu electrode layer 2 is formed without using the photoresist 71 having the opening 71a.

  Thereby, when the Cu film becomes higher than the P-SiN film 55, it grows not only in the upward direction but also in the lateral direction. Thus, by forming the Cu electrode layer 2 by isotropically growing the Cu film, the shape of the upper portion 2d of the Cu electrode layer 2 above the P-SiN film 55 is rounded. It can be set as the shape which has. In the step shown in FIG. 10D, the Cu electrode layer is not isotropic and grows only upward in the opening 71 a of the photoresist 71.

  As a result, when the organic resin film 3 is formed on the surface of the Cu electrode layer 2, the thickness 3b of the upper surface corner portion 2g of the Cu electrode layer 2 of the organic resin film 3 can be increased. Therefore, according to the present embodiment, the coverage of the organic resin film 3 in the upper surface corner portion 2g of the Cu electrode layer 2 can be improved without particularly increasing the thickness of the entire organic resin film 3.

  According to the method of this embodiment, the length 2h in the height direction of the rounded portion 2g is such that the Cu electrode layer extends from the flat surface 55b of the P-SiN film 55 that does not cover the 2ndAl film 54. The height to the upper surface of 2 is 1/3 or more of the height 2i. Thereby, compared with the case where the roundness of the upper surface corner portion 2g of the Cu electrode layer 2 is smaller than 1/3, the film thickness 3b in the upper surface corner portion 2g of the Cu electrode layer 2 of the organic resin film 3 is more Can be thicker.

(Second Embodiment)
FIG. 4 is a partial sectional view of a semiconductor device according to the second embodiment of the present invention. FIG. 4 is an enlarged view of region A in FIG. 5A to 5D show a manufacturing process of the semiconductor device according to this embodiment. In the present embodiment, a method for forming the Cu electrode layer 2 having a rounded upper corner portion 2g by a method different from the first embodiment will be described.

  As shown in FIG. 4, the Cu electrode layer 2 of the present embodiment also has a rounded shape at the upper surface corner portion 2 g, similarly to the structure shown in FIG. 2 of the first embodiment. The first organic resin film 3 has a thick film thickness 3b in the vicinity of the upper surface corner portion 2g of the Cu electrode layer 2.

  On the other hand, the structure in the vicinity of the Cu electrode layer 2 of the present embodiment is different from the structure shown in FIG. 2 of the first embodiment in that the barrier / seed layer (barrier metal layer and seed layer) 61 is different from that of the Cu electrode layer 2. Between the 2nd Al film 54 and within the opening 55a of the P-SiN film 55 to the upper surface of the P-SiN film 55 located below the Cu electrode layer 2, and the second organic The resin film 57 is disposed between the barrier / seed layer 61 and the Cu electrode layer 2 disposed on the upper surface of the P-SiN film 55 located below the Cu electrode layer 2.

  The barrier seed layer 61 is electrically connected to the 2nd Al film 54. The barrier metal layer is made of Ti, for example, and the seed layer is made of Cu. The P-SiN film 55 and the opening 55a thereof correspond to the second insulating film and the second opening of the present invention. The barrier seed layer 61 corresponds to the Cu plating seed layer of the present invention.

  The manufacturing method of this embodiment is a method of forming the barrier / seed layer 61 on the entire surface of the wafer. Specifically, after the steps shown in FIGS. 10A and 10B are performed, the steps shown in FIGS. 5A to 5D are performed.

[Step shown in FIG. 5A]
In this step, the second organic resin film 57 is formed on the barrier / seed layer 61. At this time, as the second organic resin film 57, the same material as that of the first organic resin film 3, for example, polyimide is used. The second organic resin film 57 can be made of a material different from that of the first organic resin film 3. The film thickness of the second organic resin film 57 is 1 μm or more.

  Subsequently, an opening 57a is formed in a portion corresponding to a region where the Cu electrode layer 2 is to be formed in the second organic resin film 57 by photolithography and etching. That is, the opening 57a is formed in the upper part of the opening 55a of the P-SiN film 55. The opening 57a of the second organic resin film 57 corresponds to the third opening of the present invention.

  As a result, the opening 55 a of the P—SiN film 55 is exposed from the second organic resin film 57. As a result, only the portion of the barrier / seed layer 61 where the Cu electrode layer 2 is to be formed (near the opening 55a of the P-SiN film 55) is exposed, and the other region is exposed to the second organic resin film. 57 is covered.

[Step shown in FIG. 5B]
In this step, the Cu electrode layer 2 is formed in the opening 57a of the second organic resin film 57, which is a region where the Cu electrode layer 2 is to be formed, by electrolytic plating. At this time, the Cu electrode layer 2 is formed so that the position of the upper surface 2a of the Cu electrode layer 2 is higher than the uppermost surfaces 55b and 57b of the P-SiN film 55 and the second organic resin film. The other plating conditions are the same as those in a known plating method.

[Step shown in FIG. 5 (c)]
In this step, using the Cu electrode layer 2 as a mask, the second organic resin film 57d and the barrier / seed layer 61 located except under the Cu electrode layer 2 are removed by etching. That is, the portion 57d of the second organic resin film 57 excluding the portion 57c below the Cu electrode layer 2 is removed. 5B, the plurality of Cu electrode layers 2 that are electrically connected are electrically separated from each other by the barrier / seed layer 61. In the present embodiment, the second organic resin film 57 and the barrier / seed layer 61 remain under the Cu electrode layer 2.

[Step shown in FIG. 5 (d)]
In this step, the Al-based film 62 and the organic resin film 3 are formed as in the step shown in FIG. Thereafter, wire bonding is performed on the Al-based film 62, the bonding wire 4 is bonded to the Al-based film 62, and the Cu electrode layer 2 and the external terminal are electrically connected. The semiconductor device shown in FIGS. 1 and 4 is manufactured through a sealing step using a mold resin (not shown).

  As described above, also in the present embodiment, in the step shown in FIG. 5B, the position of the upper surface 2a of the Cu electrode layer 2 is the highest of the P-SiN film 55 and the second organic resin film 57 by the plating method. The Cu electrode layer 2 is formed so as to be higher than the upper surface.

  Thus, when the Cu film becomes higher than the P-SiN film 55 and the second organic resin film 57, it grows in the upward and lateral directions. Thus, by forming the Cu electrode layer 2 by isotropically growing the Cu film, the shape of the upper portion 2d of the Cu electrode layer 2 above the P-SiN film 55 is rounded. It can be made into a certain shape. As a result, this embodiment also has the same effect as the first embodiment.

  In the present embodiment, the second organic resin film 57 is formed in the step shown in FIG. 5A, and the first organic resin film 3 is formed in the step shown in FIG. 5D. The organic resin film is formed twice. However, the process shown in FIG. 5A in this embodiment is replaced with the process of forming the thick photoresist 71 in the process shown in FIG. The number of steps is the same as that of the conventional manufacturing method described above.

(Third embodiment)
FIG. 6 is a partial sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 6 is an enlarged view of a region A in FIG. 7A to 7E show manufacturing steps of the semiconductor device according to this embodiment. In the present embodiment, a method of forming the Cu electrode layer 2 having a rounded upper surface corner portion 2g by a method different from the first and second embodiments will be described.

  As shown in FIG. 6, the Cu electrode layer 2 of the present embodiment also has a rounded shape at the upper surface corner portion 2 g, similarly to the structure shown in FIG. 2 of the first embodiment. In addition, the first organic resin film 3 has a thick film thickness 3 b in the vicinity of the upper surface corner portion 2 g of the Cu electrode layer 2.

  On the other hand, the structure in the vicinity of the Cu electrode layer 2 of the present embodiment is different from the structure shown in FIG. 2 of the first embodiment in that the barrier / seed layer 61 is between the Cu electrode layer 2 and the 2nd Al film 54. The Cu electrode layer 2 is composed of an inner first Cu film 91 and an outer second Cu film 93, and is disposed in the opening 55a (bottom surface and side wall) of the P-SiN film 55. It is that you are.

  The manufacturing method of this embodiment is also a method of forming the barrier / seed layer 61 on the entire surface of the wafer, as in the second embodiment. Specifically, after the steps shown in FIGS. 10A to 10C are performed, the steps shown in FIGS. 7A to 7C are performed. The P-SiN film 55 and the opening 55a thereof correspond to the third insulating film and the fourth opening of the present invention, respectively.

[Step shown in FIG. 7A]
In this step, the first Cu film 91 is formed in the opening 71a of the photoresist 71 formed in the step shown in FIG. The plating conditions in this electrolytic plating method are the same as those in a known plating method. This opening 71a corresponds to the fifth opening of the present invention.

  At this time, the first Cu film 91 is grown only inside the opening 71a of the photoresist 71, and the first Cu film 91 is shaped along the side wall of the opening 71a. Further, the size of the first Cu film 91 is made smaller than the Cu electrode layer 2 to be formed.

[Step shown in FIG. 7B]
In this step, the photoresist 71 is removed.

[Step shown in FIG. 7C]
In this step, using the first Cu film 91 as a mask, portions of the barrier / seed layer 61 other than those immediately below the first Cu film 91 are removed by etching. As a result, the barrier / seed layer 61 is left only below the first Cu film 91.

[Step shown in FIG. 7 (d)]
In this step, the second Cu film 92 is formed on the surface (the upper surface 91a and the side surface 91b) of the first Cu film 91 by electroless plating. Thereby, the Cu electrode layer 2 is formed. The plating conditions at this time are the same as the plating conditions in the step shown in FIG. 3B in the first embodiment. At this time, the length 2h in the height direction of the rounded portion 2g is a height from the flat surface 55b of the portion not covering the 2ndAl film 54 in the P-SiN film 55 to the upper surface of the Cu electrode layer 2. The second Cu film 92 is made sufficiently thick so that it becomes 1/3 or more of the thickness 2i.

[Step shown in FIG. 7 (e)]
In this step, the Al-based film 62 and the organic resin film 3 are formed as in the step shown in FIG. Thereafter, wire bonding is performed on the Al-based film 62, the bonding wire 4 is bonded to the Al-based film 62, and the Cu electrode layer 2 and the external terminal are electrically connected. And the semiconductor device shown in FIGS. 1 and 6 is manufactured through a sealing step using a mold resin (not shown).

  As described above, also in the present embodiment, in the step shown in FIG. 7D, the surface of the first Cu film 91 is formed on the surface of the first Cu film 91 by a plating method without using a mold such as a photoresist opening. The Cu electrode layer 2 is formed by forming the second Cu film 92.

  As a result, the second Cu film 92 grows in the upward and lateral directions, that is, in an isotropic manner. For this reason, the shape of Cu electrode layer 2 can be made into the shape which has roundness in upper surface corner part 2g. As a result, this embodiment also has the same effect as the first embodiment.

(Fourth embodiment)
FIG. 8 is a partial sectional view of a semiconductor device according to the fourth embodiment of the present invention. FIG. 8 is an enlarged view of region A in FIG. 9A to 9D show a manufacturing process of the semiconductor device in this embodiment. In the present embodiment, a means for improving the coverage in the vicinity of the upper surface corner portion 2g of the Cu electrode layer 2 in the organic resin film 3 by a method different from the first to third embodiments will be described.

  As shown in FIG. 8, like the structure shown in FIG. 2 in the first embodiment, the TEOS film 53, the 2nd Al film 54, the P-SiN film 55, the barrier metal layer 56, the organic resin film 3, It has an Al-based film 62 and bonding wires 4. A Cu electrode layer 94 is formed in the opening 55 a of the P—SiN film 55.

  In the present embodiment, unlike the above-described embodiments, the shape of the Cu electrode layer 94 is the reverse tapered shape of the side surface 94b, similar to the Cu electrode layer 72 described in the section of the related art. The organic resin film 3 includes a third organic resin film 93 and a fourth organic resin film 95. The position of the upper surface 93 b of the third organic resin film 93 is higher than the position of the upper surface 94 a of the Cu electrode layer 94. The fourth organic resin film 95 covers the upper surface 94 a of the Cu electrode layer 94 and the upper surface 93 b of the third organic resin film 93, and has an opening 95 a above the Cu electrode layer 94.

  The manufacturing method of the present embodiment is a method of forming the Cu electrode layer 94 using the barrier metal layer 56 without using the barrier / seed layer 61. Specifically, the steps shown in FIGS. 9A to 9D are performed.

[Step shown in FIG. 9A]
This step is the same as the step shown in FIG. The P-SiN film 55 and its opening 55a correspond to the fourth insulating film and the sixth opening of the present invention.

[Step shown in FIG. 9B]
In this step, the third organic resin film 93 is formed so as to reach the surface of the P-SiN film 55 and the inside of the opening 55a of the P-SiN film 55. For example, a polyimide film is used as the third organic resin film 93. The film thickness of the 3rd organic resin film 93 shall be 5-10 micrometers, for example.

  Subsequently, an opening 93a is formed in a portion corresponding to a region where the Cu electrode layer 94 is to be formed in the third organic resin film 93 by photolithography and etching. That is, the opening 93 a is formed in a portion of the third organic resin film 93 located above the opening 55 a of the P-SiN film 55. In the present embodiment, the opening 93 a of the third organic resin film 93 is located on the center side of the opening 55 a of the P-SiN film 55.

[Step shown in FIG. 9C]
In this step, the Cu electrode layer 94 is formed only inside the opening 93a of the third organic resin film 93 by electroless plating. That is, the Cu electrode layer 94 is formed using the opening 93a of the third organic resin film 93 as a mold. As a result, a Cu electrode 94 electrically connected to the 2nd Al film 54 is formed via the barrier metal layer 56.

  At this time, the Cu electrode layer 94 is formed so that the position of the upper surface 94 a of the Cu electrode layer 94 does not exceed the upper surface 93 b of the third organic resin film 93. The thickness of the Cu electrode layer 94 is 3 to 10 μm, for example. Further, other plating conditions at this time are the same as the steps shown in FIG. 3B of the first embodiment. In FIG. 9C, the position of the upper surface 94a of the Cu electrode layer 94 is set lower than the upper surface 93b of the third organic resin film 93, but may be the same position.

[Step shown in FIG. 9 (d)]
In this step, the fourth organic resin film 95 is formed from the upper surface 94 a of the Cu electrode layer 94 to the upper surface 93 b of the third organic resin film 93. The fourth organic resin film 95 is made of the same material as the third organic resin film 93. For example, a polyimide film can be used as the fourth organic resin film 95. Note that the materials of the third organic resin film 93 and the fourth organic resin film 95 may be different. The film thickness of the fourth organic resin film 95 is set to 1 μm or more, for example.

  Thereafter, in the fourth organic resin film 95, an opening 95a is formed in a region where the Al-based film 62 is to be formed, and the Al-based film 62 is formed in the opening 95a. Subsequently, wire bonding is performed, and the bonding wire 4 is connected to the Al-based film 62. Furthermore, the semiconductor device shown in FIGS. 1 and 8 is manufactured through a sealing step using a mold resin (not shown).

  As described above, in the present embodiment, the Cu electrode layer 94 is formed only inside the opening 93a in the third organic resin film 93 in the step shown in FIG. That is, the Cu electrode layer 94 is formed so that the position of the upper surface 94 a of the Cu electrode layer 94 does not exceed the upper surface 93 b of the third organic resin film 93. Further, in the step shown in FIG. 9D, the fourth organic resin film 95 is formed from the upper surface 94 a of the Cu electrode layer 94 to the upper surface 93 b of the third organic resin film 93.

  Thereby, the film thickness 3b of the organic resin film 3 in the upper surface corner portion 94g of the Cu electrode layer 94 can be increased. Therefore, according to the present embodiment, the coverage of the organic resin film 3 in the upper surface corner portion 94g of the Cu electrode layer 94 can be improved without particularly increasing the thickness of the entire organic resin film 3.

  In the present embodiment and the first embodiment, a Cu electrode is formed by plating using a barrier metal layer 56 such as TiN formed on the upper surface of the 2ndAl film 54 without using the seed layer 61 made of Cu. Layers 2 and 94 are formed. This barrier metal layer 56 is patterned together with the 2nd Al film 54.

  In contrast, in the second and third embodiments, after the seed layer 61 is formed on the entire surface of the wafer, the seed layer 61 is formed in the step shown in FIG. 5C or the step shown in FIG. By patterning, the seed layer 61 located in an unnecessary region is removed.

  Therefore, according to this embodiment and 1st Embodiment, the process of removing the seed layer 61 located in an unnecessary area | region can be made unnecessary.

(Other embodiments)
(1) In each of the above-described embodiments, the semiconductor device having LDMOS, CMOS, and bipolar transistors as elements has been described as an example. However, the present invention is not limited to this, and other large driving current (for example, 10 amperes or more) is required. The present invention can also be applied to a semiconductor device or a semiconductor device including another power device.

  (2) In each of the above-described embodiments, the case where an element formed in a semiconductor substrate such as an LDMOS, CMOS, or bipolar transistor is used as an element has been described as an example. However, the element is formed in a semiconductor substrate. The present invention can be applied not only to a semiconductor device using an element formed on the surface of a semiconductor substrate, such as a passive element.

It is sectional drawing of the semiconductor device in 1st Embodiment of this invention. It is an enlarged view of the area | region A in FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device in 1st Embodiment of this invention. It is a fragmentary sectional view of the semiconductor device in a 2nd embodiment of the present invention. It is sectional drawing which shows the manufacturing process of the semiconductor device in 2nd Embodiment of this invention. It is a fragmentary sectional view of the semiconductor device in a 3rd embodiment of the present invention. It is sectional drawing which shows the manufacturing process of the semiconductor device in 3rd Embodiment of this invention. It is a fragmentary sectional view of the semiconductor device in a 4th embodiment of the present invention. It is sectional drawing which shows the manufacturing process of the semiconductor device in 4th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the conventional semiconductor device. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; It is a fragmentary sectional view of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Power device, 2, 72, 94 ... Cu electrode layer,
2a, 94a ... the upper surface of the Cu electrode layer, 2b, 94b ... the side surface of the Cu electrode layer,
2 g, 94 g, the upper surface corner of the Cu electrode layer,
3, 81 ... Organic resin film (first organic resin film), 4 ... Wire for bonding,
5 ... Mold resin, 6 ... Element structure, 7 ... Wiring structure, 8 ... Cu nitride film,
53 ... TEOS film, 54 ... 2ndAl film,
55 ... P-SiN film, 56 ... Barrier metal layer, 57 ... Second organic resin film,
61 ... barrier seed layer, 62 ... Al-based film,
71 ... Photoresist, 73 ... Oxide film,
91 ... 1st Cu film, 92 ... 2nd Cu film,
93: third organic resin film, 95: fourth organic resin film.

Claims (6)

Providing a semiconductor substrate on which an element (6) and a wiring layer (54) electrically connected to the element (6) are formed;
Forming a Cu electrode layer (2) having a thickness of 3 μm or more electrically connected to the wiring layer (54) on the semiconductor substrate and above the wiring layer (54);
Forming a first organic resin film (74, 3) covering the Cu electrode layer (2) on the surface of the Cu electrode layer (2);
The step of forming the Cu electrode layer (2) comprises forming the Cu electrode layer (2) by isotropically growing a Cu film by a plating method. In the step of preparing the semiconductor substrate, the barrier metal layer (56) formed on the surface of the wiring layer (54), the wiring layer and the barrier metal layer (56) are covered, and the wiring layer (54 And a semiconductor substrate comprising a first insulating film (55) having a first opening (55a) formed above the barrier metal layer (56),
In the step of forming the Cu electrode layer (2), the position of the upper surface (2a) of the Cu electrode layer (2) is located in the first insulating film (55) in the first opening (55a). The method for manufacturing a semiconductor device according to claim 1, wherein the Cu electrode layer (2) is formed to be higher than an uppermost surface (55b). In the step of preparing the semiconductor substrate, a second insulating film (55) that covers the wiring layer (54) and has a second opening (55a) formed above the wiring layer (54). Of the Cu plating seed layer (61) formed on the surface of the second insulating film (55) from the inner surface of the second opening (55a), and among the Cu plating seed layer (61), A second organic resin that covers a portion formed on the surface of the second insulating film (55) and has a third opening (57a) formed above the second opening (55). Preparing the semiconductor substrate comprising a film (57),
In the step of forming the Cu electrode layer (2), the position of the upper surface (2a) of the Cu electrode layer (2) in the third opening (57a) is the second insulating film and the second electrode. The Cu electrode layer (2) is formed to be higher than the uppermost surfaces (55b, 57b) of the organic resin films (55, 57),
Of the second organic resin film (57), the Cu electrode layer (2) is formed between the step of forming the Cu electrode layer (2) and the step of forming the first organic resin film (3). 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing a portion (57 d) excluding a lower portion of (). The step of preparing the semiconductor substrate includes a third insulating film (55) that covers the wiring layer (54) and has a fourth opening (55a) above the wiring layer (54). Preparing the semiconductor substrate,
The step of forming the Cu electrode layer (2) includes:
Forming a photoresist (71) having a fifth opening (71a) on a portion located above the fourth opening (55a) on the third insulating film (55);
Forming a first Cu film (91) only by electroplating inside the fifth opening (71a);
Removing the photoresist (71);
Forming the Cu electrode layer (2) by forming the second Cu film (92) isotropically on the surface of the first Cu film (91) by electroless plating. The method of manufacturing a semiconductor device according to claim 1, comprising: An element (6) formed on a semiconductor substrate;
A wiring layer (54) formed on the main surface of the semiconductor substrate and electrically connected to the element (6);
A Cu electrode layer (2) formed on the upper side of the wiring layer (54) and electrically connected to the wiring layer (54) having a thickness of 3 μm or more;
In a semiconductor device comprising an organic resin film (3) covering the Cu electrode layer (2),
The Cu electrode layer (2) has a rounded upper corner (2g). The wiring layer (54) is covered with a first insulating film (55), and the Cu electrode layer (2) is provided in an opening (55a) provided in the first insulating film (55). And
The length (2h) in the direction perpendicular to the surface of the semiconductor substrate in the rounded portion (2g) is from the flat surface (55b) of the first insulating film (55) to the Cu electrode layer (2 6. The semiconductor device according to claim 5 , wherein the length is equal to or more than 1/3 of a length (2 i) in a direction perpendicular to the surface of the semiconductor substrate up to the upper surface (2 a).

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