JP4293380B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to an SRAM (static random access memory) and an on-chip memory mounted in a system LSI.

As the voltage applied to the memory cell is reduced and the cell size is reduced, deterioration of soft error resistance becomes a problem. As a semiconductor integrated device using an ECC (Error Correct Codes) circuit for correcting such a data error, Japanese Patent Laid-Open Nos. 61-50295 and 7-45096 are known. Japanese Patent Laid-Open No. 7-45096 discloses a circuit technique for correcting a defective bit by adding a parity bit to normal data. Japanese Patent Application Laid-Open No. 11-212877 discloses a circuit technique for rewriting a part of data having the same parity bit.
JP 61-50295 A JP-A-7-45096

  However, in Japanese Patent Application Laid-Open No. 7-45096, in order to correct an error at the time of reading, it is necessary to read all the data in the array, and data cannot be read, corrected and output in one cycle. In JP-A-11-212877, first, data and parity bits are read out, a part of the data whose error is corrected is replaced with write data, parity bits are regenerated, and only the regenerated parity bits and write data are displayed. Could not write a bit with error corrected.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows. A semiconductor device comprising a plurality of memory cells and an error correction circuit, and reading and writing are completed in one cycle. In the semiconductor device, memory cells sharing the same PWELL on the same word are assigned to different addresses.

  Further, by providing the memory mat with a latch-type sense amplifier, the semiconductor device has a domino-type defect relief circuit that supports the page mode and the burst mode based on the data held in the latch-type sense amplifier. Further, the semiconductor device performs a write operation of data having a value different from the data read once during the write operation.

  As a layout of a plurality of memory cells and an error correction circuit, a plurality of memory mats composed of a plurality of memory cells, a local bus formed in parallel with a word line direction for transferring read data and write data of the memory cells, and write data At least at the intersection of the global bus and the local bus, a global bus for writing parallel to the data line for transferring data from the input pad IO, a global bus for reading parallel to the data line for transferring read data to the output pad IO A configuration including one or more error correction circuits can be given.

  According to the present invention, an increase in area and power consumption can be suppressed, and errors due to soft errors can be corrected.

  Several preferred examples of the semiconductor memory device according to the present invention will be described below with reference to the drawings.

<Example 1>
FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to an SRAM. The SRAM memory with ECC, which is a semiconductor memory device, is divided into a plurality (eight in this embodiment) of memory blocks BLOCK. Each block BLOCK includes a memory array, a latch-type sense amplifier circuit CSA, and a Y switch circuit CYS.

  The memory array includes a memory column A and a memory column B, and the memory column A and the memory column B are assigned to different addresses. For example, when there is one parity bit for every 10-bit unit address, if adjacent memory cells of the same word line are assigned to the same address, the parity bits assigned will overlap if adjacent memory cells are defective. Therefore, the defect cannot be remedied.

  However, when the address is assigned to another address, it is assigned to another parity bit, so that even if a defect occurs in an adjacent memory cell, it can be remedied. Since a soft error is likely to occur in an adjacent memory, it is effective to assign another address to the adjacent column (bit).

  In parallel with the word line, the 138-bit wide local bus and the data line shared by read and write are parallel to the 16-bit wide read data global bus GRBUS and the 16-bit wide write data global bus GWBUS. Is arranged. An error correction block is arranged at the intersection of the local bus and the global bus.

  At the time of reading, only Y column data is output to the local bus LBUS by 138 bits by the Y switch. Of the 138 bits, 128 bits are normal data and 10 bits are parity bits. In the error correction block from 138-bit data, an error of 1 bit or less is corrected and 128-bit data is output, but only the necessary 16 bits are output to the read data global bus GRBUS according to the address. Since the read value is held in the latch type sense amplifier, the output of 128-bit output data of the error correction block is also maintained.

  When an address for reading another bit out of 128-bit data output from the error correction block is input, it is not necessary to access the memory array, and by changing the selection at the output of the error correction block, Page mode can be supported because data can be output at high speed.

  In the page mode, the word line selected by the row address is first fixed (the potential of the word line is selected ("L" or "H")), the column address is changed, and the potential is read and the next Read operation is performed by changing the column address. Since the word line is selected first and the data has already been read out halfway, the word line selection time is not required and high-speed data reading is possible.

  In the present invention, since the 128-bit output of the error correction block is maintained, it is possible to sequentially select and read out the bit lines while the word line is selected, and the page mode can be applied. . Based on the same principle, it is possible to support a burst mode in which a column address (burst address) is automatically generated internally and sequentially read out by one read command.

  In addition, when a multi-bit error occurs across the memory column A and the memory column B on the same word line, the memory column A and the memory column B are corrected separately, so that the error correction circuit block can only correct 1 bit. Even without this, such a multi-bit failure can be corrected.

  A test circuit TEST is connected between the error correction block and the input / output pad IO. The TEST circuit serves to invalidate the error correction circuit. When testing the operation of the memory block, a path that does not pass through the error correction circuit is required. However, this circuit invalidates the error correction circuit with a logic circuit such as a NAND / NOR circuit and does not go through the error correction circuit. It becomes possible to perform writing / reading operations on the cell.

  Writing will be described with reference to FIG. 2 which is an enlarged view of a part of FIG. In the write operation, first, the normal data of 128 bits and the parity bit of 10 bits are read out and output to the local bus LBUS as in the read operation. Based on the read data, the error correction circuit corrects the error and outputs 128 bits. The write data generation circuit replaces 16 bits of write data with a part of 128-bit data and outputs 128 bits. Based on these 128 bits, a parity bit generation circuit generates 10 parity bits. The generated 10 parity bits and 128-bit data are returned to the local bus. However, since the read data remains in the local bus, only the bus corresponding to the 16-bit write data, the 10-bit parity bit, and the 1-bit correction bit whose value has changed is changed.

  Writing to the memory cell is performed when the read data remaining in the latch type sense amplifier and the value of the data input to the local bus are different (16-bit write data bit, 10-bit parity bit, 1-bit correction bit) Only), the write amplifier is activated and writing is performed.

  With the configuration as described above, power during writing can be reduced. In addition, since the 138-bit local bus realizes reading and writing with a common wiring, it is not necessary to provide a bus region up to the chip end, and an increase in area can be reduced.

<Example 2>
FIG. 3 is a circuit diagram showing an embodiment in which the present invention is applied to an SRAM. The semiconductor manufacturing apparatus is formed on a semiconductor substrate such as single crystal silicon. The SRAM memory 200 with ECC, which is a semiconductor memory device, is divided into a plurality (32 in this embodiment) of memory mats MAT. Each memory mat MAT includes a circuit 110 shown in FIG. Eight memory mats MAT constitute one memory block (BLOCK), and a local bus LBUS is arranged at the center of the block.

  In this embodiment, the bus width of the local bus is 138 bits. An error correction block 145 is arranged at a position where the local buses (LBUS0, LBUS1) of the two blocks (BLOCK0, BLOCK1) intersect. Similarly, error correction blocks 153 are arranged at positions where local buses (LBUS2, LBUS3) of two blocks (BLOCK2, BLOCK3) intersect. The error correction block 145 and the error correction block 153 are connected by a read data global bus GRBUS and a write data global bus GWBUS.

  The error correction block 145 selects either the local bus LBUS0 or the local bus LBUS1 based on the error correction circuit 140, the parity bit generation circuit 130, and the selection signal 138, and transfers the data to the error correction circuit 140. A selection circuit 144 that selects the error-corrected data 142 based on the selection signal 146 and outputs it to the read data global bus GRBUS0, and a circuit 143 that generates the write data WDT based on the selection signal 141 The write data drive circuit (133, 134) outputs write data to the local bus LBUS.

  The 2-to-1 selection circuit 137 is a circuit in which a plurality of selection circuits including an AND circuit (AND1, AND2), a NOR circuit NOR0, and an inverter circuit INV8 are arranged, and one of the local buses (LBUS0) is selected by a selection signal 138. , LBUS1) is selected and the data is output to the bus 139.

  In this embodiment, the error correction circuit 140 corrects a 1-bit error using 128-bit data and 10-bit parity bits, and outputs 128-bit data to the bus 142. The selection circuit 144 includes a plurality of selection circuits including N-channel MOS transistors (MN37, MN38), P-channel MOS transistors (MP37, MP38), and inverter circuits (INV10, INV11). The 16-bit data is selected from the 128-bit data from the bus 142 and is output to the read data global bus GRBUS0.

  In the write data generation circuit 143, a plurality of data selection circuits including N-channel MOS transistors (MN35, MN36), P-channel MOS transistors (MP35, MP36), and an inverter circuit INV9 are arranged, read, and errored. 16 bits of the 128-bit data 142 for which is corrected are replaced with the 16-bit data of the write data global bus GWBUS based on the write data selection signal 141, and output to the write data bus WDT.

  The parity bit generation circuit 130 generates 10-bit parity bits used for error correction from the 128-bit write data WDT and outputs them to the write parity bit bus HWDT. The write data drive circuit 134 that outputs write data to the local bus is configured by arranging a plurality of circuits including the clocked inverter circuit CKINV4 and the inverter circuit INV6, and writes the write data WDT and the write parity bit HWDT to the local bus LBUS0. Output based on the data control signal WBC0.

  The write data drive circuit 133 that outputs write data to the local bus is configured by a plurality of circuits including a clocked inverter circuit CKINV5 and an inverter circuit INV7, and writes the write data WDT and the write parity bit HWDT to the local bus LBUS1. Output based on the data control signal WBC1.

  A selection circuit 147 that connects the read data global bus GRBUS0 connected to the error correction block 145 and the read data global bus GRBUS1 connected to the error correction block 153 to the read data global bus GRBUS based on the selection signal 156. Is configured by arranging a plurality of data selection circuits including N-channel MOS transistors (MN39, MN40), P-channel MOS transistors (MP39, MP40), and an inverter circuit INV12.

  The IO output circuit 149 is a circuit that outputs the data of the read data global bus GRBUS to the output pad IO based on the IO enable signal IOEN, and is configured by arranging a plurality of circuits including the clocked inverter CKINV6 and the inverter INV13. Has been.

  The control block 160 selects a word line decode signal WDEC for decoding a word line, a mat decode signal MDEC for decoding a mat (MAT), and a column from an address signal ADD, a chip selection signal CS, and a write selection signal / WE. Y switch decode signal YDEC, write selection signal WE, each selection signal (138, 141, 146), and ATD pulse ATD are generated. Next, the mat MAT circuit 110 will be described with reference to FIG.

  The mat (MAT) is configured by an array block in which a plurality of basic unit units 125 (normal data 128 units, parity bit 10 units, redundant 4 units in this embodiment) are arranged and a control circuit 128.

  The basic unit 125 is composed of a two-column memory cell array. A plurality of memory cells are connected to the data lines (DT0, DB0). For example, the memory cell CELL0 is a flip-flop (P channel type) configured by connecting the input and output of a pair of CMOS inverters to each other. N channel connecting MOS transistor (MP00, MP01), N channel type transistor (MN00, MN01)), and storage node N0 and storage node N1 of the flip-flop to data line (DT0, DB0) It is composed of type MOS transistors (MN03, MN04).

  A word line SWD is connected to the gate electrodes of the N channel type MOS transistors (MN03, MN04). P-channel MOS transistors (MP00, MP01) are formed on the N-type well NWELL0, N-channel transistors (MN00, MN03) are formed on the P-type well PWELL0, and N-channel transistors (MN01, MN04) are P It is formed on the mold well PWELL1.

  The N-type well and the P-type well are insulated by LOCOS (Local Oxidation of Silicon) or trench isolation. A P-type well PWELL0, an N-type well NWELL0, and a P-type well PWELL1 are arranged in this order with LOCOS or trench isolation interposed therebetween, and the N-type well is sandwiched between two P-type wells. Both P-type and N-type wells are semiconductor regions formed on a semiconductor substrate.

  In a layout in which two P-type wells are not used, different conductivity type wells are not arranged in the word line direction, so that soft errors are easily propagated. On the other hand, if this configuration is adopted, wells of different conductivity types are arranged in the word line direction, and insulation is taken between the wells of different conductivity types, so that soft errors are difficult to propagate.

  A plurality of memory cells are connected to the data lines (DT1, DB1). For example, the memory cell CELL1 is a flip-flop (P channel type) configured by connecting the input and output of a pair of CMOS inverters to each other. N-channel connecting MOS transistors (MP10, MP11), N-channel transistors (MN10, MN11)), and storage nodes N2 and N3 of the flip-flop to data lines (DT1, DB1) It is composed of type MOS transistors (MN13, MN14).

  A sub word line SWD is connected to the gate electrodes of the N channel type MOS transistors (MN13, MN14). The P-channel MOS transistors (MP10, MP11) are formed on the N-type well NWELL1, the N-channel transistors (MN10, MN13) are formed on the P-type well PWELL1, and the N-channel transistors (MN11, MN14) are P It is formed on the mold well PWELL2.

  A P-type well PWELL1, an N-type well NWELL1, and a P-type well PWELL2 are arranged in this order with LOCOS or trench isolation interposed therebetween, and the N-type well is sandwiched between two P-type wells. Note that the memory cells CELL0 and CELL1 sharing the PWELL whose gates of the transfer MOSs (MN03, MN04, MN13, and MN14) are connected to the same word line are allocated to different addresses (parity) in advance.

  The basic unit 125 includes a sense amplifier circuit (CSA), a write amplifier circuit (CWA), an equalize / precharge circuit (CEQ0, CEQ1), and a Y switch circuit (CYS0, CYS1). A redundancy shift switch 111 and a redundancy decoding circuit 114 are also included.

  The sense amplifier circuit (CSA) includes a flip-flop composed of P-channel MOS transistors (MP27, MP28) and N-channel MOS transistors (MN25, MN26) and a latch composed of an N-channel MOS transistor MN27 that activates the sense amplifier. Type sense amplifier circuit and switch circuit (MP25, MP26).

  A sense amplifier control signal SE is connected to the gate electrodes of the MOS transistors (MN27, MP25, MP26). In order to precharge the output signals (ST0, SB0) of the sense amplifier, P-channel MOS transistors (MP29, MP30, MP31) are arranged. An equalize / precharge circuit control signal EQ is connected to the gate electrodes of the P-channel MOS transistors (MP29, MP30, MP31).

  The clocked inverter circuit CKINV0 is a circuit that outputs the value of the sense amplifier output SB0 to the local bus LBUS. The clocked inverter circuit CKINV0 is controlled by control signals (RBC, RBCB). The clocked inverter circuit CKINV1 is a circuit that inputs the sense amplifier output ST0 to the write amplifier circuit CWA. The control signal is fixed so that the clocked inverter circuit CKINV1 is always active.

  The Y switch circuit CYS0 is composed of P-channel MOS transistors (MP05, MP06) and N-channel MOS transistors (MN05, MN06) that connect the data lines (DT0, DB0) and the sense amplifier circuit CSA, and control signals (YS, YSB). Controlled by The Y switch circuit CYS1 is composed of P-channel MOS transistors (MP15, MP16) and N-channel MOS transistors (MN15, MN16) that connect the data lines (DT1, DB1) and the sense amplifier circuit CSA, and control signals (YS, YSB). Controlled by

  The write amplifier circuit CWA includes a clocked inverter circuit (CINV2, CINV3), an inverter circuit (INV0, INV1), an AND circuit AND0, and an exclusive OR circuit XOR0. Only when the signal on the local bus LBUS differs from the read data ST0 by the control signal WBC, the data is propagated to the data lines (DT0, DB0).

  The equalize / precharge circuit CEQ0 includes a P-channel MOS transistor MP02 connecting the power supply potential VDD and the data line DT0, a P-channel MOS transistor MP03 connecting the power supply potential VDD and the data line DB0, and a P connecting the data line DT0 and the data line DB0. The channel type MOS transistor MP04 is used. A control signal EQ is connected to the gate electrodes of the P-channel MOS transistors (MP02, MP03, MP04).

  The equalize / precharge circuit CEQ1 includes a P-channel MOS transistor MP12 that connects the power supply potential VDD and the data line DT1, a P-channel MOS transistor MP13 that connects the power supply potential VDD and the data line DB1, and a P that connects the data line DT1 and the data line DB1. It is composed of a channel type MOS transistor MP14. A control signal EQ is connected to the gate electrodes of the P-channel MOS transistors (MP12, MP13, MP14).

  The redundancy shift switch 111 includes N-channel MOS transistors (MN21, MN22, MN23, MN24) and P-channel MOS transistors (MP21, MP22, MP23, MP24). The redundancy decoding circuit 114 includes an inverter circuit INV2 and an OR circuit OR0.

  Under normal conditions, the N-channel MOS transistors (MN21, MN23) and the P-channel MOS transistors (MP21, MP23) are turned on, and the N-channel MOS transistors (MN22, MN24) and the P-channel MOS transistors (MP22, MP24) Is off, and the data on the data lines (DT0, DB0, DT1, DB1) is input to the sense amplifier CSA.

  However, for example, if the memory cell of the basic unit 125 is defective, the shift selection signal 126 turns off the N channel type MOS transistors (MN21, MN23) and the P channel type MOS transistors (MP21, MP23), and the N channel type. The type MOS transistors (MN22, MN24) and the P-channel type MOS transistors (MP22, MP24) are turned on, and the sense amplifier CSA is connected to the data line of the basic unit on the right side by the redundant shift signal lines (RSTR, RSBR). Connected.

  Further, the redundant shift enable signal RDECR becomes HIGH level, and the basic unit on the right side of the basic unit 125 is similarly shifted. When a defect occurs in the memory cell of the basic unit on the left side, the redundant shift enable signal RDECL becomes HIGH level, and the N channel type MOS transistors (MN21, MN23) and the P channel type MOS transistors (MP21, MP23). Is turned off, the N-channel MOS transistors (MN22, MN24) and the P-channel MOS transistors (MP22, MP24) are turned on, and the data on the data lines (DT0, DB0, DT1, DB1) is transferred to the redundant shift signal line ( (RSTL, RSBL) is connected to the left adjacent sense amplifier, and the sense amplifier CSA is connected to the data line of the right adjacent basic unit by a redundant shift signal line (RSTR, RSBR).

  Similarly, the redundancy shift enable signal RDECR becomes HIGH level, and the basic unit on the right side of the basic unit 125 is similarly shifted. Since the 138-bit width data is read, the shift type defect relief circuit as described above is more effective than accessing another mat as in the prior art.

  Next, a case where a read operation is performed will be described with reference to operation waveforms in FIG. When the chip selection signal CS becomes “H” or the address ADD transitions, an ATD pulse is generated and a read operation is started. The equalize / precharge control signal EQ of the mat (MAT) selected by the mat decode signal MDEC becomes the LOW level, and the precharge / equalize of the data lines (DT, DB) is performed. At this time, all the word lines SWD are turned off.

  After precharge / equalization is completed, the selected word line SWD is turned on based on the word line decode signal WDEC, and a potential difference is generated between the data lines (DT, DB). Further, either the data line (DT0, DB0) or the data line (DT1, DB1) is connected to the sense amplifier circuit CSA by the Y switch control signal (YS, YSB) generated by the Y switch decode signal YDEC. . Thereafter, the sense amplifier control signal SE is set to a HIGH level to activate the sense amplifier, and data is output to the local bus LBUS by read data control signals (RBC, RBCB).

  The data output to the local bus LBUS is 128 bits of normal data and 10 bits of parity bits. The data output to the local bus LBUS passes through the selection circuit 137, is input to the error correction circuit 140, the error is corrected, and 128-bit data is output to the data bus 142. Further, 16-bit data is selected by the selection circuit 145, output to the read data global bus GRBUS0, input to the IO output circuit 149 through the selection circuit 147, and output to the output pad IO by the IO enable signal IOEN. .

  Since the data held in the sense amplifier continues to be output to the data bus 142, the address ADD changes in the next cycle so that another 16 bits of the output 128 bits are output to the output pad IO. In this case, data can be output at a higher speed than normal access by simply switching the selection signal 146 without accessing the memory cell.

  Further, the memory cells (CELL0, CELL1) share the P-type well PWELL1, and when α rays are incident on the PWELL1, the data in the memory cell CELL0 and the memory cell CELL1 may be inverted at the same time. However, since the memory cell CELL0 and the memory cell CELL1 sharing the same P-type well are allocated in advance to different addresses (parity) and are not accessed at the same time, an error correction circuit capable of correcting only one bit can be corrected.

  Further, the P-type well PWELL0 and the P-type well PWELL1 are separated by the N-type well NWELL0, and the α ray incident on the P-type well PWELL1 does not affect the P-type well PWELL0, and therefore, the memory cell CELL0 The data of the memory cell on the left side is not affected. Thus, the memory cells CELL that do not share the same P-type well are less likely to fail at the same time, and there is no problem if they are read simultaneously.

  In the present invention, the read operation can be performed in one cycle. One cycle refers to the period from the address change to the next change. From another viewpoint, it can be said that this is the period from the rise (fall) of the word line SWD to the next rise (fall).

Next, a case where a write operation is performed will be described with reference to operation waveforms in FIG.
When the chip selection signal CS becomes “H” or the address transitions, an ATD pulse is generated and a read operation is started. The equalize / precharge control signal EQ of the mat (MAT) selected by the mat decode signal MDEC becomes the LOW level, and the precharge / equalize of the data lines (DT, DB) is performed. At this time, all the word lines SWD are turned off.

  After precharge / equalization is completed, the selected word line SWD is turned on based on the word decode signal WDEC, and a potential difference is generated between the data lines (DT, DB). Also, either the data line (DT0, DB0) or the data line (DT1, DB1) is connected to the sense amplifier circuit CSA by the Y switch control signal (YS, YSB) generated by the Y switch decode signal YDEC. Yes.

  Thereafter, the sense amplifier control signal SE is set to the HIGH level to activate the sense amplifier, and data is output to the local bus LBUS by the read data control signals (RBC, RBCB).

  The data output to the local bus LBUS is 128 bits of normal data and 10 bits of parity bits. The data output to the local bus LBUS passes through the selection circuit 137, is input to the error correction circuit 140, and 128-bit data with the error corrected is output to the data bus 142. The output data is input to the write data generation circuit 143.

  Further, 16-bit write data is input from the input pad IO to the write data generation circuit 143 through the write data global bus GWBUS. Based on the selection signal 141, part of the error-corrected data (16 bits) is replaced with 16-bit write data global bus GWBUS and output as write data WDT.

  The write data WDT is 128-bit data, and the parity bit generation circuit 130 generates 10-bit parity bits. The generated parity bit HWDT and write data WDT are returned to the local bus LBUS by the write data drive circuit 133 by the write data control signal WBC0. Since the read data remains in the local bus, the local bus LBUS corresponding to the data whose value has changed (write data 16 bits from the input pad IO, parity bit 10 bits, error-corrected 1 bit) Only the value changes.

  The write amplifier circuit CWA is activated by the write data control signal WBC, and the read data is held in the latch type sense amplifier CSA. Data line (DT, DB) only when data different from the read data held exists in the local bus LBUS (corresponding to 16 bits of write data from the input pad IO, 10 bits of parity, 1 bit corrected for errors) Is input to the memory cell CELL.

  In this way, when there is no change in data, the local bus LBUS and the data line do not transition, so that power consumption can be reduced. Further, all data returned to the local bus LBUS may be written to the memory cell CELL. In the present invention, the write operation can be performed in one cycle. One cycle refers to the period from the address change to the next change. From another viewpoint, it can be said that this is the period from the rise (fall) of the word line SWD to the next rise (fall).

<Example 3>
The memory mat MAT with shift type defect relief circuit shown in the second embodiment can be replaced with a circuit 210 to which a current relief circuit as shown in FIGS. 7 and 8 is added. 7 and 8 are joined together with AA ′ as a boundary.

  The mat MAT circuit 210 will be described with reference to FIGS. The mat (MAT) includes an array block in which a plurality of basic unit sets SET are arranged, a control circuit 212, and a decoder circuit 213 that specifies a repair set SET.

  The basic unit set SET includes a plurality of units UNIT (in this embodiment, 4 units (UNIT0, UNIT1, UNIT2, UNIT3) and a control circuit SETCNT. The unit UNIT includes a plurality of columns of memory cell arrays (in this embodiment, 2 columns). ), A memory cell power supply circuit 211, an equalize / precharge circuit (CEQ0, CEQ1), a column switch (CRYS0, CRYS1), a sense amplifier CSA, and a write amplifier CWA.

  A plurality of memory cells CELL are connected to the data lines (DT0, DB0). For example, the memory cell CELL0 is a flip-flop (P channel) configured by connecting the input and output of a pair of CMOS inverters to each other. N-type MOS transistors (MP00, MP01), N-channel type transistors (MN00, MN01)), and the flip-flop storage node N0 and storage node N1 are connected to a data line (DT0, DB0). It is composed of channel type MOS transistors (MN03, MN04). A word line SWD is connected to the gate electrodes of the N channel type MOS transistors (MN03, MN04).

  A plurality of memory cells CELL are connected to the data lines (DT1, DB1). For example, the memory cell CELL1 is a flip-flop (P channel) configured by connecting the input and output of a pair of CMOS inverters to each other. N-type MOS transistors (MP10, MP11), N-channel type transistors (MN10, MN11), and the flip-flop storage nodes N2 and N3 are connected to data lines (DT1, DB1). It is composed of channel type MOS transistors (MN13, MN14). A sub word line SWD is connected to the gate electrodes of the N channel type MOS transistors (MN13, MN14).

  The sense amplifier circuit (CSA) includes a flip-flop composed of P-channel MOS transistors (MP27, MP28) and N-channel MOS transistors (MN25, MN26) and a latch composed of an N-channel MOS transistor MN27 for controlling the sense amplifier activity. Type sense amplifier circuit and switch circuit (MP25, MP26). A sense amplifier control signal SE is connected to the gate electrodes of the MOS transistors (MN27, MP25, MP26).

  In order to precharge the output signals (ST0, SB0) of the sense amplifier, P-channel MOS transistors (MP29, MP30, MP31) are arranged. An equalize / precharge circuit control signal EQ is connected to the gate electrodes of the P-channel MOS transistors (MP29, MP30, MP31).

  The clocked inverter circuit CKINV0 is a circuit that outputs the value of the sense amplifier output SB0 to the local bus LBUS. The clocked inverter circuit CKINV0 is controlled by control signals (RBC, RBCB). The clocked inverter circuit CKINV1 is connected to the sense amplifier output ST0. The control signal is fixed so that the clocked inverter circuit CKINV1 is always active.

  The column switch circuit CRYS0 includes P-channel MOS transistors (MP50, MP52) and N-channel MOS transistors (MN50, MN52) that connect the data lines (DT0, DB0) and the sense amplifier circuit CSA, and control signals (NYAT, NYAB). , A P-channel MOS transistor (MP51, MP53) and an N-channel MOS transistor (MP53) that connect the data line (DT0, DB0) and the sense amplifier circuit CSA in the adjacent set (SET (n + 1)). MN51, MN53), and is composed of relief switches controlled by control signals (RYAT, RYAB).

  That is, the first and second sense amplifiers (CSA) are connected to the first data line pair (DT, DB) and the second data line pair (DT, DB) of the two sets SET (n, n + 1), respectively. Nevertheless, the column switch circuit (CRYS) selects either the output of the first data line pair or the output of the second data line pair and inputs it to the first sense amplifier. The output of the first data line pair is selected when there is no defect immediately before the shift direction (n-1) or in its own set (n), and the output of the second data line pair is selected. The case where there is a defect in the front (n-1) in the shifting direction or in its own set (n).

  The column switch circuit CRYS1 is composed of P channel type MOS transistors (MP60, MP62) and N channel type MOS transistors (MN60, MN62) that connect the data lines (DT1, DB1) and the sense amplifier circuit CSA, and control signals (NYBT, NYBB). , A P-channel MOS transistor (MP61, MP63) and an N-channel MOS transistor (MP63) that connect the data line (DT1, DB1) and the sense amplifier circuit CSA in the adjacent set (SET (n + 1)). MN61, MN63), and is composed of relief switches controlled by control signals (RYBT, RYBB).

  The write amplifier circuit CWA includes a clocked inverter circuit (CINV2, CINV3) and an inverter circuit (INV1). Data is propagated to the data lines (DT0, DB0) or the data lines (DT1, DB1) by the control signal WBC.

  The equalize / precharge circuit CEQ0 includes a P-channel MOS transistor MP02 connecting the power supply potential VDD and the data line DT0, a P-channel MOS transistor MP03 connecting the power supply potential VDD and the data line DB0, and a P connecting the data line DT0 and the data line DB0. The channel type MOS transistor MP04 is used. A control signal EQ is connected to the gate electrodes of the P-channel MOS transistors (MP02, MP03, MP04).

  The equalizing / precharging circuit CEQ1 includes a P-channel MOS transistor MP12 that connects the power supply potential VDD and the data line DT1, a P-channel MOS transistor MP13 that connects the power supply potential VDD and the data line DB1, and a P that connects the data line DT1 and the data line DB1. It is composed of a channel type MOS transistor MP14. A control signal EQ is connected to the gate electrodes of the P-channel MOS transistors (MP12, MP13, MP14).

  The memory cell power supply circuit 211 includes a P-channel MOS transistor MP50 that connects the power supply potential VDD and the power supply line VDDM of the memory cell. A signal PWROFF for controlling voltage supply to the memory cell is connected to the gate electrode of the P-channel MOS transistor MP50. In this embodiment, the memory cell power supply circuit 211 is connected between the power supply potential VDD on the high potential side and the power supply line VDDM supplied to the source side of the P-channel MOS transistors (MP00, MP01, MP10, MP11) in the memory cell. It is connected between the power supply potential (ground potential) on the low potential side and the line supplied to the source side of the drive N-channel MOS transistors (MN00, MN01, MN10, MN11) in the memory cell. Also good.

  At this time, the memory cell power supply circuit is composed of an N-channel MOS transistor, and the inverter INV24 is not required, and the output of the NAND gate NAND4 is received as it is. Further, although the area is increased, in order to reliably block current leakage, a memory cell power supply circuit can be provided on both the high potential side and the low potential side.

  In order to reduce the power consumption in the memory cell, a switch consisting of a MOS transistor having a source / drain path is provided between the power supply line and the line that supplies the operating potential of the memory cell. In the case of adopting the configuration of (1), a memory cell power supply circuit is provided between the power supply line not provided with a switch, and a MOS transistor having a conductivity type different from that of the MOS transistor forming the switch is used.

  An N-channel MOS transistor in which a source / drain path is provided between a power supply potential (ground potential) on the low potential side and a driving MOS transistor in the memory cell is considered as a switch for shutting off at the time of standby because of area efficiency. There are many configurations to take. Therefore, if a memory cell power supply circuit is provided between the power supply potential on the low potential side and the driving MOS transistor in the memory cell, two stages of MOS transistors are inserted in series, and the operation speed of the memory cell is suppressed. Therefore, it is advantageous to adopt the configuration of this embodiment in which a memory cell power supply circuit is provided between the high potential side and the load MOS transistor in the memory cell.

  The control circuit SETCNT indicates that the NAND circuit NAND4 that decodes the decode signals (RDEC0, RDEC1, and REN) from the decoder circuit 213 that specifies the repair set SET, and the output of the NAND circuit NAND4 and the set SET (n + 1) are shifted. A circuit AND1 that generates a signal RDECL that is ANDed with the signal RDECR and is transmitted to the set SET (n−1), an inverter circuit INV24 that generates a current relief signal PWROFF by inverting the output of the NAND circuit NAND4, and a signal RDECR A circuit (NAND20, NAND21, NAND2) for controlling the column switch circuit (CRYS0, CRYS1) based on the circuit INV26 for inverting, the OR circuit OR1 for stopping equalization at the time of current relief, and the relief information and the Y selection signals (YSA, YSB) , NAND23, INV20, INV21, INV22, INV23) composed of.

  The control circuit 212 controls the control signals (SWD, EQ, SE, RBC, RBCB, WBC, WBCBYSA, YSB) based on the basic clock ATD, the mat decode signal MDEC, the word line decode signal WDEC, the Y switch decode signal YDEC, and the write selection signal WE. ) Is generated.

  The decoder circuit 213 for designating the repair set SET decodes the decoding circuit Decode based on the signal from the fuse FUSE to generate signals (RDEC0, RDEC1, REN).

  For example, when a memory cell in the set SET (n) is defective, the output of the NAND circuit NAND4 becomes low level “L”, and all the MOS transistors of the column switch circuits (CRYS0, CRYS1) in the set SET (n) In addition, all transistors of the equalize / precharge circuits (CEQ0, CEQ1) are turned off, and the memory cell power supply P-channel MOS transistor (MP50) is also turned off. As a result, power is not supplied to the memory cells in the set SET (n), and current leakage due to defective defects does not flow.

  Also, access is not possible because the column switch is shut off. In the sense amplifier circuit CSA and the write amplifier circuit CWA in the set SET (n), the redundant shift enable signal RDECR becomes LOW level and is connected to the memory cells in the SET (n−1). Further, the sense amplifier circuit CSA and the write amplifier circuit CWA in the set SER (n−1) are connected to the memory cells in the set SER (n−2). Thus, the set on the left side of the set SET (n−1) is similarly shifted. Read and write operations are the same as those in the second embodiment.

  The present invention can be used for an on-chip memory mounted on a semiconductor memory device, particularly an SRAM or a system LSI.

1 is a circuit diagram of a semiconductor device integrated circuit according to Embodiment 1. FIG. 1 is a circuit diagram of a semiconductor device integrated circuit according to Embodiment 1. FIG. 6 is a circuit diagram of a semiconductor device integrated circuit according to Embodiment 2. FIG. 6 is a circuit diagram of a semiconductor device integrated circuit according to Embodiment 2. FIG. 7 is an operation waveform at the time of reading of the semiconductor device integrated circuit according to the second embodiment. 9 is an operation waveform at the time of writing in the semiconductor device integrated circuit according to the second embodiment. 6 is a circuit diagram of a semiconductor device integrated circuit according to Embodiment 3. FIG. 6 is a circuit diagram of a semiconductor device integrated circuit according to Embodiment 3. FIG.

Explanation of symbols

MN: N-channel MOS transistor MN: P-channel MOS transistor CELL ... SRAM memory cell PB ... Parity bit DATA ... Data MCL ... Memory column TEST ... Test circuit INV ... Inverter circuit CKINV ... Clocked inverter circuit NAND ...... NAND circuit AND ... AND circuit NOR ... NOR circuit OR ... OR circuit XOR ... Exclusive OR circuit N ... Connection node VDD ... Power supply potential VSS ... Ground potential MAT, 110 , 210 ... Memory mat MB, BLOCK ... Memory block MCL ... Memory column CSA ... Latch type sense amplifier circuit DT, DB ... Data line SWD ... Word line EQ ... Equalize precharge circuit control signal CEQ ... ... Equalize precharge circuit YS, Y B, YSA ... Y switch control signal CYS ... Y switch circuit SE ... Sense amplifier control signal CSA ... Sense amplifier circuits ST0, SB0 ... Sense amplifier output signal CWA ... Write amplifier circuits RBC, RBCB ... Read data control signal WBC ... ... Write data control signal LBUS ... Local bus DATALBUS ... Data local bus PLBUS ... Parity local bus WDCRT ... Write data generation circuits RDECL, RDECR ... Redundant shift enable signals RSTL, RSBL, RSTR, RSBR ... Redundant shift signal line GRBUS ... Read data global bus GWBUS ... Write data global bus WDT ... Write data HWDT ... Write parity bit IO ... Input / output pad IOE ...... IO enable signal ADD ... Address WE, / WE ... Write selection signal WDEC ... Word line decode signal MDEC ... Matt decode signal YDEC ... Y switch decode signal ATD ... ATD pulse PWELL ... P-type well NWELL ... N-type well 111 ... Redundancy shift circuit 114 ... Redundancy decode circuit 125, UNIT ... Basic unit 126, RDEC, REN ... Shift selection signals 128, 212 ... Control circuit PBCRT, 130 ... Parity bit Generation circuits 133, 134... Write data drive circuits 137, 144, 147... Selection circuits 138, 141, 146, 156... Selection signals 139, 142... Data bus ECCCRT, 140. Data generation circuit ECCBLK, 145, 153 ... Error correction block 149 ... IO output circuit CTLB, 160 ... Control circuit 200 ... SRAM with ECC
SET …… Set SETCNT …… Control circuit PWROFF …… Memory cell voltage power supply control signal VDDM …… Memory cell power supply line 211 …… Memory cell power supply circuit 213 …… Relief set SET designation decoder circuit FUSE …… Fuses NYA, NYB …… Column switch control signals RYA, RYB ... Column switch control signal CRYS ... Column switch circuit.

Claims (10)

A word line,
A first memory cell and a second memory cell connected to the word line;
A first data line pair connected to the first memory cell;
A second data line pair connected to the second memory cell;
The first memory cell includes
A first CMOS inverter having an N-channel first MOS transistor and a P-channel second MOS transistor;
A second CMOS inverter having an N-channel third MOS transistor and a P-channel fourth MOS transistor;
An N-channel first transfer MOS transistor provided between the output of the first CMOS inverter and one of the first data line pair;
An N-channel second transfer MOS transistor provided between the output of the second CMOS inverter and the other of the first data line pair;
The outputs and inputs of the first and second CMOS inverters are connected to each other,
The second memory cell includes
A third CMOS inverter having an N-channel fifth MOS transistor and a P-channel sixth MOS transistor;
A fourth CMOS inverter having an N-channel seventh MOS transistor and a P-channel eighth MOS transistor;
An N-channel third transfer MOS transistor provided between the output of the third CMOS inverter and one of the second data line pairs;
An N-channel fourth transfer MOS transistor provided between the output of the fourth CMOS inverter and the other of the second data line pair;
The outputs and inputs of the third and fourth CMOS inverters are connected to each other,
The first MOS transistor and the first transfer MOS transistor are formed in a first P-type well,
The second MOS transistor and the fourth MOS transistor are formed in a first N-type well,
The third MOS transistor, the second transfer MOS transistor, the fifth MOS transistor, and the third transfer MOS transistor are formed in a second P-type well,
The sixth MOS transistor and the eighth MOS transistor are formed in a second N-type well,
The seventh MOS transistor and the fourth transfer transistor are formed in a third P-type well,
The first N-type well is provided between the first P-type well and the second P-type well,
The second N-type well is provided between the second P-type well and the third P-type well,
The semiconductor device, wherein the first memory cell and the second memory cell are assigned to different addresses and error-corrected at different timings. The semiconductor device according to claim 1.
The semiconductor device includes a local data line connected to the first data line pair and the second data line pair;
A first Y switch circuit provided between the first data line pair and the local data line pair;
A second Y switch circuit provided between the second data line pair and the local data line pair;
The semiconductor device, wherein the first Y switch circuit and the second Y switch circuit are not selected in parallel. The semiconductor device according to claim 2.
The semiconductor device further comprises a sense amplifier circuit provided between the first and Y-th switch circuits and the local data line. The semiconductor device according to claim 2 or 3,
The semiconductor device further comprises an error correction circuit connected to the local data line. The semiconductor device according to any one of claims 2 to 4,
The semiconductor device further includes a global bus connected to the error correction circuit,
The semiconductor device according to claim 1, wherein a bus width of the global bus is smaller than a bus width of the local bus. In claim 5,
The global bus extends in a direction in which the first and second data line pairs extend. In any one of Claims 2 thru | or 6,
The semiconductor device, wherein the local bus extends in a direction in which the word line extends. Multiple word lines,
A plurality of memory cells connected to the plurality of word lines,
Each of the plurality of memory cells is formed in two P-type wells provided on a semiconductor substrate and an N-type well sandwiched between the two P-type wells,
Two adjacent memory cells among the plurality of memory cells share one P-type well of the two P-type wells,
2. A semiconductor device characterized in that two memory cells sharing one P-type well among the two P-type wells are assigned to different addresses and error-corrected at different timings. In claim 8,
One of the two memory cells sharing one of the two P-type wells is connected to the first data line pair,
The other of the two memory cells sharing one of the two P-type wells is connected to the second data line pair,
The semiconductor device, wherein the first data line pair and the second data line pair are not selected in parallel. In claim 9,
A local bit line connected to the first data line pair and the second data line pair;
A semiconductor device, further comprising an error correction circuit connected to the local bit line pair.

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