JP4296242B2 - Option setting circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an option setting circuit for outputting a mode signal for setting an optional function in an integrated circuit (hereinafter referred to as “IC”).
[0002]
[Prior art]
The degree of integration of ICs has been improved, and there is an increasing number of ICs having a plurality of functions. For example, in an IC such as a microcomputer, a function for performing a normal operation and a function for an in-circuit emulator are formed on one chip so as to reduce the development cost and the development schedule. When such an IC is actually used, only one of the two functions is used according to the purpose. For this purpose, an option setting circuit for outputting a mode signal for setting an optional function is provided on the IC, and the level of the mode signal is set to “L” or “H” at the final stage of the manufacturing process. Yes.
[0003]
FIG. 2 is a circuit diagram showing an example of a conventional option setting circuit.
The option setting circuit includes P-channel MOS transistors (hereinafter referred to as “PMOS”) 1 and 2 and N-channel MOS transistors (hereinafter referred to as “NMOS”) 3 and 4. The sources of the PMOSs 1 and 2 are connected to the power supply potential VDD, and the drains are connected to the drains of the NMOSs 3 and 4, respectively. The sources and gates of the NMOSs 3 and 4 are connected to the ground potential GND. The gate of the PMOS 2 is connected to the drain of the NMOS 3. Further, the gate of the PMOS 1 is connected to the drain of the NMOS 4, that is, the node N1, and the mode signal MOD for setting the operation mode is output from the node N1.
[0004]
In such an option setting circuit, the mode signal MOD is set to “H” or “L” by implanting ions into one of the gates of the NMOSs 3 and 4 to form a depletion type.
For example, when the NMOS 4 is made a depletion type, the NMOS 4 is always turned on. Since the NMOS 3 is in the OFF state, the mode signal MOD at the node N1 is set to “L”. Further, when the NMOS 3 is of a depletion type, the mode signal MOD is set to “H”.
[0005]
However, the conventional option setting circuit has the following problems.
That is, since the gates of the NMOSs 3 and 4 are directly connected to the ground potential GND of the power supply system, there is a problem that the gate oxide film is destroyed.
In addition, depending on the design process, there is a problem that the step of ion implantation to the gates of the NMOSs 3 and 4 may not be used.
[0006]
The present invention provides an option setting circuit that solves the problems of the prior art, does not cause destruction of a gate oxide film, and can set a mode signal without using ion implantation. is there.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, according to a first aspect of the present invention, in an option setting circuit, the source is connected to the power supply potential, the drain is connected to the first node, and the gate is connected to the second node. The first transistor, the source connected to the ground potential, the drain connected to the second node, the gate connected to the first node, the source connected to the power supply potential, and the drain and gate connected to the first node. A pattern connection unit that connects a third transistor connected to each node to one of the first and second nodes by a wiring pattern and outputs the potential of the node as a mode signal for option setting And.
[0008]
According to a second aspect of the present invention, in the option setting circuit, a third transistor having the same transistors as the first aspect, a source connected to the ground potential, and a drain and a gate connected to the second node, respectively. A transistor and a pattern connecting portion similar to the first invention are provided.
[0009]
According to a third aspect, in the option setting circuit according to the second aspect, a fourth transistor having a source connected to a power supply potential and a drain and a gate connected to the first node is provided.
[0010]
According to the first to third aspects, since the option setting circuit is configured as described above, the following operation is performed.
When the power is turned on, the third (and fourth) transistor is turned on, the first node becomes the power supply potential, and the second node becomes the ground potential. As a result, the first and second transistors are turned on, and the potentials of the first and second nodes are determined. One of the first and second nodes is connected by a wiring pattern in the pattern connecting portion, and the potential of the connected node is output as a mode signal.
[0011]
According to a fourth aspect of the present invention, in the option setting circuit, the same transistors as the first aspect, the source is connected to the power supply potential, the drain is connected to the first node, and the control signal is connected to the gate. A third transistor is provided, and a pattern connection portion similar to that of the first invention is provided.
[0012]
According to a fifth aspect of the present invention, in the option setting circuit, the first and second transistors similar to the first aspect, the source is connected to the ground potential, the drain is connected to the second node, and the control signal is supplied to the gate. A third transistor is provided, and a pattern connection portion similar to that of the first invention is provided.
[0013]
According to the fourth and fifth inventions, the following operation is performed.
When a control signal is supplied to the gate of the third transistor, the third transistor is turned on, and the potentials of the first and second nodes are determined. One of the first and second nodes is connected by a wiring pattern in the pattern connecting portion, and the potential of the connected node is output as a mode signal.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 is a circuit diagram of an option setting circuit showing a first embodiment of the present invention.
This option setting circuit includes PMOS 11 and 12, NMOS 13, and pattern connection unit 20.
[0015]
The source of the PMOS 11 is connected to the power supply potential VDD, the drain is connected to the node NH, and the gate is connected to the node NL. The source of the PMOS 12 is connected to the power supply potential VDD, and the drain and gate are connected to the node NH. The drain of the NMOS 13 is connected to the node NL, the gate is connected to the node NH, and the source is connected to the ground potential GND.
[0016]
The pattern connection unit 20 is a place for pattern connection for setting the mode signal MOD to “H” or “L” in the final stage of the IC manufacturing process. The pattern connection unit 20 is connected to the node NH. And a pattern c for outputting a mode signal MOD. One of the patterns a and c or the patterns b and c is connected by contact or metal wiring. The pattern c of the pattern connection unit 20 is connected to the input side of the option circuit.
[0017]
Next, the operation will be described.
Before the power supply voltage VDD is applied, the nodes NH and NL are both “L”. Here, when the power supply voltage VDD is applied, the PMOS 12 is turned on. As a result, the node NH is raised to “H”, the NMOS 13 is turned on, and the node NL is maintained at “L”. Further, the PMOS 11 is turned on.
[0018]
The levels of the nodes NH and NL are output to the patterns a and b of the pattern connection unit 20. The mode signal MOD set in the pattern connection unit 20 is output from the pattern c connected to one of the patterns a and b by the pattern connection unit 20.
[0019]
As described above, the option setting circuit of the first embodiment includes the PMOS 12 that is turned on when the power is turned on, and connects the output-side nodes NL and NH to the gates of the PMOS 11 and the NMOS 13, respectively. Thereby, the power supply system is not directly connected to the gate, and there is no possibility that the gate oxide film is destroyed. Further, the number of transistors is smaller than that in FIG. 2, and the circuit can be simplified. Further, since the pattern connection unit 20 can set a mask option based on a contact or a wiring layer, it can set an arbitrary mode signal MOD regardless of the manufacturing process (that is, no ion implantation step is required). Can do.
[0020]
(Second Embodiment)
FIG. 3 is a circuit diagram of an option setting circuit showing a second embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.
This option setting circuit includes a PMOS 11, NMOSs 13 and 14, and a pattern connection unit 20.
[0021]
The source of the PMOS 11 is connected to the power supply potential VDD, the drain is connected to the node NH, and the gate is connected to the node NL. The drain of the NMOS 13 is connected to the node NL, the gate is connected to the node NH, and the source is connected to the ground potential GND. The drain and gate of the NMOS 14 are connected to the node NL, and the source is connected to the ground potential GND. Moreover, the pattern connection part 20 is the same as that of FIG.
[0022]
In such an option setting circuit, when the power supply voltage VDD is applied, the NMOS 14 is turned on. As a result, the node NL is pulled down to “L”, the PMOS 11 is turned on, and the node NH is pulled up to “H”. Also, the NMOS 13 is turned on. The levels of the nodes NH and NL are output to the patterns a and b of the pattern connection unit 20, and the mode signal MOD set by the pattern connection unit 20 is output from the pattern c.
[0023]
As described above, the option setting circuit of the third embodiment has the NMOS 14 that is turned on when the power is turned on, and connects the output-side nodes NH and NL to the gates of the NMOS 13 and the PMOS 11, respectively. This has the same advantage as the first embodiment.
[0024]
(Third embodiment)
FIG. 4 is a circuit diagram of an option setting circuit showing a third embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.
This option setting circuit includes PMOS 11 and 12, NMOS 13 and 14, and a pattern connection unit 20.
[0025]
The sources of the PMOSs 11 and 12 are connected to the power supply potential VDD, and the drains are connected to the node NH. The gates of the PMOSs 11 and 12 are connected to the nodes NL and NH, respectively. On the other hand, the drains of the NMOSs 13 and 14 are connected to the node NL, and the sources are connected to the ground potential GND. The gates of the NMOSs 13 and 14 are connected to the nodes NH and NL, respectively. The pattern connecting unit 20 is the same as that shown in FIG.
[0026]
In such an option setting circuit, when the power supply voltage VDD is applied, the PMOS 12 and the NMOS 14 are turned on, the node NL is pulled down to “L”, and the node NH is pulled up to “H”. As a result, the PMOS 11 and the NMOS 13 are turned on. The levels of the nodes NH and NL are output to the patterns a and b of the pattern connection unit 20, and the mode signal MOD set by the pattern connection unit 20 is output from the pattern c.
[0027]
As described above, the option setting circuit of the third embodiment includes the PMOS 12 and the NMOS 14 that are turned on when the power is turned on, and connects the nodes NL and NH on the output side to the gates of the PMOS 11 and the NMOS 13, respectively. . Thereby, the level setting at the time of turning on the power becomes stable and reliable, and the response speed becomes faster. Further, since the power supply system is not directly connected to the gate, there is no possibility that the gate oxide film is broken. Furthermore, since the pattern connection unit 20 can set a mask option based on a contact or a wiring layer, an arbitrary mode signal MOD can be set regardless of the manufacturing process.
[0028]
(Fourth embodiment)
FIG. 5 is a circuit diagram of an option setting circuit showing a fourth embodiment of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.
In this option setting circuit, the connection destination of the gate of the PMOS 12 in FIG. 1 is changed from the node NH to the terminal 15 to which the reset signal RST is applied. Other configurations are the same as those in FIG.
[0029]
In such an option setting circuit, when the reset signal RST at the terminal 15 is “H” when the power supply voltage VDD is applied, the PMOS 12 is turned off, and the PMOS 11 and the NMOS 13 are in an unstable state. The levels of NH and NL are not fixed.
[0030]
Next, when the reset signal RST becomes “L”, the PMOS 12 is turned on, the node NH becomes “H”, the NMOS 13 turns on, and the node NL becomes “L”. Further, the PMOS 11 is turned on. The levels of the nodes NH and NL are output to the patterns a and b of the pattern connection unit 20, and the mode signal MOD set by the pattern connection unit 20 is output from the pattern c.
Thereafter, even if the reset signal RST becomes “H”, the on state of the PMOS 11 and the NMOS 13 does not change, and the level of the mode signal MOD is maintained as it is.
[0031]
As described above, the option setting circuit of the fourth embodiment has the PMOS 12 controlled by the reset signal RST, and connects the output-side nodes NL and NH to the gates of the PMOS 11 and the NMOS 13, respectively. Thus, in addition to the advantages of the first embodiment, it becomes possible to synchronize the entire circuit and to stabilize the operation.
[0032]
(Fifth embodiment)
FIG. 6 is a circuit diagram of an option setting circuit showing a fifth embodiment of the present invention. Elements common to those in FIG. 3 are denoted by common reference numerals.
In this option setting circuit, the connection destination of the gate of the NMOS 14 in FIG. 3 is changed from the node NL to the terminal 15 to which the reset signal RST is applied. Other configurations are the same as those in FIG.
[0033]
In such an option setting circuit, when the reset signal RST at the terminal 15 is “L” when the power supply voltage VDD is applied, the NMOS 14 is turned off, the PMOS 11 and the NMOS 13 are unstable, and the node The levels of NH and NL are not fixed.
[0034]
Next, when the reset signal RST becomes “H”, the NMOS 14 is turned on, the node NL becomes “L”, the PMOS 11 is turned on, and the node NH becomes “H”. Further, the NMOS 13 is turned on. The levels of the nodes NH and NL are output to the patterns a and b of the pattern connection unit 20, and the mode signal MOD set by the pattern connection unit 20 is output from the pattern c.
Thereafter, even if the reset signal RST becomes “L”, the on state of the PMOS 11 and the NMOS 13 does not change, and the level of the mode signal MOD is maintained as it is.
[0035]
As described above, the option setting circuit of the fifth embodiment has the NMOS 14 controlled by the reset signal RST, and connects the output-side nodes NL and NH to the gates of the PMOS 11 and the NMOS 13, respectively. As a result, in addition to the advantages of the second embodiment, it becomes possible to synchronize the entire circuit and to stabilize the operation.
[0036]
【The invention's effect】
As described above in detail, according to the first and second aspects of the invention, the third transistor that is turned on when the power is turned on has the third and second nodes on the output side. 1 is connected to the gate of the transistor. Thereby, the power supply system is not directly connected to the gate of the transistor, and there is no possibility that the gate oxide film is broken. Further, since the pattern connection portion can set a mask option based on a contact or a wiring layer, an arbitrary mode signal can be set regardless of the manufacturing process.
[0037]
According to the third invention, a fourth transistor that is turned on when the power is turned on is added to the second invention. Thereby, in addition to the effects of the second invention, stable operation and improved set speed can be achieved.
[0038]
According to the fourth and fifth inventions, the third transistor that is turned on when the control signal is applied is provided, and the first and second nodes on the output side are respectively connected to the second and first transistors. Connected to the gate. As a result, the circuit operation can be synchronized, and the power supply system is not directly connected to the gate of the transistor, so that there is no possibility that the gate oxide film is destroyed. Further, since the pattern connection portion can set a mask option based on a contact or a wiring layer, an arbitrary mode signal can be set regardless of the manufacturing process.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an option setting circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of a conventional option setting circuit.
FIG. 3 is a circuit diagram of an option setting circuit showing a second embodiment of the present invention.
FIG. 4 is a circuit diagram of an option setting circuit showing a third embodiment of the present invention.
FIG. 5 is a circuit diagram of an option setting circuit showing a fourth embodiment of the present invention.
FIG. 6 is a circuit diagram of an option setting circuit showing a fifth embodiment of the present invention.
[Explanation of symbols]
11,12 PMOS
13,14 NMOS
15 Terminal 20 Pattern connection

Claims (5)

A first transistor having a source connected to a power supply potential, a drain connected to a first node, and a gate connected to a second node;
A second transistor having a source connected to a ground potential, a drain connected to the second node, and a gate connected to the first node;
A third transistor having a source connected to a power supply potential and a drain and a gate connected to the first node;
A pattern connection unit that connects either the first or second node according to a wiring pattern and outputs the potential of the node as a mode signal for option setting;
An option setting circuit characterized by comprising. A first transistor having a source connected to a power supply potential, a drain connected to a first node, and a gate connected to a second node;
A second transistor having a source connected to a ground potential, a drain connected to the second node, and a gate connected to the first node;
A third transistor having a source connected to ground potential and a drain and gate connected to the second node;
A pattern connection unit that connects either the first or second node according to a wiring pattern and outputs the potential of the node as a mode signal for option setting;
An option setting circuit characterized by comprising. 3. The option setting circuit according to claim 2, further comprising a fourth transistor having a source connected to a power supply potential and a drain and a gate connected to the first node. A first transistor having a source connected to a power supply potential, a drain connected to a first node, and a gate connected to a second node;
A second transistor having a source connected to a ground potential, a drain connected to the second node, and a gate connected to the first node;
A third transistor having a source connected to a power supply potential, a drain connected to the first node, and a gate supplied with a control signal;
A pattern connection unit that connects either the first or second node according to a wiring pattern and outputs the potential of the node as a mode signal for option setting;
An option setting circuit characterized by comprising. A first transistor having a source connected to a power supply potential, a drain connected to a first node, and a gate connected to a second node;
A second transistor having a source connected to a ground potential, a drain connected to the second node, and a gate connected to the first node;
A third transistor having a source connected to a ground potential, a drain connected to the second node, and a gate supplied with a control signal;
A pattern connection unit that connects either the first or second node according to a wiring pattern and outputs the potential of the node as a mode signal for option setting;
An option setting circuit characterized by comprising.

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