JP4297211B2 - Function simulation method of system composed of hardware and software - Google Patents

Description

ソースコードファイル３１のクラスＩｎｔ３２のオブジェクト作成部３２１では、クラスＩｎｔ３２のオブジェクトを作成する。クラスＩｎｔ３２のオブジェクト作成部３２１は、例えば
Int32 d, e, f;
と記述される。これにより、クラスInt32のオブジェクトd、e及びfが作成される。
【００２７】
データ処理部３３１は作成されたオブジェクトに対するデータ処理であり、例えば
d = e + f;
と記述される。
【００２８】
この加算を実行すると、クラスＩｎｔ３２の定義部３０１により通常の加算が行なわれ、さらにｓｐｅｎｄ＿ｔｉｍｅ（１０）が読み出されるので、これをハードウエアブロックまたはソフトウエアによる加算時間に対応させることができる。
【００２９】
オブジェクト作成後は、どの箇所で該オブジェクトに対し加算演算を行なってもｓｐｅｎｄ＿ｔｉｍｅ（１０）が実行され、ソースコードファイル３１に関数ｓｐｅｎｄ＿ｔｉｍｅを直接記述する必要がない。また、シミュレーション結果に基づいて上述のように処理をハードウエアの一部とソフトウエアの一部を一方から他方へ置き換えたり、ハードウエアの一部又は全部の処理速度を変更したりする場合には、関数ｓｐｅｎｄ＿ｔｉｍｅ（ｘ）の引数値ｘを変えるだけでよい。したがって、モデルの作成及び修正が容易になる。
【００３０】
同様に、アーキテクチャ定義部３０２は、６４ビット整数の加算と、その実行に要する時間とを定義するものであり、クラスＩｎｔ６４の宣言と、このクラスのメンバー関数である‘＋’演算子関数の定義とからなる。この関数内では、関数ｓｐｅｎｄ＿ｔｉｍｅ（２０）を呼び出している。
【００３１】
この引数値がアーキテクチャ定義部３０１のそれと異なるので、アーキテクチャ定義部３０２をアーキテクチャ定義部３０１とは異なるハードウエアブロックの処理に対応させることができる。また、クラスＩｎｔ３２のオブジェクト作成部３２１を、クラスＩｎｔ６４のオブジェクト作成部に変更すれば、データ処理部３３１での処理時間が変わる。したがって、オブジェクト作成部を変更するだけでモデルを容易に修正することが可能となる。
【００３２】
上記同様に、アーキテクチャ定義部３０３は、３２ビット浮動小数点数の乗算とその実行に要する時間とを定義するものであり、アーキテクチャ定義部３０４は、６４ビット浮動小数点数の乗算とその実行に要する時間とを定義するものである。
【００３３】
図３ではクラスＩｎｔ３２のオブジェクト作成部３２１とクラスＦｌｔ３２のオブジェクト作成部３２２とを分離して記述しているが、両オブジェクト作成部を纏めて１ヵ所に記述してもよいことは勿論である。
【００３４】
図３の例では、加算演算に対し異なる引数値ｘのｓｐｅｎｄ＿ｔｉｍｅ（ｘ）を対応させるために、引数値ｘの数だけ同様のクラスを宣言しそのメンバ関数を定義しなければならない。
【００３５】
次に、図４を参照して、１つのクラスＩｎｔ３２の宣言で複数の引数値ｘのｓｐｅｎｄ＿ｔｉｍｅ（ｘ）を間接的かつ選択的に呼び出す場合を説明する。
【００３６】
この場合、クラスＩｎｔ３２とは別に、引数値ｘの異なるｓｐｅｎｄ＿ｔｉｍｅ（ｘ）を呼び出す複数のクラスを宣言しておき、これらのクラスの１つをポインタで指定することにより、１つのクラスＩｎｔ３２の定義で複数の引数値ｘのｓｐｅｎｄ＿ｔｉｍｅ（ｘ）を間接的かつ選択的に呼び出す。
【００３７】
アーキテクチャ定義ファイル３０Ａのアーキテクチャ定義部３０１Ａにおいて、クラスＩｎｔ３２が宣言され、‘＋’演算子関数が定義され、この関数内でポインタを使って基本クラスＡｒｃのメンバ関数ｆ（）を呼び出している。ｆ（）＝０の‘＝０’は仮想関数であることを示している。この関数内には、関数ｓｐｅｎｄ＿ｔｉｍｅ（ｘ）の呼び出しは無く、基本クラスＡｒｃに対する派生クラスＡｒｃ１及びＡｒｃ２の各々において、互いに異なる引数値ｘをもつｓｐｅｎｄ＿ｔｉｍｅ（ｘ）を呼び出している。
【００３８】
ソースコードファイル３１Ａの派生クラス指定・オブジェクト作成部３２１Ａにおいて、基本クラスＡｒｃの静的メンバであるポインタに派生クラスＡｒｃ２のアドレスを格納することにより派生クラスＡｒｃ２を指定し、クラスＩｎｔ３２のオブジェクトを作成する。これにより、ソースコードファイル３１Ａのデータ処理部３３１での加算において、ｓｐｅｎｄ＿ｔｉｍｅ（４０）が実行される。
【００３９】
アーキテクチャ定義部３０１Ａの具体例は次の通りである。

上記関数Int32_Add_Cost()は、図４中の関数ｆ（）に対応している。
【００４０】
基本クラスＡｒｃの宣言部４１の具体例は次の通りである。

上記具体例において、std::map< Task*, Arch* > task_arch_mapは、Taskクラスあるいはその派生クラスオブジェクトへのポインタと、Archクラスあるいはその派生クラスオブジェクトへのポインタとの関連を格納するテーブルであり、各タスクがある時点で利用しているアーキテクチャを記録する。
【００４１】
task_arch_map(Task::crnt_task()) = archは、これを実行しているタスクをスレッド管理機能から入手し、そのタスクとarchで示すアーキテクチャとの関連をテーブルに格納することを意味している。
【００４２】
派生クラスＡｒｃ１の宣言部４２及び派生クラスＡｒｃ２の宣言部４３の具体例は次の通りである。

クラスＩｎｔ３２のオブジェクト作成部３２１の具体例は次の通りである。

データ処理部３３１の具体例は次の通りである。
【００４３】
d = e + f;
次に、他の具体例を説明する。
【００４４】
以上の例を拡張して、データ処理部３３に演算式を記述するだけで、データを受信し演算する処理又はデータを演算しその結果を転送する処理、例えば図２のハードウエアブロック２６と２７との間、ハードウエアブロック２５と２８の間、又は、ハードウエアブロック２５と２９との間で所定量のデータを送受しその後で演算を行う処理を表すことができる。この場合、演算子関数において、どのハードウエアブロック間であるかにより異なるデータ送受時間に対応したｓｐｅｎｄ＿ｔｉｍｅ（ｘ）を呼び出す。引数値ｘは、予め設定しておいたArch間の関連から得るためのテーブルに格納している。以下にその具体例を示す。
【００４５】
アーキテクチャ定義ファイル３０１Ａのクラス宣言部の具体例は次の通りである。

上記具体例において、‘＝’演算子関数operator=は、左辺値の存在するArchを最新のArchに設定することを意味している。これにより、＝の左辺のオブジェクトが、それを呼び出したアーキテクチャに設定される。
【００４６】
std::map< Arch*, int > transfer_cost_tableは、各アーキテクチャ（ハードウエアブロック）毎に持っている、他アーキテクチャとの間の通信コスト（通信時間）を格納するテーブルであり、Archクラスあるいはその派生クラスオブジェクトへのポインタを与えることで通信コストを得ることができる。
【００４７】
transfer_cost_table[a] = cは、各アーキテクチャ毎に持っている、他アーキテクチャとの間の通信コスト（通信時間）格納テーブルに対し、アーキテクチャａとの通信コストがｃであることを設定している。
【００４８】
crnt_arch()は、Archクラスの静的メンバ関数であり、それを呼び出したタスクをスレッド管理機能から得、それとArchクラスの静的メンバであるtask_arch_mapとから、呼び出したタスクがその時点で利用しているアーキテクチャを得るために用いる。
【００４９】
データ処理部３３１の具体例は次の通りである。

上記具体例において、B.Set_Trans_Cost(&A, 100)は、通信コストテーブルに、アーキテクチャＢのアーキテクチャＡとの通信コストが１００であることを設定している。
【００５０】
次に、システムモデル１３の評価方法について説明する。
【００５１】
システムモデル１３には、互いに並列処理されるタスクが記述されており、シミュレータ１２Ａはこれに基づいてマルチタスクを実行するシミュレーションを行う。モデルのソースコードファイル３１において、各ハードウエアブロックの動作開始及び終了時点でそのブロック名をメモリに格納しておき、シミュレーション終了後にこれを読み出すことにより図５に示すような並列処理結果が得られる。
【００５２】
図５中のＡ〜Ｃは、図２中のハードウエアブロックに記載した記号であり、例えばブロックＡの矩形はブロックＡの動作期間を示している。ブロックＡ〜Ｃの同時刻最大使用数はそれぞれ２、２及び１であり、ブロックのＡ〜Ｃのハードウエア価格をそれぞれ例えば１００、２０００及び１０とすると、周辺装置の価格見積値は１００×２＋２０００×２＋１０×１＝４２１０となる。この価格と、処理時間２５の要求値に対する％とから、システムの構成がリーズナブルであるかどうかを評価することができる。
【００５３】
また、ブロックＡ〜Ｃの使用電力をそれぞれ例えば１０Ｗ、２００Ｗ及び１Ｗとすると、システムの最大使用電力見積値は４００Ｗとなり、これと、処理時間２５の要求値に対する％とから、システムの構成がリーズナブルであるかどうかを評価することができる。最大使用電力の替わりに、平均電力を用いてもよい。
【００５４】
以上の説明から明らかなように、本発明には以下の付記が含まれる。
【００５５】
（付記１）機能シミュレーション対象の、ハードウェアとソフトウエアとで構成されるシステムモデルをコンピュータプログラムで作成する方法であって、該コンピュータプログラムは、
演算子を多重定義する演算子関数と演算対象の変数とを含み該関数に所定時間を費やす演算コスト関数の呼び出しを含むアーキテクチャクラスを宣言し該演算子関数及び該演算コスト関数を定義するアーキテクチャ定義部と、
該クラスのオブジェクトを作成する宣言部と、
該システムの動作を表すためにオブジェクト間の演算を行う処理部と、
を有し、該所定時間はソフトウエア又はハードウエアの演算実行時間に相当し、該システムのアーキテクチャに応じて該所定時間が異なり、該システムのアーキテクチャ変更に対し該処理部の内容を変えずに該所定時間の値を変更することを特徴とする機能シミュレーション対象モデル作成方法。（１）
（付記２）該システムのアーキテクチャに応じて該所定時間が互いに異なる該クラスを同一演算子に対し複数有し、
該システムのアーキテクチャ変更に対し該処理部の内容を変えずに該宣言部の記述を変更することを特徴とする付記１記載の機能シミュレーション対象モデル作成方法。（２）
（付記３）該アーキテクチャ定義部はさらに、該演算コスト関数を含む基本クラスの宣言と、該所定時間を定めるために該基本クラスに対し該演算コスト関数を上書きする、該所定時間の値毎の派生クラスの宣言とを含み、
アーキテクチャに応じた所定時間をもつ演算コスト関数の呼び出しを行うオブジェクトが該宣言部で作成されるように派生クラスのオブジェクトを指定する呼び出し関数指定部をさらに有することを特徴とする付記１記載の機能シミュレーション対象モデル作成方法。（３）
（付記４）該アーキテクチャクラスはさらに、データ転送時間に対応した所定時間を費やす転送コスト関数の呼び出しを含み、
該オブジェクトの間の演算を、データを受信して演算し又はデータを演算して送信する動作に対応させることを特徴とする付記１乃至３のいずれか１つに記載の機能シミュレーション対象モデル作成方法。（４）
（付記５）該プログラムの言語はＣ＋＋であることを特徴とする付記１乃至４のいずれか１つに記載の機能シミュレーション対象モデル作成方法。
【００５６】
（付記６）該コンピュータプログラムは、並列処理される複数のタスクを有することを特徴とする付記１乃至５のいずれか１つに記載の機能シミュレーション対象モデル作成方法。
【００５７】
（付記７）各タスクは、使用中のハードウエア構成ブロックの種別を示すデータを出力するコードを含むことを特徴とする付記６記載の機能シミュレーション対象モデル作成方法。
【００５８】
（付記８）（ａ）付記７記載の方法で作成された該システムモデルをシミュレータで所定期間動作させ、動作中に出力される、該使用中のハードウエア構成ブロックの種別を示すデータを記憶装置に格納しておき、
（ｂ）該所定期間経過後に該データを該記憶装置から読み出して、各時刻で使用中のハードウエア構成ブロックの種別と数を求め、
（ｃ）該種別と数とに基づいて該アーキテクチャを評価することを特徴とする機能シミュレーション対象モデル評価方法。（５）
（付記９）該ステップ（ｃ）では、同時に使用される同種ハードウエア構成ブロックの最大個数を求め、ハードウエア構成ブロックの種別毎の価格と該種別のハードウエア構成ブロックの同時使用最大個数との積の総和を該システムのハードウェア価格と見積もることを特徴とする付記８記載の機能シミュレーション対象モデル評価方法。
【００５９】
（付記１０）該記憶装置には、ハードウエア構成ブロックの種別毎の消費電力値が格納されており、
該ステップ（ｃ）では、各時刻で使用されているハードウエア構成ブロックの種別と個数と消費電力値とに基づいて該ハードウェアの消費電力を評価値として見積もることを特徴とする付記８記載の機能シミュレーション対象モデル評価方法。
【図面の簡単な説明】
【図１】本発明の、機能設計されたハードウエアとソフトウエアとからなるシステムモデルの評価説明図である。
【図２】該ハードウエアとソフトウエアとからなるシステムの構成例を示す概略ブロック図である。
【図３】アーキテクチャ定義ファイル及びソースコードファイルのより具体的な構成例を示す図である。
【図４】演算子関数を含む１つのクラスで複数の引数値ｘの関数ｓｐｅｎｄ＿ｔｉｍｅ（ｘ）を間接的かつ選択的に呼び出す場合を説明する図である。
【図５】マルチタスク実行結果に対するモデル評価説明図である。
【図６】従来の、機能設計されたハードウエアとソフトウエアとからなるシステムモデルの評価説明図である。
【符号の説明】
１０ ソフトウエアモデル
１１ ハードウエアモデル
１２、１２Ａ シミュレータ
１３ システムモデル
２０ ワンチップマイクロコンピュータ
２１ ＭＰＵ
２２ メモリ
２３、２４ Ｉ／Ｏインタフェース
２５〜２９ ハードウエアブロック
３０、３０Ａ アーキテクチャ定義ファイル
３１、３１Ａ ソースコードファイル
３２ オブジェクト作成部
３３ データ処理部
３０１、３０１Ａ クラスＩｎｔ３２の定義部
３０２ クラスＩｎｔ６４の定義部
３０３ クラスＦｌｔ３２の定義部
３０４ クラスＦｌｔ６４の定義部
３２１ クラスＩｎｔ３２のオブジェクト作成部
３２１Ａ 派生クラス指定及びクラスＩｎｔ３２のオブジェクト作成部
３２２ クラスＦｌｔ３２のオブジェクト作成部
３３１、３３２ データ処理部
４１ 基本クラスＡｒｃの定義部
４２ 派生クラスＡｒｃ１の定義部
４３ 派生クラスＡｒｃ２の定義部[0001]
The present invention relates to a function simulation how the system consisting of hardware and software.
[0002]
[Prior art]
For example, when functionally designing and evaluating a system in which a peripheral semiconductor device is connected to a one-chip microcomputer, processing as shown in FIG. 6 has been conventionally performed. That is, the software model 10 of the one-chip microcomputer and the hardware model 11 of the peripheral semiconductor device are separately created by a program, and the software model 10 and the hardware model 11 are linked by the simulator 12 and based on the result. When the system was evaluated, if it was not reasonable, the software model 10 and the hardware model 11 were corrected and the simulation was repeated.
[0003]
[Problems to be solved by the invention]
However, since the software model 10 and the hardware model 11 are separate, if one of these is corrected, the other must be corrected accordingly, which is complicated. For example, when a part of hardware is replaced with software in order to reduce the product price, the hardware model 11 must be corrected, and the software model 10 must be corrected accordingly. The same applies to the case where the processing speed does not meet the specifications and a part of the software is replaced with hardware. Such corrections are frequently made to the model, which caused the system development period to increase.
[0004]
SUMMARY OF THE INVENTION In view of such problems, correction is easy to provide a functional simulation how the system composed of hardware and software.
[0005]
[Means for solving the problems and their effects]
In one aspect of the method of creating a system model composed of hardware and software, which is a function simulation target, according to the present invention, the computer program includes:
An architecture definition that declares an architecture class that includes an operator function that overloads an operator and a variable to be operated and includes a call to an operation cost function that spends a predetermined time on the function, and defines the operator function and the operation cost function And
A declaration part for creating an object of the class;
A processing unit that performs operations between objects to represent the operation of the system;
The predetermined time corresponds to an operation execution time of software or hardware, the predetermined time varies depending on the architecture of the system, and the contents of the processing unit are not changed in response to a change in the architecture of the system. The value of the predetermined time is changed.
[0006]
According to this configuration, an architecture that replaces part of the hardware and part of the software from one to the other based on the simulation result of the system model, or changes the processing speed of part or all of the hardware. In response to the change, the value of the predetermined time may be changed without changing the contents of the processing unit, so that the correction of the system model is easy.
[0007]
In another aspect of the function simulation target model creation method according to the present invention, a plurality of the classes having the predetermined times different from each other according to the architecture of the system are provided for the same operator.
The description of the declaration unit is changed without changing the contents of the processing unit in response to a change in the architecture of the system.
[0008]
According to this configuration, since the processing time in the processing unit can be changed by changing the description of the declaration unit, the system model can be easily corrected.
[0009]
In still another aspect of the method for creating a functional simulation target model according to the present invention, the architecture definition unit further includes a declaration of a basic class including the calculation cost function and the calculation cost for the basic class to determine the predetermined time. Including a declaration of a derived class for each value of the predetermined time, overwriting the function,
It further has a calling function specifying unit that specifies an object of a derived class so that an object that calls an operation cost function having a predetermined time according to the architecture is created in the declaration unit.
[0010]
According to this configuration, one class can correspond to a plurality of processing times, so that the configuration of the architecture definition unit is simplified.
[0011]
Other objects, configurations and effects of the present invention will become apparent from the following description.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0013]
FIG. 2 is a schematic block diagram illustrating a configuration example of a system including hardware and software, which is a function design target.
[0014]
This system is composed of a one-chip microcomputer 20 and its peripheral devices. In the one-chip microcomputer 20, a memory 22 and I / O interfaces 23 and 24 are connected to an MPU 21 by a bus. Hardware blocks 25 to 28 are connected to the I / O interface 23, and a hardware block 29 is connected to the I / O interface 24.
[0015]
Each hardware block is a functional block, and the difference between the processing by the hardware block and the processing by the software is only the processing time.
[0016]
In the development of this system, when a functional model is created and simulation is performed for the evaluation, the model of the one-chip microcomputer 20 is represented by a program stored in the memory 22 in consideration of processing time. Similarly, the hardware blocks 25 to 29 are represented by programs that perform the respective functions in consideration of the processing time.
[0017]
Therefore, a simulation can be performed by representing a model of the entire system as one program and operating the program. In this case, each processing unit in the program needs to consider the execution time due to the difference in the hardware configuration of the model component. When a part of the hardware is omitted based on the simulation result and the function is realized by software, or conversely, a part of the software is replaced by hardware or the processing speed of the hardware is changed In this case, the program execution time required for processing may be changed according to the processing speed of software or hardware. Parallel processing can be represented by multitask processing without distinguishing between processing by software and hardware. The multitask process is executed by, for example, a multithread method.
[0018]
However, since the processing by the one-chip microcomputer 20 and the processing by the hardware blocks 25 to 29 are mixed, the processing time must be taken into account in each part of the program, and the program is corrected for partial modification of the model. The processing time must be changed throughout. Therefore, it is necessary to devise a method for expressing the processing time to avoid complexity.
[0019]
FIG. 1 is a block diagram showing the principle configuration of the present invention.
[0020]
The above-described system model 13 created by the program is operated by the simulator 12A, and the system is evaluated based on the result. If it is not reasonable, the system model 13 is corrected and a simulation is repeated.
[0021]
The system model 13 includes an architecture definition file 30 that abstractly defines each element of the architecture, and a source code file 31 that embodies this and represents the operation of the model. In the following, a case where the program language is C ++ will be described.
[0022]
The architecture definition file 30 includes class declarations and class member function definitions. The source code file 31 includes an object creating unit 32 that creates an object of a class and a data processing unit 33 that performs processing on the created object.
[0023]
FIG. 3 shows a more specific configuration example of the architecture definition file 30 and the source code file 31.
[0024]
The architecture definition file 30 includes architecture definition units 301 to 304. The architecture definition unit 301 defines the addition of a 32-bit integer and the time required to execute it. The architecture definition unit 301 includes a declaration of a class Int32 and a definition of a '+' operator function that is a member function of this class. . In this function, another function send_time (10) is called.
[0025]
The send_time (10) is a function that spends a time of 10 length (time 10) for the simulator 12A, and this time is an addition execution time in the simulation. The calculation time of the addition itself is regarded as 0 by the simulator 12A. This also applies to other processes other than the function “spend_time”. The unit of time is a unit for the simulator 12A to operate the system model 13, and in the multitask by the multithread method, the process of incrementing the simulation time by 1 after each task is operated for a unit time is repeated.
[0026]
A specific example of the declaration of class Int32 is as follows.

The object creation unit 321 of class Int32 of the source code file 31 creates an object of class Int32. The object creation unit 321 of class Int32 is, for example,
Int32 d, e, f;
Is described. As a result, objects d, e, and f of class Int32 are created.
[0027]
The data processing unit 331 is a data process for the created object.
d = e + f;
Is described.
[0028]
When this addition is executed, normal addition is performed by the definition unit 301 of the class Int32, and the send_time (10) is read out. This can correspond to the addition time by the hardware block or software.
[0029]
After the object is created, the send_time (10) is executed no matter where the addition operation is performed on the object, and it is not necessary to directly describe the function send_time in the source code file 31. Also, when replacing part of the hardware and part of the software from one to the other, or changing the processing speed of part or all of the hardware based on the simulation results as described above It is only necessary to change the argument value x of the function send_time (x). Therefore, it becomes easy to create and modify the model.
[0030]
Similarly, the architecture definition unit 302 defines the addition of 64-bit integers and the time required to execute them. The declaration of the class Int64 and the definition of the “+” operator function that is a member function of this class It consists of. In this function, the function send_time (20) is called.
[0031]
Since this argument value is different from that of the architecture definition unit 301, the architecture definition unit 302 can correspond to processing of a hardware block different from that of the architecture definition unit 301. If the object creation unit 321 of class Int32 is changed to an object creation unit of class Int64, the processing time in the data processing unit 331 changes. Therefore, it is possible to easily modify the model simply by changing the object creation unit.
[0032]
Similarly to the above, the architecture definition unit 303 defines the multiplication of 32-bit floating point numbers and the time required for execution thereof, and the architecture definition unit 304 determines the time required for multiplication of 64-bit floating point numbers and the execution thereof. Is defined.
[0033]
In FIG. 3, the object creation unit 321 of the class Int32 and the object creation unit 322 of the class Flt32 are described separately, but it goes without saying that both object creation units may be described together in one place.
[0034]
In the example of FIG. 3, in order to associate a send_time (x) of different argument values x with the addition operation, the same class as the number of argument values x must be declared and its member function must be defined.
[0035]
Next, with reference to FIG. 4, a case will be described in which send_time (x) of a plurality of argument values x is indirectly and selectively called with a declaration of one class Int32.
[0036]
In this case, apart from the class Int32, a plurality of classes that call the send_time (x) having different argument values x are declared, and one of these classes is designated by a pointer, thereby defining one class Int32. Calls send_time (x) of multiple argument values x indirectly and selectively.
[0037]
In the architecture definition section 301A of the architecture definition file 30A, a class Int32 is declared, a '+' operator function is defined, and a member function f () of the base class Arc is called using a pointer in this function. “= 0” in f () = 0 indicates a virtual function. In this function, the function send_time (x) is not called, and the send_time (x) having different argument values x is called in each of the derived classes Arc1 and Arc2 with respect to the base class Arc.
[0038]
In the derived class designation / object creation unit 321A of the source code file 31A, the derived class Arc2 is designated by storing the address of the derived class Arc2 in the pointer that is a static member of the base class Arc, and an object of the class Int32 is created. . As a result, the send_time (40) is executed in the addition of the source code file 31A by the data processing unit 331.
[0039]
A specific example of the architecture definition unit 301A is as follows.

The function Int32_Add_Cost () corresponds to the function f () in FIG.
[0040]
A specific example of the declaration part 41 of the base class Arc is as follows.

In the above example, std :: map <Task *, Arch *> task_arch_map is a table that stores the association between the pointer to the Task class or its derived class object and the pointer to the Arch class or its derived class object. Record the architecture that each task uses at a certain point.
[0041]
task_arch_map (Task :: crnt_task ()) = arch means that the task executing this is obtained from the thread management function, and the relationship between the task and the architecture indicated by arch is stored in the table.
[0042]
Specific examples of the declaration part 42 of the derived class Arc1 and the declaration part 43 of the derived class Arc2 are as follows.

A specific example of the object creation unit 321 of the class Int32 is as follows.

A specific example of the data processing unit 331 is as follows.
[0043]
d = e + f;
Next, another specific example will be described.
[0044]
Extending the above example, simply writing an arithmetic expression in the data processing unit 33, processing for receiving and calculating data, or processing for calculating data and transferring the result, such as the hardware blocks 26 and 27 in FIG. , Between hardware blocks 25 and 28, or between hardware blocks 25 and 29, and a process of performing a calculation after that. In this case, in the operator function, send_time (x) corresponding to different data transmission / reception times is called depending on which hardware block is present. The argument value x is stored in a table to be obtained from the relationship between Arches set in advance. Specific examples are shown below.
[0045]
A specific example of the class declaration part of the architecture definition file 301A is as follows.

In the above specific example, the '=' operator function operator = means that the Arch having the left-side value is set to the latest Arch. This sets the object on the left side of = to the architecture that called it.
[0046]
std :: map <Arch *, int> transfer_cost_table is a table that stores the communication cost (communication time) with other architectures for each architecture (hardware block). Arch class or its derivatives The communication cost can be obtained by giving a pointer to the class object.
[0047]
transfer_cost_table [a] = c sets that the communication cost with the architecture a is c with respect to the communication cost (communication time) storage table with each other architecture for each architecture.
[0048]
crnt_arch () is a static member function of the Arch class, and the task that called it is obtained from the thread management function, and the called task is used at that point from task_arch_map, which is the static member of the Arch class. Used to obtain the architecture
[0049]
A specific example of the data processing unit 331 is as follows.

In the above specific example, B.Set_Trans_Cost (& A, 100) sets that the communication cost of the architecture B with the architecture A is 100 in the communication cost table.
[0050]
Next, a method for evaluating the system model 13 will be described.
[0051]
The system model 13 describes tasks to be processed in parallel with each other, and the simulator 12A performs a simulation for executing a multitask based on this. In the model source code file 31, the block names are stored in the memory at the start and end of the operation of each hardware block, and the parallel processing result as shown in FIG. .
[0052]
A to C in FIG. 5 are symbols described in the hardware block in FIG. 2. For example, a rectangle of the block A indicates an operation period of the block A. The maximum number of blocks A to C used at the same time is 2, 2 and 1, respectively. If the hardware prices of the blocks A to C are 100, 2000 and 10, for example, the estimated price of the peripheral device is 100 × 2 + 2000. × 2 + 10 × 1 = 4210. Whether the system configuration is reasonable can be evaluated from this price and the% of the required processing time 25.
[0053]
Further, assuming that the power consumption of the blocks A to C is 10 W, 200 W, and 1 W, respectively, the estimated maximum power consumption of the system is 400 W, and the system configuration is reasonable because of the percentage of the required value for the processing time 25. Can be evaluated. Average power may be used instead of maximum power consumption.
[0054]
As is clear from the above description, the present invention includes the following supplementary notes.
[0055]
(Supplementary note 1) A method of creating a system model composed of hardware and software, which is a target of functional simulation, using a computer program,
An architecture definition that declares an architecture class that includes an operator function that overloads an operator and a variable to be operated and includes a call to an operation cost function that spends a predetermined time on the function, and defines the operator function and the operation cost function And
A declaration part for creating an object of the class;
A processing unit that performs operations between objects to represent the operation of the system;
The predetermined time corresponds to an operation execution time of software or hardware, the predetermined time varies depending on the architecture of the system, and the contents of the processing unit are not changed in response to a change in the architecture of the system. A function simulation target model creation method, wherein the value of the predetermined time is changed. (1)
(Supplementary note 2) A plurality of the classes having the predetermined times different from each other according to the architecture of the system for the same operator,
The function simulation target model creation method according to appendix 1, wherein the description of the declaration unit is changed without changing the contents of the processing unit in response to the architecture change of the system. (2)
(Supplementary Note 3) The architecture definition unit further declares a basic class including the calculation cost function, and overwrites the calculation cost function with respect to the basic class to determine the predetermined time. Including declarations of derived classes,
The function according to supplementary note 1, further comprising a call function specifying unit that specifies an object of a derived class so that an object that calls an operation cost function having a predetermined time according to the architecture is created in the declaration unit Simulation target model creation method. (3)
(Supplementary note 4) The architecture class further includes a call to a transfer cost function that spends a predetermined time corresponding to the data transfer time,
The function simulation target model creation method according to any one of appendices 1 to 3, wherein the computation between the objects corresponds to an operation of receiving and calculating data or calculating and transmitting data . (4)
(Supplementary note 5) The function simulation target model creation method according to any one of supplementary notes 1 to 4, wherein the language of the program is C ++.
[0056]
(Supplementary note 6) The function simulation target model creation method according to any one of supplementary notes 1 to 5, wherein the computer program has a plurality of tasks to be processed in parallel.
[0057]
(Additional remark 7) Each task contains the code | cord | chord which outputs the data which show the classification of the hardware structural block in use, The function simulation object model preparation method of Additional remark 6 characterized by the above-mentioned.
[0058]
(Supplementary Note 8) (a) The system model created by the method described in Supplementary Note 7 is operated for a predetermined period by a simulator, and data indicating the type of hardware configuration block in use, which is output during the operation, is stored. Stored in the
(B) After the predetermined period has elapsed, the data is read from the storage device, and the type and number of hardware constituent blocks in use at each time are obtained.
(C) A function simulation target model evaluation method characterized by evaluating the architecture based on the type and number. (5)
(Supplementary Note 9) In the step (c), the maximum number of the same type of hardware configuration blocks used at the same time is obtained, and the price for each type of hardware configuration block and the maximum number of simultaneous use of the hardware configuration block of the type are calculated. 9. The function simulation target model evaluation method according to appendix 8, wherein a sum of products is estimated as a hardware price of the system.
[0059]
(Supplementary Note 10) The storage device stores a power consumption value for each type of hardware configuration block.
9. In the step (c), the power consumption of the hardware is estimated as an evaluation value based on the type and number of hardware configuration blocks used at each time and the power consumption value. Function simulation target model evaluation method.
[Brief description of the drawings]
FIG. 1 is an evaluation explanatory view of a system model composed of hardware and software whose functions are designed according to the present invention.
FIG. 2 is a schematic block diagram illustrating a configuration example of a system including the hardware and software.
FIG. 3 is a diagram illustrating a more specific configuration example of an architecture definition file and a source code file.
FIG. 4 is a diagram for explaining a case where a function send_time (x) of a plurality of argument values x is indirectly and selectively called in one class including an operator function.
FIG. 5 is an explanatory diagram of model evaluation for a multitask execution result.
FIG. 6 is an evaluation explanatory diagram of a conventional system model composed of hardware and software whose functions are designed.
[Explanation of symbols]
10 Software Model 11 Hardware Model 12, 12A Simulator 13 System Model 20 One-Chip Microcomputer 21 MPU
22 Memory 23, 24 I / O interface 25-29 Hardware block 30, 30A Architecture definition file 31, 31A Source code file 32 Object creation unit 33 Data processing unit 301, 301A Definition unit 302 of class Int32 Definition unit 303 of class Int64 Class Flt32 definition unit 304 Class Flt64 definition unit 321 Class Int32 object creation unit 321A Derived class designation and class Int32 object creation unit 322 Class Flt32 object creation unit 331, 332 Data processing unit 41 Base class Arc definition unit 42 Definition part 43 of derived class Arc1 Definition part of derived class Arc2

Claims (6)

A function simulation method for causing a computer to operate a system model composed of hardware and software described in a computer program, the computer program comprising an operator function overloading an operator and a variable to be operated on And a plurality of architecture classes including a call to an operation cost function that consumes a predetermined time in the operator function, and the predetermined time corresponds to an operation execution time of a block or software constituting the hardware,
The computer
(A) Create an object of the class, by performing calculation between objects, to operate the system model, in the operation start and end of each block, indicating the type and age of the blocks constituting the hardware Store the data in a storage device,
(B) Read the data from the storage device after the simulation is executed,
(C) evaluating the architecture based on the read data and outputting the result;
In the step (a), by operating the system model in multithread, a plurality of blocks constituting the hardware are operated in parallel, or the blocks constituting the hardware and the software are operated in parallel. Function simulation method.   In the step (c), the maximum number of hardware configuration blocks of the same type that are used at the same time is obtained, and the sum of the product of the price for each type of hardware configuration block and the maximum number of simultaneous use of hardware configuration blocks of the type is calculated. The function simulation method according to claim 1, wherein the hardware simulation price of the system is estimated. The storage device stores a power consumption value for each type of hardware configuration block,
In the step (c), according to claim 1, wherein the power estimation of the hardware as an evaluation value based on the power consumption value and type and number of the hardware building blocks used at each time Function simulation method. According to the architecture of the hardware building block of the system model, the predetermined time has a plurality of classes different for the same operator,
4. The function simulation method according to claim 1, wherein the predetermined time is changed in response to an architecture change . The plurality of architecture classes include a base class including the operation cost function and a plurality of derived classes having different predetermined times from each other, overwriting the operation cost function with respect to the base class to determine the predetermined time. ,
The operation cost function having a predetermined time corresponding to the architecture is called by designating one of the plurality of derived classes and creating the object in the step (a). The function simulation method according to 1. The architecture class further includes a call to a transfer cost function that spends a predetermined time corresponding to the data transfer time;
6. The function simulation method according to claim 1, wherein the calculation between the objects corresponds to an operation of receiving and calculating data or calculating and transmitting data.

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