JP4297287B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device in which element regions are separated by a groove provided in a semiconductor substrate, and in particular, a nonvolatile memory cell that operates at a high voltage and a transistor that operates at a low voltage are formed on the same semiconductor substrate. The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, batch erasable flash memories such as EEPROM (Electrically Erasable Programmable Read Only Memory) have come to be used for IC cards and the like. An EEPROM memory cell has two gate electrodes, a floating gate and a control gate, and data is written / erased by controlling the input / output of charges to / from the floating gate.

  The flash memory is provided with a drive circuit for driving the memory cell. In recent years, a system LSI in which a memory cell and a CPU or other logic circuit are formed on the same semiconductor substrate has been developed. Hereinafter, the drive circuit or the logic circuit formed on the same semiconductor substrate as the memory cell is referred to as a peripheral circuit.

  1 to 4 are sectional views showing a conventional method of manufacturing a semiconductor device (flash memory) in the order of steps. 1 to 4, the cross section of the memory cell formation portion is shown on the left side of the drawing, and the cross section of the peripheral circuit formation portion is shown on the right side of the drawing.

  First, as shown in FIG. 1A, a pad oxide film 101 is formed on a semiconductor substrate 100, and a silicon nitride film 102 is formed thereon by a CVD (Chemical Vapor Deposition) method. Note that a film having a stacked structure of a silicon oxide layer and a silicon nitride layer may be formed instead of the silicon nitride film 102.

  Next, as shown in FIG. 1B, the silicon nitride film 102 is patterned into a predetermined shape by photolithography. Then, using this silicon nitride film 102 as a mask, the pad oxide film 101 and the semiconductor substrate 100 are etched to form shallow grooves (trench) 103a and 103b in the memory cell formation portion and the peripheral circuit formation portion, respectively.

  Next, as shown in FIG. 2A, silicon oxide is deposited on the entire upper surface of the semiconductor substrate 100 to form a silicon oxide film 105, and the grooves 103a and 103b are filled with silicon oxide. Thereafter, the silicon oxide film 105 and the silicon nitride film 102 are polished by, for example, CMP (Chemical Mechanical Polishing) to flatten the surface. However, in this step, the silicon oxide in the grooves 103a and 103b may be separated from each other, and the polishing is finished before the silicon nitride film 102 is completely removed.

  Thereafter, as shown in FIG. 2B, the silicon nitride film 102 is removed by etching. Hereinafter, a film made of silicon oxide in the groove 103a in the memory cell formation portion is called an element isolation film 106a, and a film made of silicon oxide in the groove 103b in the peripheral circuit formation portion is called an element isolation film 106b.

  Next, as shown in FIG. 3A, after the silicon oxide film 101 is removed by etching, the exposed substrate surface is oxidized, and tunnels having a predetermined thickness are respectively formed in the memory cell formation portion and the peripheral circuit formation portion. An oxide film 107a and a gate oxide film 107b are formed.

  Next, as shown in FIG. 3B, the floating gate 108a, the intermediate insulating film 109, and the control gate 110a are formed in the memory cell formation portion, and the gate electrode 110b is formed on the gate oxide film 107b in the peripheral circuit formation portion. Form. The floating gates 108a are formed one by one on the tunnel oxide film 107a in each memory cell region, and the control gate 110a is formed so as to pass over the plurality of floating gates 107a arranged in a straight line.

  Thereafter, impurities are implanted into the surface of the semiconductor substrate 100 using the control gate 110a and the gate electrode 110b as masks to form source / drain layers (not shown). Further, an interlayer insulating film 111 is formed on the entire upper surface of the semiconductor substrate 100, and the control gate 110a and the gate electrode 110b are covered with the interlayer insulating film 111.

Next, a contact hole (not shown) is formed at a predetermined position of the interlayer insulating film 111 by photolithography. Then, a metal film is formed on the entire upper surface of the semiconductor substrate 100, and this metal film is patterned to form a bit line 112a in the memory cell formation portion and a wiring 112b in the peripheral circuit formation portion as shown in FIG. Form. In this way, the flash memory is completed.
JP 2000-269450 A JP 2001-68652 A JP-A-2-260660

  However, the inventors of the present application consider that the above-described conventional method for manufacturing a semiconductor device has the following problems.

  FIG. 5 is an enlarged view showing the shape of the upper edge portion of the element isolation film. As shown in FIG. 5, in the conventional method, since the curvature of the interface between the upper edge of the element isolation film 106 and the semiconductor substrate 100 is small, thinning (a phenomenon in which the insulating film becomes thin near the corner) occurs. . As a result, a parasitic transistor is generated in parallel with the memory cell, and as a result, a hump occurs in the current-voltage characteristic of the memory cell, causing an increase in leakage current.

  Further, while the peripheral circuit transistor operates at a low voltage of 3.3 V or lower, a high voltage of about 20 V is applied to the memory cell, so that the upper edge of the element isolation film 106 and the semiconductor substrate 100 If the curvature at the interface is small, a strong electric field is concentrated on that portion, and the controllability of charge in and out of the floating gate 108a is deteriorated, and the tunnel oxide film 107a is damaged.

  On the other hand, it is conceivable to increase the curvature of the interface between the upper edge of the element isolation film 106 and the semiconductor substrate 100. However, since the area of the element region is inevitably reduced, current driving of the transistors constituting the peripheral circuit is performed. The capability is reduced, and the operation speed is reduced. When the curvature of the interface between the element isolation film 106 and the semiconductor substrate 100 is increased and the area of the element region of the peripheral circuit forming portion is also increased, there arises a problem that the high integration of the semiconductor device is hindered.

  Patent Document 1 proposes that the curvature of the end portion of the element region of the peripheral circuit formation portion is larger than the curvature of the end portion of the element region of the memory cell formation portion. However, in this case, it is not possible to prevent the controllability of charge in and out of the floating gate of the memory cell and damage to the tunnel oxide film, and to prevent the peripheral circuit drive capability and integration density from decreasing. I can't.

  In view of the above, an object of the present invention is to avoid a decrease in the current driving capability of a transistor driven at a low voltage while ensuring the reliability of the gate insulating film of a nonvolatile memory cell to which a high voltage is applied, and to further improve the semiconductor device. It is an object to provide a method of manufacturing a semiconductor device that can achieve high integration.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a plurality of first grooves in a first region of a semiconductor substrate; and forming a plurality of second grooves in a second region; A step of increasing the curvature of the upper edge portion of the substrate, a step of filling the first and second grooves with an insulating material, an element that is driven at a low voltage in the first region, and forming in the second region Forming a nonvolatile memory cell driven at a high voltage.

  For example, a first insulating film made of silicon oxide is formed in first and second regions on the semiconductor substrate, and a second insulating film made of silicon nitride is formed on the first insulating film. Then, after patterning the second insulating film, the first insulating film and the semiconductor substrate are etched using the second insulating film as a mask to form a first groove in the first region, and the second region A second groove is formed.

  Thereafter, the first insulating film in the second region is side-etched. Thereby, a gap is formed between the semiconductor substrate around the second groove and the second insulating film. When the inner surface of the groove is oxidized, the gap promotes the oxidation of the surface of the semiconductor substrate around the second groove. Therefore, the curvature of the edge of the semiconductor substrate at the upper edge of the second groove is larger than the curvature of the edge of the semiconductor substrate at the upper edge of the first groove. Thereafter, an isolation material is formed by filling an insulating material in the first and second trenches, a MOS transistor or the like that operates at a low voltage is formed in the first region, and a high voltage is applied in the second region. A non-volatile memory cell to be supplied is formed.

  Thus, in the present invention, since the curvature of the interface between the upper edge of the groove in the first region and the semiconductor substrate is reduced, elements such as MOS transistors can be integrated at high density. In addition, since the curvature of the interface between the upper edge of the groove in the second region and the semiconductor substrate is increased, it is possible to prevent the electric field from being concentrated on a part, and to prevent damage to the tunnel oxide film and the change in characteristics. The

  A method for reducing the curvature of the upper edge of the groove in the first region and increasing the curvature of the upper edge of the groove in the second region is described in the second region, as will be described later in the embodiment. For example, there is a method in which a silicon oxide film is formed thick on the semiconductor substrate and a silicon oxide film is formed thin on the semiconductor substrate in the first region. In this case, since a relatively large amount of oxygen is supplied to the substrate surface around the trench through the thick silicon oxide film, oxidation of the substrate surface around the trench in the second region is promoted. Thereby, in the 2nd field, the curvature of the edge of the semiconductor substrate of the upper edge part of a slot becomes large compared with the 1st field.

  As another method for increasing the curvature of the edge of the semiconductor substrate at the upper edge of the groove, a gap between the semiconductor substrate and the insulating film is formed around the groove by performing a heat treatment in a hydrogen atmosphere after the groove is formed. The method of oxidizing the substrate surface after forming the substrate, the method of oxidizing the substrate surface after exposing the semiconductor substrate surface around the groove by appropriately controlling the etching conditions in the etching process using the resist film as a mask, etc. There is.

  According to the present invention, the curvature of the boundary between the upper edge of the element molecular film and the semiconductor substrate in a region where an element to which a high voltage is supplied, such as a memory cell of a nonvolatile semiconductor device, is formed as in a MOS transistor. Since the curvature of the interface between the upper edge of the element isolation film and the semiconductor substrate in the region where the element operating at a low voltage is formed is larger, the characteristics and reliability of the memory cell and the like are improved, and the semiconductor There is an effect that high integration of the device is achieved.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
6 to 10 are sectional views showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. Note that this embodiment mode shows an example in which the present invention is applied to manufacture of a flash memory (EEPROM) having a memory cell and a peripheral circuit for driving the memory cell. In FIGS. In either case, the left side of the figure shows a cross section of the memory cell forming portion, and the right side shows a cross section of the peripheral circuit forming portion.

  First, as shown in FIG. 6A, a pad oxide film 11 is formed on a semiconductor substrate 10 by, eg, thermal oxidation, and a silicon nitride film 12 is formed thereon by CVD. Note that a film having a stacked structure of a silicon oxide layer and a silicon nitride layer may be formed instead of the silicon nitride film 12.

  Next, as shown in FIG. 6B, the silicon nitride film 12 is etched by a photolithography method to remove the silicon nitride film 12 in the element isolation region of the memory cell formation portion and the peripheral circuit formation portion. Only the silicon nitride film 12 is left. Then, using the remaining silicon nitride film 12 as a mask, the pad oxide film 11 and the semiconductor substrate 10 are etched to form shallow grooves (trench) 13a and 13b in the memory cell formation portion and the peripheral circuit formation portion, respectively.

  Next, a resist film (not shown) that covers the peripheral circuit formation portion is formed. Then, the edge portion of the pad oxide film 11 is etched (side-etched) under the condition of isotropic etching with respect to the silicon oxide film. As a result, a gap is formed between the silicon nitride film 12 around the groove 13a and the semiconductor substrate 10, as shown in FIG. Thereafter, the resist film is removed.

  Next, for example, heat treatment is performed in an atmosphere having a temperature of 850 to 1100 ° C. and an oxygen concentration of 10%, and as shown in FIG. 7B, an oxidation having a thickness of 5 nm or more is formed on the inner surfaces of the grooves 13a and 13b. A silicon film 14 is formed.

  At this time, in this embodiment, since a gap between the semiconductor substrate 10 and the silicon nitride film 12 is formed in advance on the upper edge of the groove 13a, an oxidizing agent (oxygen) to the upper edge of the groove 13a. Supply is promoted. As a result, a thick oxide film (bird's beak) is formed in this portion as shown in FIG. 7B, and the edge of the semiconductor substrate 10 around the groove 13a is rounded.

  Next, as shown in FIG. 8A, silicon oxide is deposited on the entire upper surface of the semiconductor substrate 10 by high density plasma CVD to form a silicon oxide film 15, and the grooves 13a and 13b are oxidized. Fill with silicon. Thereafter, the silicon oxide film 15 and the silicon nitride film 12 are polished by, for example, a CMP method to flatten the surface. However, in this step, the silicon oxide in the grooves 13a and 13b may be separated from each other, and the polishing is finished before the silicon nitride film 12 is completely removed. Instead of polishing the silicon oxide film 15 by CMP, the silicon oxide film 15 may be etched back until the side surface of the silicon nitride film 12 is exposed to some extent.

  Next, as shown in FIG. 8B, the silicon nitride film 12 is removed by wet etching using, for example, hot phosphoric acid. Hereinafter, the film made of silicon oxide in the groove 13a in the memory cell formation portion is called an element isolation film 16a, and the film made of silicon oxide in the groove 13b in the peripheral circuit formation portion is called an element isolation film 16b.

  Next, the pad oxide film 11 is removed by etching to expose the surface of the semiconductor substrate 10. At this time, the element isolation films 16a and 16b are also etched to reduce the film thickness. Thereafter, the surface of the semiconductor substrate 10 exposed by removing the pad oxide film 11 is thermally oxidized to form a tunnel oxide film 17a in the memory cell formation portion as shown in FIG. 9A, and in the peripheral circuit formation portion. A gate oxide film 17b is formed. The thicknesses of the tunnel oxide film 17a and the gate oxide film 17b are set according to the required specifications.

  Next, as shown in FIG. 9B, the floating gate 18a, the intermediate insulating film 19 and the control gate 20a are formed in the memory cell formation portion, and the gate electrode 20b is formed on the gate oxide film 17b in the peripheral circuit formation portion. Form. One floating gate 18a is formed on each tunnel oxide film 17a in each memory cell region. The control gate 20a is formed so as to pass above the plurality of floating gates 18a arranged in a straight line.

  Next, impurities are introduced into the surface of the semiconductor substrate 10 using the control gate 20a and the gate electrode 20b as a mask to form source / drain layers (not shown). Further, an interlayer insulating film 21 made of, for example, silicon oxide is formed on the entire upper surface of the semiconductor substrate 10, and the control gate 20 a and the gate electrode 20 b are covered with the interlayer insulating film 21.

  Next, a contact hole (not shown) is formed at a predetermined position of the interlayer insulating film 21 by photolithography. Then, a metal film is formed on the entire upper surface of the semiconductor substrate 10, and this metal film is patterned to form a bit line 22a in the memory cell formation portion as shown in FIG. A wiring 22b is formed. In this way, the flash memory is completed.

  In the present embodiment, as shown in FIG. 7A, the pad oxide film 11 is side-etched so that the semiconductor substrate 10 and the silicon nitride film 12 at the upper edge of the groove 13a of the memory cell formation portion are formed. A gap is formed between them. Thus, when the inner surface of the groove 13a is oxidized, the oxidation of the upper edge of the groove 13a is promoted, and the curvature of the edge of the semiconductor substrate 10 is increased as shown in FIG. On the other hand, since the pad oxide film 11 is not side-etched in the peripheral circuit forming portion, the oxidation of the edge of the groove 13b is suppressed, and the curvature of the edge of the semiconductor substrate 10 is reduced as shown in FIG.

  As a result, changes in characteristics due to thinning and electric field concentration are avoided in the memory cell formation portion, and a decrease in current drive capability is avoided in the peripheral circuit formation portion. Further, in this embodiment mode, a predetermined current driving capability can be obtained without enlarging the element region of the peripheral circuit formation portion, so that the semiconductor device can be highly integrated.

  Furthermore, in the present embodiment, the interface between the semiconductor substrate 10 and the upper edge of the element isolation film 16a has a curved surface with a large curvature, and the tunnel oxide film can be formed with a uniform thickness. High reliability.

(Second Embodiment)
12 to 16 are sectional views showing a method of manufacturing a semiconductor device (flash memory) according to the second embodiment of the present invention in the order of steps. 12 to 16, in each case, a cross section of the memory cell formation portion is shown on the left side and a cross section of the peripheral circuit formation portion is shown on the right side.

  First, as shown in FIG. 12A, a pad oxide film 21 is formed on the semiconductor substrate 10 by, eg, thermal oxidation. Then, the memory cell formation portion is covered with a resist film (not shown), and the pad oxide film 21 in the peripheral circuit formation portion is removed as shown in FIG.

  Next, as shown in FIG. 13A, the surface of the semiconductor substrate 10 is thermally oxidized again to form a pad oxide film 22a in the memory cell formation portion and a pad oxide film 22b in the peripheral circuit formation portion. .

  Next, as shown in FIG. 13B, a silicon nitride film 23 is formed on the pad oxide films 22a and 22b by the CVD method. Instead of the silicon nitride film 23, a film in which a silicon oxide layer and a silicon nitride layer are stacked may be formed.

  Next, as shown in FIG. 14A, the silicon nitride film 23 is etched by photolithography to remove the silicon nitride film 23 in the element isolation region, leaving the silicon nitride film 23 only in the element region. Then, using the remaining silicon nitride film 23 as a mask, the pad oxide films 22a and 22b and the semiconductor substrate 10 are etched to form shallow grooves (trench) 24a and 24b in the memory cell formation portion and the peripheral circuit formation portion, respectively.

  Next, for example, heat treatment is performed in an atmosphere having a temperature of 850 to 1100 ° C. and an oxygen concentration of 10%, and as shown in FIG. 14B, oxidation is performed on the inner surfaces of the grooves 24a and 24b with a thickness of 5 nm or more. A silicon film 25 is formed.

  At this time, since the pad oxide film 22a is formed thickly around the groove 24a of the memory cell formation portion, a relatively large amount of oxidant (oxygen) is applied to the substrate surface around the groove 24a via the pad oxide film 22a. Supplied. As a result, as shown in FIG. 14B, the edge of the semiconductor substrate 10 around the groove 24a has a rounded shape.

  Next, as shown in FIG. 15A, silicon oxide is deposited on the entire upper surface of the semiconductor substrate 10 by high-density plasma CVD to form a silicon oxide film 26, and the grooves 24a and 24b are filled with silicon oxide. Thereafter, the silicon oxide film 26 and the silicon nitride film 23 are polished by, for example, a CMP method to planarize the surface. In this step, the silicon oxide in the grooves 24a and 24b may be separated from each other, and the polishing is finished before the silicon nitride film 23 is completely removed. Instead of polishing the silicon oxide film 26 by CMP, the silicon oxide film 26 may be etched until the side surfaces of the silicon nitride film 23 are exposed to some extent.

  Next, as shown in FIG. 15B, the silicon nitride film 23 is removed by, for example, hot phosphoric acid. Hereinafter, a film made of silicon oxide in the groove 24a of the memory cell formation portion is called an element isolation film 27a, and a film made of silicon oxide in the groove 24b of the peripheral circuit formation portion is called an element isolation film 27b.

  Next, as shown in FIG. 16, the pad oxide films 22a and 22b are etched to expose the surface of the substrate 10. At this time, the element isolation films 27a and 27b are also etched to reduce the film thickness. Thereafter, the surface of the semiconductor substrate 10 exposed by the etching of the pad oxide films 22a and 22b is thermally oxidized to form a tunnel oxide film 28a in the memory cell formation portion and a gate oxide film 28b in the peripheral circuit formation portion. The thicknesses of the tunnel oxide film 28a and the gate oxide film 28b are set according to the required specifications.

  Next, as in the first embodiment, a floating gate, an intermediate insulating film, and a control gate are formed in the memory cell forming portion, a gate electrode is formed in the peripheral circuit forming portion, and an interlayer insulating film, a bit line, and Other wiring is formed (see FIG. 10). In this way, the flash memory is completed.

  In the present embodiment, as shown in FIG. 13A, a thick pad oxide film 22a is formed in the memory cell formation portion. Thereby, when oxidizing the inner surface of the groove 24a, a relatively large amount of oxidizing agent (oxygen) is supplied to the upper edge of the groove 24a via the pad oxide film 22a, and the oxidation of the upper edge of the groove 24a is promoted. As a result, as shown in FIG. 14B, the curvature of the edge of the semiconductor substrate 10 around the groove 24a increases. On the other hand, since the pad oxide film 22b is thin in the peripheral circuit formation portion, the amount of oxidation at the edge of the groove 24b is small, and the curvature of the edge of the semiconductor substrate 10 around the groove 24b is small as shown in FIG. Become. Thereby, also in this Embodiment, the effect similar to 1st Embodiment can be acquired.

  In this embodiment, the curvature of the edge of the semiconductor substrate 10 around the groove 24a is determined by the thickness of the pad oxide film 22a, so that the curvature can be easily controlled as compared with the first embodiment. Garage.

(Third embodiment)
17 to 20 are cross-sectional views showing a method of manufacturing a semiconductor device (flash memory) according to the third embodiment of the present invention in the order of steps. 17 to 20, the cross section of the memory cell formation portion is shown on the left side of the drawing, and the cross section of the peripheral circuit formation portion is shown on the right side.

  First, as shown in FIG. 17A, a pad oxide film 31 is formed on the semiconductor substrate 10 by, eg, thermal oxidation, and a silicon nitride film 32 is formed thereon by CVD. Instead of the silicon nitride film 32, a film having a stacked structure of a silicon oxide layer and a silicon nitride layer may be formed.

  Next, as shown in FIG. 17B, a resist film 33 having an opening at a portion corresponding to the element isolation region of the memory cell formation portion is formed on the silicon nitride film 32. Then, the silicon nitride film 32 and the pad oxide film 31 are sequentially etched using the resist film 33 as a mask, and the semiconductor substrate 10 is further etched to form a shallow groove (trench) 34.

  At this time, if the etching conditions are appropriately controlled, organic substances (organic substances released from the resist film 33) cover the substrate surface in the vicinity of the resist film 33 along with the etching, and the opening of the resist film 33 is formed as shown in FIG. The width of the groove 34 can be made narrower than the width of the portion. After forming the groove 34, the resist film 33 is removed.

  Next, a resist film (not shown) having an opening at a portion corresponding to the element isolation region of the peripheral circuit formation portion is formed. Then, after etching the silicon nitride film 32 using this resist film as a mask, the resist film is removed. Thereafter, using the silicon nitride film 32 as a mask, the pad oxide film 31 and the semiconductor substrate 10 in the peripheral circuit forming portion are etched to form a shallow groove 35 as shown in FIG.

  Next, for example, heat treatment is performed in an atmosphere having a temperature of 850 to 1100 ° C. and an oxygen concentration of 10%. As shown in FIG. 18B, the inner surfaces of the grooves 34 and 35 are oxidized with a thickness of 5 nm or more. A silicon film 36 is formed.

  At this time, in the present embodiment, since the upper surface of the semiconductor substrate 10 is exposed at the upper edge of the groove 34, an oxidant (oxygen) is supplied to the edge of the groove 34. As a result, FIG. ), A thick oxide film (bird's beak) is formed, and the edge of the semiconductor substrate 10 around the groove 34 is rounded.

  Next, as shown in FIG. 19A, silicon oxide is deposited on the entire upper surface of the semiconductor substrate 10 by high-density plasma CVD to form a silicon oxide film 37, and the grooves 34 and 35 are filled with silicon oxide. Thereafter, the silicon oxide film 37 and the silicon nitride film 32 are polished by, eg, CMP to planarize the surface. However, in this step, the silicon oxide in the grooves 34 and 35 may be separated from each other, and the polishing is finished before the silicon nitride film 32 is completely removed. Further, instead of polishing the silicon oxide film 37 by the CMP method, the silicon oxide film 37 may be etched back until the side surface of the silicon nitride film 32 is exposed to some extent.

  Next, as shown in FIG. 19B, the silicon nitride film 32 is removed by wet etching using, for example, hot phosphoric acid. Hereinafter, the film made of silicon oxide in the groove 34 of the memory cell forming portion is called an element isolation film 38a, and the film made of silicon oxide in the groove 35 of the peripheral circuit forming portion is called an element isolation film 38b.

  Next, the pad oxide film 32 is etched to expose the surface of the substrate 10. At this time, the element isolation films 38a and 38b are also etched to reduce the film thickness. Thereafter, the surface of the semiconductor substrate 10 exposed by etching the pad oxide film 32 is thermally oxidized to form a tunnel oxide film 39a in the memory cell formation portion and a gate oxide film in the peripheral circuit formation portion as shown in FIG. 39b is formed. The thicknesses of the tunnel oxide film 39a and the gate oxide film 39b are set according to the required specifications.

  Next, as in the first embodiment, a floating gate, an intermediate insulating film, and a control gate are formed in the memory cell forming portion, a gate electrode is formed in the peripheral circuit forming portion, and an interlayer insulating film, a bit line, and Other wiring is formed (see FIG. 10). In this way, the flash memory is completed.

  In the present embodiment, as shown in FIG. 17B, the etching conditions for forming the groove 34 are controlled to make the width of the groove 34 smaller than the width of the opening of the resist film 33. As a result, when the inner surface of the groove 34 is oxidized, oxidation of the upper edge portion of the groove 34 is promoted, and the curvature of the edge of the semiconductor substrate 19 around the groove 34 is increased as shown in FIG. Become. On the other hand, in the peripheral circuit forming portion, the groove 35 is formed with the width of the opening of the resist film, so that the amount of oxidant (oxygen) supplied to the upper edge of the groove 35 is small, as shown in FIG. Further, the curvature of the edge of the semiconductor substrate 10 on the groove 35 side becomes small. Thereby, also in this Embodiment, the effect similar to 1st Embodiment can be acquired.

  In the present embodiment, the thickness of the element isolation film 38a in the memory cell formation portion and the thickness of the element isolation film 38b in the peripheral circuit formation portion can be individually set as necessary.

(Fourth embodiment)
21 to 25 are cross-sectional views showing a method of manufacturing a semiconductor device (flash memory) according to the fourth embodiment of the present invention in the order of steps. In these FIGS. 21 to 25, the cross section of the memory cell forming portion is shown on the left side of the figure, and the cross section of the peripheral circuit forming portion is shown on the right side.

  First, as shown in FIG. 21A, a pad oxide film 41 is formed on the semiconductor substrate 10 by, eg, thermal oxidation. Then, the memory cell formation portion is covered with a resist film (not shown), and the pad oxide film 41 in the peripheral circuit formation portion is removed as shown in FIG.

  Next, as shown in FIG. 22A, the surface of the semiconductor substrate 10 is thermally oxidized again to form a pad oxide film 42a in the memory cell formation portion and a pad oxide film 42b in the peripheral circuit formation portion. . An oxynitride film (SiON) may be formed instead of the pad oxide films 42a and 42b.

  Next, as shown in FIG. 22B, a polysilicon film (or amorphous silicon film) 43 doped with phosphorus (P) is formed on the pad oxide films 42a and 42b by the CVD method.

  Next, as shown in FIG. 23A, a silicon nitride film 44 is formed on the polysilicon film 43 by the CVD method. Instead of the silicon nitride film 44, a film having a stacked structure of a silicon nitride layer and a silicon oxide layer may be formed.

  Thereafter, the silicon nitride film 44 is etched by photolithography to remove the silicon nitride film 44 in the element isolation region, leaving the silicon nitride film 44 only in the element region. Then, using the remaining silicon nitride film 44 as a mask, the polysilicon film 43 and the pad oxide films 42a and 42b are etched, and the semiconductor substrate 10 is further etched. As shown in FIG. Shallow grooves (trench) 45a and 45b are formed in the peripheral circuit forming portion, respectively.

  Next, for example, heat treatment is performed in an atmosphere having a temperature of 850 to 1100 ° C. and an oxygen concentration of 10%, and as shown in FIG. 24 (a), the inner surface of the grooves 45a and 45b is oxidized with a thickness of 5 nm or more. A silicon film 46 is formed.

  At this time, since the pad oxide film 42a is thickly formed on the upper edge of the groove 45a of the memory cell formation portion, a relatively large amount of oxidant (oxygen (oxygen) is applied to the substrate surface around the groove 45a via the pad oxide film 42a. ) Is supplied. As a result, as shown in FIG. 24A, the edge of the semiconductor substrate 10 around the groove 45a has a rounded shape.

  Next, as shown in FIG. 24B, silicon oxide is deposited on the entire upper surface of the semiconductor substrate 10 by high-density plasma CVD to form a silicon oxide film 47, and the grooves 45a and 45b are filled with silicon oxide. Thereafter, the silicon oxide film 47 and the silicon nitride film 44 are polished by, eg, CMP to planarize the surface. However, in this step, the silicon oxide in the grooves 45a and 45b may be separated from each other, and the polishing is finished before the silicon nitride film 44 is completely removed.

  Next, as shown in FIG. 25, the silicon nitride film 44 is removed by, for example, hot phosphoric acid. Hereinafter, the film made of silicon oxide in the groove 45a of the memory cell formation portion is called an element isolation film 48a, and the film made of silicon oxide in the groove 45b of the peripheral circuit formation portion is called an element isolation film 48b. FIG. 26A shows an enlarged shape of the upper edge portion of the element isolation film 48a, and FIG. 26B shows an enlarged shape of the upper edge portion of the element isolation film 48b.

  Next, the polysilicon film 43 is patterned into a predetermined shape, a floating gate is formed in the memory cell formation portion, and a gate electrode is formed in the peripheral circuit portion. If necessary, patterning may be performed after further depositing polysilicon on the polysilicon film 43 to increase the film thickness.

  Thereafter, as in the first embodiment, after forming an intermediate insulating film and a control gate in the memory cell formation portion, an interlayer insulating film is formed, and bit lines and other wirings are formed (see FIG. 10). In this way, the flash memory is completed.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained. In the present embodiment, since the silicon nitride film 44 is formed after the polysilicon film 43 is formed on the pad oxide films 42a and 42b, the pad oxide films 42a and 42b are formed when the silicon nitride film 44 is etched. Avoiding damage. Thus, the pad oxide films 42a and 42b can be used as a tunnel oxide film or a gate oxide film, and the manufacturing process is simplified. Further, in the present embodiment, since the polysilicon film 43 is used as a floating gate or a gate electrode of a peripheral circuit, the manufacturing process can be further simplified.

  Furthermore, in the present embodiment, unlike the first to third embodiments, there is no step of etching the element isolation films 48a and 48b (pad oxide film removal process), so that the element isolation films 48a and 48b are recessed. Will not occur. As a result, there is an advantage that good transistor characteristics can be obtained without causing humps in the transistor characteristics.

(Fifth embodiment)
27 to 30 are cross-sectional views showing a method of manufacturing a semiconductor device (flash memory) according to the fifth embodiment of the present invention in the order of steps. In each of FIGS. 27 to 30, the cross section of the memory cell forming portion is shown on the left side and the cross section of the peripheral circuit forming portion is shown on the right side.

  First, as shown in FIG. 27A, a pad oxide film 51 is formed on the semiconductor substrate 10 by, eg, thermal oxidation, and a silicon nitride film 52 is formed thereon by CVD. Instead of the silicon nitride film 52, a film having a stacked structure of a silicon oxide layer and a silicon nitride layer may be formed.

  Next, as shown in FIG. 27B, a resist film 53 having an opening at a portion corresponding to the element isolation region of the memory cell formation portion is formed on the silicon nitride film 52. Then, the silicon nitride film 52 and the pad oxide film 51 are sequentially etched using the resist film 53 as a mask, and then the semiconductor substrate 10 is further etched to form a shallow groove (trench) 54. Thereafter, the resist film 53 is removed.

Next, heat treatment is performed in a hydrogen atmosphere at about 800 ° C. As a result, the upper edge portion of the groove 54 contracts, and a gap is formed between the semiconductor substrate 10 and the pad oxide film 51 at the upper edge portion of the groove 54 as shown in FIG. Hydrogen is preferably diluted with a gas such as Ar (argon) or N ₂ (nitrogen).

  Next, a resist film (not shown) having an opening at a portion corresponding to the element isolation region of the peripheral circuit formation portion is formed. Then, after etching the silicon nitride film 52 using this resist film as a mask, the resist film is removed. Thereafter, using the silicon nitride film 52 as a mask, the pad oxide film 51 and the semiconductor substrate 10 in the peripheral circuit forming portion are etched to form a shallow groove 55 as shown in FIG.

  Next, for example, heat treatment is performed in an atmosphere having a temperature of 850 to 1100 ° C. and an oxygen concentration of 10%, and as shown in FIG. 29A, the inner surface of the grooves 54 and 55 is oxidized to a thickness of 5 nm or more. A silicon film 56 is formed.

  At this time, in the present embodiment, since the semiconductor substrate 10 is exposed at the upper edge of the groove 54, a thick oxide film (bird's beak) is formed as shown in FIG. The semiconductor substrate 10 has a rounded edge.

  Next, as shown in FIG. 29B, silicon oxide is deposited on the entire upper surface of the semiconductor substrate 10 by high-density plasma CVD to form a silicon oxide film 57, and the groove 54.55 is filled with silicon oxide. Thereafter, the silicon oxide film 57 and the silicon nitride film 52 are polished by, eg, CMP to planarize the surface. In this step, the silicon oxide in the grooves 54 and 55 may be separated from each other, and the polishing is finished before the silicon nitride film 52 is completely removed.

  Next, as shown in FIG. 30A, the silicon nitride film 52 is removed by wet etching using, for example, hot phosphoric acid. Hereinafter, the film made of silicon oxide in the groove 54 of the memory cell formation portion is called an element isolation film 58a, and the film made of silicon oxide in the groove 55 of the peripheral circuit formation portion is called an element isolation film 58b.

  Next, the pad oxide film 51 is etched to expose the surface of the substrate 10. At this time, the element isolation films 58a and 58b are also etched to reduce the film thickness. Thereafter, the surface of the semiconductor substrate 10 exposed by the etching of the pad oxide film 51 is thermally oxidized to form a tunnel oxide film 59a in the memory cell forming portion and in the peripheral circuit forming portion as shown in FIG. A gate oxide film 59b is formed.

  Next, as in the first embodiment, a floating gate, an intermediate insulating film, and a control gate are formed in the memory cell forming portion, a gate electrode is formed in the peripheral circuit forming portion, an interlayer insulating film, a bit line, and others Are formed (see FIG. 10). In this way, the flash memory is completed.

  Also in the present embodiment, the curvature of the interface between the upper edge of the element isolation film 57a and the semiconductor substrate 10 is increased in the memory cell formation portion, and the interface between the element isolation film 57b and the semiconductor substrate 10 is increased in the peripheral circuit formation portion. Curvature decreases. Therefore, also in the present embodiment, the same effect as in the first embodiment can be obtained.

(Sixth embodiment)
31 to 34 are cross-sectional views showing a method of manufacturing a semiconductor device (flash memory) according to a sixth embodiment of the present invention in the order of steps. 31 to 34, the left side of the drawing shows the cross section of the memory cell formation portion, and the right side shows the cross section of the peripheral circuit formation portion.

  First, as shown in FIG. 31A, a pad oxide film 61 is formed on the semiconductor substrate 10 by, eg, thermal oxidation, and a silicon nitride film 62 is formed thereon by CVD.

  Next, as shown in FIG. 31B, the silicon nitride film 62 in the memory cell formation portion is patterned by photolithography, and the pad oxide film 61 and the semiconductor substrate 10 are further etched to form a shallow groove 63. To do.

  Next, as shown in FIG. 32A, for example, heat treatment is performed in an atmosphere having a temperature of 850 to 1100 ° C. and an oxygen concentration of 10%, and a silicon oxide film 64 having a thickness of 5 nm or more is formed on the inner surface of the groove 63. Form.

  Next, as shown in FIG. 32B, the silicon nitride film 62 in the peripheral circuit forming portion is patterned by photolithography, and the pad oxide film 61 and the semiconductor substrate 10 are further etched to form a shallow groove 65. .

  Next, as shown in FIG. 33A, for example, heat treatment is performed in an atmosphere having a temperature of 850 to 1100 ° C. and an oxygen concentration of 10%, and a silicon oxide film 66 having a thickness of 5 nm or more is formed on the inner surface of the groove 65. Form.

  At this time, since the upper edge portion of the groove 63 in the memory cell region is already oxidized and rounded when the silicon oxide film 64 is formed, the oxygen supply amount is relatively large and the oxide film is thick. (Birds beak) is formed, and the curvature of the edge of the semiconductor substrate 10 around the groove 63 is increased.

  Next, as shown in FIG. 33B, silicon oxide is deposited on the entire upper surface of the semiconductor substrate 10 by high-density plasma CVD to form a silicon oxide film 67, and the grooves 63 and 65 are filled with silicon oxide. Thereafter, the silicon oxide film 67 and the silicon nitride film 62 are polished by, for example, CMP to planarize the surface. In this step, the silicon oxide in the grooves 63 and 65 may be separated from each other, and the polishing is finished before the silicon nitride film 62 is completely removed.

  Next, as shown in FIG. 34A, the silicon nitride film 62 is removed by wet etching using, for example, hot phosphoric acid. Hereinafter, the film made of silicon oxide in the groove 63 of the memory cell formation portion is called an element isolation film 68a, and the film made of silicon oxide in the groove 65 of the peripheral circuit formation portion is called an element isolation film 68b.

  Next, the pad oxide film 61 is etched to expose the surface of the substrate 10. At this time, the element isolation films 68a and 68b are also etched to reduce the film thickness. Thereafter, the surface of the semiconductor substrate 10 exposed by the etching of the pad oxide film 61 is thermally oxidized to form a tunnel oxide film 69a in the memory cell forming portion and in the peripheral circuit forming portion as shown in FIG. A gate oxide film 69b is formed.

  Next, as in the first embodiment, a floating gate, an intermediate insulating film, and a control gate are formed in the memory cell forming portion, a gate electrode is formed in the peripheral circuit forming portion, an interlayer insulating film, a bit line, and others Are formed (see FIG. 10). In this way, the flash memory is completed.

  In the present embodiment, the curvature of the edge of the semiconductor substrate 10 around the groove 63 is increased by thermally oxidizing the wall surface of the groove 63 of the memory cell formation portion twice. Thereby, the effect similar to 1st Embodiment can be acquired.

  In the present embodiment, after the silicon oxide film 64 is formed on the inner surface of the groove 64, the silicon oxide film 64 may be removed. This facilitates embedding of silicon oxide in the trench 64 when forming the silicon oxide film 67 and increases the curvature of the upper edge portion of the trench 64 when forming the silicon oxide film 66. it can.

  In the first to sixth embodiments described above, the case where the present invention is applied to a method for manufacturing a flash memory has been described. However, the scope of the present invention is limited to the flash memory and the method for manufacturing the same. It is not something. The present invention can be applied to various semiconductor device manufacturing methods in which a memory cell operating at a high voltage and a transistor operating at a low voltage are formed on the same semiconductor substrate.

  Matters related to the present invention will be collectively described as additional notes.

  (Supplementary Note 1) A plurality of first elements formed in a first region of a semiconductor substrate, a first groove formed between the first elements in the first region, and the first groove A first element isolation film made of an insulating material filling the semiconductor element, a plurality of second elements formed in a second region of the semiconductor substrate and supplied with a higher voltage than the first element, A second groove formed between the second elements in a second region; and a second element isolation film made of an insulating material filling the second groove; A semiconductor device, wherein a curvature of an interface between an upper edge of the isolation film and the semiconductor substrate is larger than a curvature of an interface between the upper edge of the first element isolation film and the semiconductor substrate.

  (Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the second element is a memory cell of a nonvolatile semiconductor memory.

  (Supplementary note 3) The semiconductor device according to supplementary note 2, wherein the first element is a MOS transistor.

  (Appendix 4) Forming a plurality of first grooves in the first region of the semiconductor substrate and forming a plurality of second grooves in the second region, and a curvature of the upper edge of the second groove A step of filling the first and second grooves with an insulating material, a first element is formed in the first region, and is higher than the first element in the second region Forming a second element to which a voltage is supplied, and a method for manufacturing a semiconductor device.

  (Supplementary note 5) The semiconductor device according to supplementary note 4, wherein the first element is a MOS transistor, and the second element is a memory cell of a nonvolatile semiconductor memory.

  (Additional remark 6) The process of forming a 1st insulating film in the 1st and 2nd area | region of a semiconductor substrate, and a 2nd insulating film with a material different from the said 1st insulating film on the said 1st insulating film Forming the first insulating film, patterning the second insulating film, etching the first insulating film and the semiconductor substrate using the second insulating film as a mask, and forming the first region of the semiconductor substrate Forming a first groove in the second region, forming a second groove in the second region, side-etching only the first insulating film in the second region, and A step of oxidizing the inner surface of the second groove, a step of filling an insulating material in the first and second grooves to form a first element isolation film and a second element isolation film, and the second insulation. And a step of removing the film.

  (Supplementary note 7) The method of manufacturing a semiconductor device according to supplementary note 6, wherein the first insulating film is formed of silicon oxide, and the second insulating film is formed of silicon nitride.

  (Supplementary Note 8) After the step of removing the second insulating film, between the step of removing the first insulating film in the first and second regions, and between the first grooves in the first region The method of manufacturing a semiconductor device according to appendix 6, further comprising: forming a third insulating film and forming a fourth insulating film between the second grooves in the second region.

  (Supplementary note 9) The method of manufacturing a semiconductor device according to supplementary note 8, further comprising forming a MOS transistor in the first region and forming a memory cell in the second region.

  (Additional remark 10) A 1st insulating film is formed in the 1st area | region of a semiconductor substrate, and a film thickness is larger than a said 1st insulating film with the same insulating material as a said 1st insulating film in a 2nd area | region. Forming a second insulating film; forming a third insulating film on the first and second insulating films with an insulating material different from that of the first and second insulating films; Patterning the third insulating film, etching the first and second insulating films and the semiconductor substrate using the third insulating film as a mask, and forming a first groove in the first region, Forming a second groove in the second region; oxidizing the inner surfaces of the first and second grooves; and embedding an insulating material in the first and second grooves to form a first element And a step of forming an isolation film and a second element isolation film, and a step of removing the second insulating film. The method of manufacturing a semiconductor device.

  (Supplementary note 11) The method for manufacturing a semiconductor device according to supplementary note 10, wherein the first and second insulating films are formed of silicon oxide, and the third insulating film is formed of silicon nitride.

  (Supplementary note 12) The method of manufacturing a semiconductor device according to Supplementary note 10, further comprising forming a MOS transistor in the first region and forming a memory cell in the second region.

  (Additional remark 13) The process of forming a 1st insulating film in the 1st and 2nd area | region of a semiconductor substrate, and a 2nd insulating film with an insulating material different from the said 1st insulating film on the said 1st insulating film Forming a resist film on the second insulating film, patterning the resist film in the first region, and using the resist film as a mask, the second region in the second region. Etching the insulating film, the first insulating film, and the semiconductor substrate, forming a first groove having a width narrower than the opening of the resist film, removing the resist film, Patterning the second insulating film in one region; etching the first insulating film and the semiconductor substrate using the second insulating film in the first region as a mask; and The second of the same width as the opening of the second insulating film Forming a groove; oxidizing the inner surfaces of the first and second grooves; and embedding an insulating material in the first and second grooves to form a first element isolation film and a second element isolation. A method of manufacturing a semiconductor device, comprising: forming a film; and removing the second insulating film.

  (Supplementary note 14) The method of manufacturing a semiconductor device according to supplementary note 13, wherein the first insulating film is formed of silicon oxide, and the second insulating film is formed of silicon nitride.

  (Supplementary note 15) The method of manufacturing a semiconductor device according to Supplementary note 13, further comprising forming a MOS transistor in the first region and forming a memory cell in the second region.

  (Supplementary Note 16) A first insulating film is formed in a first region of a semiconductor substrate, and the second insulating layer is made of the same insulating material as that of the first insulating film and has a thickness larger than that of the first insulating film. A step of forming two insulating films, a step of forming a semiconductor film on the first and second insulating films, and an insulating material different from that of the first and second insulating films on the semiconductor film. Forming the third insulating film; patterning the third insulating film; and using the third insulating film as a mask, the semiconductor film, the first and second insulating films, and the semiconductor substrate. Etching, forming a first groove in the first region, forming a second groove in the second region, oxidizing the inner surfaces of the first and second grooves, A process of forming a first element isolation film and a second element isolation film by filling an insulating material in the first and second grooves. The method of manufacturing a semiconductor device characterized by having and.

  (Supplementary note 17) The method of manufacturing a semiconductor device according to supplementary note 16, wherein the first and second insulating films are formed of silicon oxide, and the third insulating film is formed of silicon nitride.

  (Supplementary note 18) The method of manufacturing a semiconductor device according to supplementary note 16, further comprising forming a MOS transistor in the first region and forming a memory cell in the second region.

  (Supplementary note 19) The method of manufacturing a semiconductor device according to supplementary note 16, further comprising forming at least one gate electrode of the MOS transistor and the memory cell using the semiconductor film.

  (Appendix 20) Forming a first insulating film in the first and second regions of the semiconductor substrate, and a second insulating film on the first insulating film with an insulating material different from the first insulating film Forming a first groove by etching the second insulating film, the first insulating film, and the semiconductor substrate in the second region, and performing a heat treatment in a hydrogen atmosphere. A step of forming a gap between the upper edge of the first groove and the first insulating film, and the second insulating film, the first insulating film, and the semiconductor in the first region Etching the substrate to form a second groove; oxidizing the inner surfaces of the first and second grooves; and filling the first and second grooves with an insulating material to form a first element And a step of forming an isolation film and a second element isolation film, and a step of removing the second insulating film. Method of manufacturing a semiconductor device that.

  (Supplementary note 21) The method for manufacturing a semiconductor device according to supplementary note 20, wherein the first insulating film is formed of silicon oxide, and the second insulating film is formed of silicon nitride.

  (Supplementary note 22) The method of manufacturing a semiconductor device according to supplementary note 20, further comprising forming a MOS transistor in the first region and forming a memory cell in the second region.

  (Supplementary Note 23) A step of forming a first insulating film in the first and second regions of the semiconductor substrate, and a second insulation with an insulating material different from that of the first insulating film on the first insulating film Forming a film; etching the second insulating film in the second region; the first insulating film; and the semiconductor substrate to form a first groove; and Oxidizing the surface; etching the second insulating film in the first region; the first insulating film; and the semiconductor substrate to form a second groove; and The inner surface is oxidized and the inner surface of the first groove is further oxidized to change the curvature of the interface between the upper edge of the first groove and the semiconductor substrate, and the upper edge of the second groove and the semiconductor substrate. A step of making the curvature larger than the curvature of the interface between the first and second grooves, and filling the first and second grooves with an insulating material. The method of manufacturing a semiconductor device, characterized in that it comprises a step of forming a film and the second isolation layer, and removing the second insulating film.

  (Supplementary note 24) The method of manufacturing a semiconductor device according to supplementary note 23, wherein the first insulating film is formed of silicon oxide, and the second insulating film is formed of silicon nitride.

  (Supplementary note 25) The method of manufacturing a semiconductor device according to supplementary note 23, further comprising forming a MOS transistor in the first region and forming a memory cell in the second region.

FIG. 1 is a cross-sectional view (No. 1) showing a conventional method for manufacturing a semiconductor device (flash memory). FIG. 2 is a sectional view (No. 2) showing a conventional method of manufacturing a semiconductor device (flash memory). FIG. 3 is a sectional view (No. 3) showing a conventional method for manufacturing a semiconductor device (flash memory). FIG. 4 is a sectional view (No. 4) showing a conventional method for manufacturing a semiconductor device (flash memory). FIG. 5 is an enlarged view showing the shape of the upper edge portion of the element isolation film. FIG. 6 is a sectional view (No. 1) showing the method for manufacturing the semiconductor device (flash memory) according to the first embodiment of the invention. FIG. 7 is a cross-sectional view (No. 2) showing the method for manufacturing the semiconductor device (flash memory) of the first embodiment of the present invention. FIG. 8 is a cross-sectional view (No. 3) showing the method for manufacturing the semiconductor device (flash memory) of the first embodiment of the present invention. FIG. 9 is a cross-sectional view (No. 4) showing the method for manufacturing the semiconductor device (flash memory) of the first embodiment of the present invention. FIG. 10 is a sectional view (No. 5) showing the method for manufacturing the semiconductor device (flash memory) according to the first embodiment of the invention. FIG. 11A is an enlarged view showing the upper edge of the groove of the memory cell formation portion of the semiconductor device of the first embodiment, and FIG. 11B is the upper side of the groove of the peripheral circuit formation portion. It is a figure which expands and shows an edge part. FIG. 12 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device (flash memory) of the second embodiment of the present invention. FIG. 13 is a cross-sectional view (No. 2) showing the method for manufacturing the semiconductor device (flash memory) of the second embodiment of the present invention. FIG. 14 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device (flash memory) of the second embodiment of the present invention. FIG. 15 is a cross-sectional view (No. 4) showing the method for manufacturing the semiconductor device (flash memory) of the second embodiment of the present invention. FIG. 16 is a sectional view (No. 5) showing the method for manufacturing the semiconductor device (flash memory) of the second embodiment of the present invention. FIG. 17 is a cross-sectional view (No. 1) showing the method for manufacturing the semiconductor device (flash memory) of the third embodiment of the present invention. FIG. 18 is a cross-sectional view (No. 2) showing the method for manufacturing the semiconductor device (flash memory) of the third embodiment of the present invention. FIG. 19 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device (flash memory) of the third embodiment of the present invention. FIG. 20 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device (flash memory) of the third embodiment of the present invention. FIG. 21 is a cross-sectional view (No. 1) showing the method for manufacturing the semiconductor device (flash memory) of the fourth embodiment of the present invention. FIG. 22 is a cross-sectional view (No. 2) showing the method for manufacturing the semiconductor device (flash memory) of the fourth embodiment of the present invention. FIG. 23 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device (flash memory) according to the fourth embodiment of the present invention. FIG. 24 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device (flash memory) according to the fourth embodiment of the present invention. FIG. 25 is a cross-sectional view (No. 5) showing the method for manufacturing the semiconductor device (flash memory) of the fourth embodiment of the present invention. FIG. 26A is an enlarged view showing the shape of the upper edge portion of the element isolation film of the memory cell formation portion of the semiconductor device of the fourth embodiment, and FIG. 26B is the element isolation of the peripheral circuit formation portion. It is a figure which expands and shows the shape of the upper edge part of a film | membrane. FIG. 27 is a cross-sectional view (No. 1) showing the method for manufacturing the semiconductor device (flash memory) of the fifth embodiment of the present invention. FIG. 28 is a cross-sectional view (No. 2) showing the method for manufacturing the semiconductor device (flash memory) of the fifth embodiment of the present invention. FIG. 29 is a cross-sectional view (No. 3) showing the method for manufacturing the semiconductor device (flash memory) of the fifth embodiment of the present invention. FIG. 30 is a cross-sectional view (No. 4) showing the method for manufacturing the semiconductor device (flash memory) of the fifth embodiment of the present invention. FIG. 31 is a cross-sectional view (No. 1) showing the method for manufacturing the semiconductor device (flash memory) according to the sixth embodiment of the invention. FIG. 32 is a cross-sectional view (No. 2) illustrating the method for manufacturing the semiconductor device (flash memory) according to the sixth embodiment of the invention. FIG. 33 is a cross-sectional view (No. 3) showing the method for manufacturing the semiconductor device (flash memory) of the sixth embodiment of the present invention. FIG. 34 is a cross-sectional view (No. 4) showing the method for manufacturing the semiconductor device (flash memory) of the sixth embodiment of the present invention.

Explanation of symbols

10, 100 ... semiconductor substrate,
11, 21, 22a, 22b, 31, 41, 42a, 42b, 51, 61, 101 ... pad oxide film,
12, 23, 32, 44, 52, 62, 102 ... silicon nitride film,
13a, 13b, 24a, 24b, 34, 35, 45a, 45b, 54, 55, 63, 65, 103a, 103b ... grooves (trench),
15, 25, 26, 36, 37, 46, 47, 56, 57, 64, 66, 67, 105 ... silicon oxide film,
16a, 16b, 27a, 27b, 38a, 38b, 48a, 48b, 58a, 58b, 68a, 68b, 106a, 106b ... element isolation film,
17a, 28a, 39a, 59a, 69a, 107a ... tunnel oxide film,
17b, 28b, 39b, 59b, 69b, 107b... Gate oxide film,
18, 108a ... floating gate,
19, 109 ... intermediate insulating film,
20a, 110a ... control gate,
20b, 110b ... gate electrodes,
21, 111 ... interlayer insulating film,
22a, 112a ... bit lines,
22b, 112b ... wiring,
33, 53 ... resist film,
43 ... Polysilicon film.

Claims (3)

A first insulating film made of silicon oxide is formed in the first region of the semiconductor substrate, and the second insulating layer is made of the same insulating material as the first insulating film and has a thickness larger than that of the first insulating film Forming a second insulating film;
Forming a third insulating film on the first and second insulating films with an insulating material different from that of the first and second insulating films;
Patterning the third insulating film;
Etching the first and second insulating films and the semiconductor substrate using the third insulating film as a mask, forming a first groove in the first region, and forming a second groove in the second region Forming, and
Oxidizing the inner surfaces of the first and second grooves;
Filling the first and second trenches with an insulating material to form a first element isolation film and a second element isolation film;
Removing the second insulating film;
Forming a non-volatile memory cell in the second region. A method for manufacturing a semiconductor device, comprising: A first insulating film made of silicon oxide is formed in a first region of the semiconductor substrate, and a second insulating film is made of the same insulating material as the first insulating film and has a thickness larger than that of the first insulating film. Forming an insulating film of 2;
Forming a semiconductor film on the first and second insulating films;
Forming a third insulating film on the semiconductor film with an insulating material different from that of the first and second insulating films;
Patterning the third insulating film;
The semiconductor film, the first and second insulating films, and the semiconductor substrate are etched using the third insulating film as a mask to form a first groove in the first region, and in the second region Forming a second groove;
Oxidizing the inner surfaces of the first and second grooves;
Filling the first and second trenches with an insulating material to form a first element isolation film and a second element isolation film;
Forming a non-volatile memory cell in the second region. A method for manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a MOS transistor in the first region.

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