JP4297553B2 - Game machine - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present inventionGame machineIn particular, an arithmetic processing device for games that acquires game control information being executed and contributes to game management and the likeA gaming machine equipped withRegarding improvements.
[0002]
[Prior art]
  In a ball game machine or a revolving game machine (hereinafter referred to as a “game machine”), a game control part is constituted by a microcomputer and a so-called amusement chip that is made into one chip is mounted on a game board. In addition to game control, various peripheral circuits are required on the game board, which is not sufficient in terms of mounting cost and reliability. In recent years, several peripheral circuits have been incorporated into the same chip to reduce costs. And improving reliability.
[0003]
  One of the peripheral circuits incorporated in the chip is a circuit for monitoring the state of game control. If this circuit is called a “management block” for convenience, the main role of the management block is to evaluate the legitimacy of the game program and monitor various data during the execution of the game program.
[0004]
  For example, since the game program is stored in the program ROM in the amusement chip, the program can be read by the CPU in the chip and passed to the management block, or the data during execution of the game program can be stored in the user work in the amusement chip. Since the data is stored in the RAM, the data is similarly read out by the CPU and passed to the management block.
[0005]
[Problems to be solved by the invention]
  However, in the above method, since the game program and the data being executed are transferred to the management block with the CPU in the amusement chip as an intermediary, for example, if data is acquired in real time during the game, the CPU operation program (I.e., the game program) must have processing steps for data intermediation, and such program processing requires extra execution time of the program for data acquisition, so the number of game machine detections is limited. It is not suitable as a game machine program that needs to be executed in a short time such as milliseconds. In other words, since the time factor of processing directly affects the profit of the amusement store while the gaming machine is in operation, the execution time becomes the profit of the amusement store when the functions other than the minimum necessary functions are included in the program. Since it is necessary to verify how much it affects each time a game machine is developed, it can be said that development efficiency is not good. Therefore, there is no way to acquire data using a state in which the gaming machine is not in operation (for example, when a boot program immediately after system reset is activated), and real-time data acquisition cannot be performed. There is a point.
[0006]
  Therefore, an object of the present invention is to allow a game program and data being executed to be transferred to a management block without intermediating the CPU, thereby enabling real-time data acquisition during the game.
[0007]
[Means for Solving the Problems]
  The invention described in claim 1In a gaming machine equipped with a game control device configured by storing a board in a case together with a game processing unit for controlling a game state,
  The gaming arithmetic processing device comprises:
  It is divided into a game block that performs game control and a management block that performs information management, and is formed as an integrated circuit.
  The game block is
  A program ROM storing game programs;
  A CPU that executes the game program and controls the gaming machine;
  A user work RAM for providing a work area necessary for execution of the game program;
  The program ROM and the userworkA CPU bus connecting the RAM and the CPU;
  An external bus interface for interfacing with the outside of the gaming processing unit using an address signal and a data signal;
  Comprising
  The management block is
  AboveA boot ROM that stores a boot program that performs a predetermined simple check when the gaming arithmetic processing unit is turned on and passes the process to a predetermined address of the game program if the simple check is normal;
  Monitors the state of the CPU bus, and accesses the program ROM and the user work RAM via the CPU bus when the CPU bus is not used by the CPU, and takes in necessary data to the management block side. A bus monitor circuit;
  Security memory where unique ID and manufacturer code are written,
  A management work RAM for holding the contents of the program ROM read through the bus monitor circuit and the contents of the user work RAM;
  Based on a command from the outside, information on the game block side stored in the management work RAM is obtained.After performing encryption processingAn external communication control circuit for transferring to the outside;
  Controls the operation on the management block side, detects the release period of the CPU bus via the bus monitor circuit, reads the contents of the program ROM and the contents of the user work RAM, and writes them to the management work RAM And a control circuit for transferring the contents of the management work RAM to the outside in response to a command from the outside,
  A management bus for connecting the bus monitor circuit, security memory, management work RAM, external communication control circuit, and control circuit;
  Have
  In addition, a part of the CPU bus on the game block side is included, and the boot ROM and a bus monitor circuit are connected to the CPU bus,
  During the release period of the CPU bus, the contents of the program ROM and user work RAM are read and written to the management work RAM, and the written contents are transferred to the outside in response to an external command.With
The gaming arithmetic processing unit, while generating the write mode of the program ROM, sequentially increments the address signal to the program ROM from the outside of the gaming arithmetic processing unit via the data signal. Write a game programIt is characterized by that.
According to a second aspect of the present invention, the gaming arithmetic processing device includes a recording area for storing a writing end code indicating the end of writing of the game program to the program ROM, and the recording area includes a predetermined bit. The write end code is recorded by physically cutting the line.
  According to a third aspect of the present invention, the game arithmetic processing unit is characterized in that the write mode of the program ROM occurs when the MODE signal input from the outside of the game arithmetic processing unit becomes H level. .
[0008]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking as an example a game store (hereinafter referred to as a “hall”) in which a large number of pachinko gaming machines are installed.
[0009]
・ Hall structure
  FIG. 1 is a block diagram showing the overall structure of the hall. In FIG. 1, reference numeral 1 denotes a hall. In the hall 1, a pachinko island 11 in which a number of CR (card reader) type gaming machines 10j (j is a, b... , Auxiliary state change information recording device JRs, history processing device 12, counter computer CC, FAX device 13, office computer HC, printer 14, communication control devices 15-18, ball counter 19, island safe 20, surveillance camera A system 21, an announcement system 22, and a setting / inspection apparatus 23 are arranged. The setting / inspection device 23 isPermanentNot. Connected to the in-store network 37 whenever necessary.
[0010]
  Pachinko island 11 includes information collection terminal devices 31a and 31b (hereinafter also referred to as “information collection terminal device 31” as appropriate), gaming machines 10a and 10b (same “gaming machine 10”), card-type balls Lending device 32a, 32b (same as "card-type ball lending device 32"), ball cutting device 33a, 33b ("ball cutting device 33"), pulse tanks 34a, 34b ("pulse tank 34") and network relay device 35 (for example, a router). A plurality of pachinko islands 11 are arranged in the hall 1, but each “island” has a similar configuration (however, the type of gaming machine is different for each island), so here, one pachinko island 11 is used. Will be described.
[0011]
  One network relay device 35 is arranged for each pachinko island 11, but the other devices (for example, the information collecting terminal device 31, the ball cutting device 33, and the pulse tank 34) are the gaming machines 10a and 10b. The same number (that is, paired with the gaming machine 10) is arranged.
[0012]
  The gaming machine 10 has game control devices 41a and 41b (hereinafter appropriately represented by "game control device 41") for controlling the game state, and the game control device 41 is used for gaming to control an accessory. An arithmetic processing device (simply referred to as “arithmetic processing device” in the drawing) 200 (this is an IC for a so-called amuse chip, the detailed configuration of which will be described later) is incorporated. The game control device 41 includes a game control board and a case for housing the board.
[0013]
  A card-type ball lending device 32 is arranged on the side of the gaming machine 10, and a ball lending operation using a prepaid card (PC) can be performed by the gaming machine 10.
[0014]
  The ball cutting device 33 replenishes balls from the pachinko island 11 to the replenishment tank of the gaming machine 10, for example, a signal that becomes one pulse every time 10 balls are replenished (a replenishment ball number signal shown in FIG. 2 described later). ) Is output from the ball cutter 33. The pulse tank 34 counts the balls after the game collected from the gaming machine 10 to the outside. For example, the pulse tank 34 outputs a signal (which will be described later) which becomes one pulse every 10 outflows (collection) of the balls. The collected ball number signal shown in FIG. 2 is output.
[0015]
  The information collection terminal device 31 includes PJ1 and PJ2, and distribution circuits 42a and 42b (hereinafter, appropriately represented by “distribution circuit 42”). The distribution circuit 42 is connected to the gaming machine 10, the card-type ball lending device 32, the ball cutting device 33, and the pulse tank 34, and distributes and transfers signals input / output from these devices to PJ1 and PJ2. For example, the distribution circuit 42 distributes and transfers the sales signal, supply ball number signal, recovered ball number signal, jackpot signal, special figure rotation signal, probability variation signal, and amuse communication signal to PJ1, and hits PJ2. Stop signal, metal frame opening / closing signal, wooden frame opening / closing signal, empty pan signal (signal for detecting that the amount of balls replenished from the pachinko island 11 to the storage tank of the gaming machine 10), abnormal signal (incorrect electromagnetic wave) Distributes and transmits a signal to detect an illegal magnetic force and electromagnetic wave) and a power-off signal.
[0016]
  PJ1 is based on the sales signal, the supply ball number signal, the collected ball number signal, the jackpot signal, the special figure rotation signal, the probability change signal, and the amuse communication signal inputted / outputted from the game control device 41, and the gaming machine 10 and the game The game information output from the equipment and the game information (state change information) transferred from the PJ2 are calculated and processed, and processing for detecting changes in the game information from the collected game information is performed. The correctness determination (true / false determination) of the arithmetic processing unit 200 is also performed, and the detailed block configuration will be described later.
[0017]
  PJ2 is a process for transferring state change information (for example, a gold frame opening signal, an empty pan signal, etc.) collected mainly from gaming machine 10 and gaming equipment to PJ1 and a request to stop firing from PJ1. When there is, the process etc. which make the gaming machine 10 impossible are performed.
[0018]
  The network relay device 35 has, for example, a router function, and is a device that relay-connects between the LONs in the island network 36 and the store network 37. The island network 36 employs LON (LON (Local Operating Network: a registered trademark of the company) developed by Echalon, USA).
[0019]
  Pachinko island 11 is connected to JR, JRs, history processing device 12, CC, HC, communication control devices 15-18, and setting / inspection device 23 via island network 36, network relay device 35 and store network 37. . Similarly, LON is adopted for the in-store network 37.
[0020]
  The intra-island network 36, the network relay device 35, and the in-store network 37 constitute a communication network 61 (also referred to as “LON communication network”) that connects PJ1, PJ2, JR, CC, and HC as a whole.
[0021]
  One JR is provided in Hall 1. For example, one is installed for 500 gaming machines. Or when there are multiple floors, one may be installed for each floor. JR organizes and records game information (state change information) reported from PJ1 of each pachinko island 11 for each gaming machine, and JRs backs up JR.
[0022]
  The history processing device 12 is a device for recording error information from PJ1, PJ2, JR, JRs, etc. connected to the in-store network 37. The error history is analyzed after the failure (PJ1, PJ2,. Node to which JR, JRs, etc. are connected).
[0023]
  A general-purpose personal computer can be used as the CC. The CC collects the state change information of the gaming machine 10 on the current day by polling JR or JRs, and performs a process of detecting and displaying the state change. Generally, in the state change information, the big hit or the probability fluctuation is usually required to check the detailed game information of the gaming machine 10 in which the event has occurred in the CC. Game information is collected from 10 PJ1, and detailed game information is displayed together with the previous state change information. If the JR has trouble and cannot collect information, it immediately switches to the backup JRs and collects and displays the same information.
[0024]
  Furthermore, when it is desired to check the game information of the desired gaming machine 10 through the CC, there is also a function of collecting and displaying the game information directly from the corresponding PJ1. CC and HC are connected by a dedicated network cable 62 (for example, Ethernet). If you want to check management information such as sales, model information, and time series information on CC, obtain the information from HC. Can be displayed.
[0025]
  Note that a fax machine 13 is connected to the CC, and information collected and analyzed by the CC can be processed into a predetermined print format and transmitted to the outside.
[0026]
  A general-purpose personal computer can also be used for the HC. HC generates various information that contributes to management decisions based on game information for the day and the past, collects game information by polling PJ1 or PJ2 at predetermined intervals, records it on a hard disk, etc. It can be displayed or printed in a predetermined format. In addition, when it is desired to check game information of a specific gaming machine 10 by HC, there is also a function of collecting and displaying game information directly from the corresponding PJ1. Further, when it is desired to confirm the state change information (real system information) of the gaming machine 10 by the HC, the information can be obtained from the CC via the network cable 62 and displayed. Note that a printer 14 is connected to the HC, and the collected information can be printed in a predetermined format. CC and HC constitute a management device that manages the entire game information of the game store 1.
[0027]
  The communication control devices 15 to 18 are devices that perform a communication interface between the ball counter 19, the island safe 20, the surveillance camera system 21, the announcement system 22, and the in-store network 37.
[0028]
  The ball counter 19 counts the spheres obtained by the player (for example, for exchanging prizes), transfers the count value to the CC and HC, and prints a counting result paper piece for exchanging prizes to the player. Out and output. The island safe 20 is a device for storing coins and banknotes collected from a money changer, a cash-type ball lending device or the like provided in the hall 1, and transfers the current storage amount to the HC and CC one by one.
[0029]
  The surveillance camera system 21 is a system that manages the surveillance cameras arranged in the hall 1 and records the captured images, and the announcement system 22 is a system that performs announcements in the hall 1 manually and automatically.
[0030]
  For example, a notebook personal computer can be used as the setting / inspection apparatus 23. The setting / inspection device 23 can be connected to the in-store network 37 as needed, automatically acquires an account of the LON communication network at the time of connection, and is built in the game control device 41 of the gaming machine 10 connected to an arbitrary PJ1. The game processing unit 200) can be accessed to set a unique ID for determining validity.
[0031]
  As described above, the setting / inspection device 23 is connected to the in-store network 37 "when necessary". For example, when it is necessary to replace it with a new machine, the setting / inspection device 23 is connected to the in-store network 37 after the exchange, and the game control device of the machine (replaced gaming machine 10) via the new machine PJ1. 41, the game processing unit 200 built in 41 is accessed to set a unique ID for determining validity.
[0032]
  In addition, when determining the legitimacy of the game processing unit 200 at PJ1, in addition to the above-described unique ID determination, a game program may be used as determination information. The same reference game program as the game program built in the processing device 200 is set from the setting / inspection device 23 to PJ1. The PJ1 reads out the game program from the game arithmetic processing device 200, and compares with the set reference game program to determine the validity.
[0033]
・ Configuration of PJ1
  Next, the block configuration of PJ1 will be described. FIG. 2 is a block diagram of PJ1. In FIG. 2, PJ1 includes a CPU 51, ROM 52, RAM 53, EEPROM 54, backup power supply 55, oscillation circuit 56, communication control device 57, output interface (I / F) 58, input interface (I / F) 59, and bus 60. Yes.
[0034]
  Based on the processing program stored in the ROM 52, the CPU 51 calculates and processes the game information output from the gaming machine 10 and the game equipment device that it is responsible for and the game information (state change information) transferred from the PJ2, A process for detecting a change in game information from the collected game information is performed, and the validity of the game processing unit 200 is also determined. The ROM 52 stores a processing program for determining the legitimacy of the gaming arithmetic processing device 200 and a processing program for collecting and processing game information, and the RAM 53 is used as a work area.
[0035]
  The EEPROM 54 stores the unique ID of the game processing device 200 connected to the PJ1. The procedure for storing the unique ID in the EEPROM 54 is performed by the setting / inspection device 23. The EEPROM 54 also stores setting values for monitoring state change information. This set value is set by CC or HC.
[0036]
  The backup power supply 55 is a power supply for holding the information stored in the RAM 53 even during a power failure. The oscillation circuit 56 supplies a control clock signal to the CPU 51, and the communication control device 57 performs communication control between the PJ1 and another network terminal via the island network 36. The communication control device 57 stores a different monitoring device ID for each device, and the monitoring device ID is used to identify the PJ1 when transmitting / receiving information.
[0037]
  The output interface 58 performs an output interface process between the gaming machine 10 and the CPU 51, and an amuse communication signal (for example, a program request command) is output from the output interface 58 to the game control device 41 of the gaming machine 10. .
[0038]
  The input interface 59 performs input interface processing between the gaming machine 10 and the game equipment (ball rental device 32, etc.) and the CPU 51, and includes an amuse communication signal, a sales signal by a card from the card-type ball rental device 32C, Sales signal by cash from the cash-type ball lending device 32G, replenishing ball number signal from the ball cutting device 33, recovered ball number signal from the pulse tank 34, special figure rotation signal from the game control device 41 (rotation of special figure) ), A jackpot signal, and a probability change signal (signals that notify the probability change and the jackpot game).
[0039]
  Here, PJ1 and PJ2 monitor the unique ID of the gaming arithmetic processing device 200 included in the gaming control device 41 of the gaming machine 10 as a whole, and evaluate the legitimacy of the gaming arithmetic processing device 200. Configure.
[0040]
・ Configuration of gaming machine
  FIG. 3 is a view showing the gaming machine 10, and the gaming machine 10 has a frame-shaped front frame 71, a metal frame (glass frame) 72 that supports glass, a game board 73 in which a game area is formed, and a front display. A panel 74 and an operation panel 75 provided below the front display panel 74 are provided. The front frame 71 is supported by an upper hinge 77 and a lower hinge 78 so that it can be opened and closed with respect to a wooden machine frame (not shown) on which the gaming machine 10 is installed, and the metal frame 72 is supported by the front frame 71 so as to be opened and closed. ing.
[0041]
  One end of the display panel 74 is supported by the front frame 71 so as to be openable and closable, and an upper plate 81 for receiving a prize ball is formed. In order to move the ball of the upper plate 81 to a ball storage plate (also called a tray) 82, An opening / closing lever 83 is provided for opening and closing the connecting passage. The operation panel 75 is provided with an ashtray 84 and the above-described sphere storage tray 82, and is provided with a sphere extraction lever 85 for extracting the sphere stored in the sphere storage tray 82 downward to the outside. Further, a ball launching operation knob 86 is provided on the right end side of the operation panel 75, and a big hit indicator 87 that is lit or blinks at the time of the big hit is provided above the front frame 71 of the gaming machine 10. .
[0042]
  The game board 73 is formed with a game area in which a substantially circular area on the front surface is surrounded by a guide rail 88, and a plurality of rows of identification information (so-called special symbols; hereinafter referred to as “special figures”) are arranged in the game area. Special display device 89 for variable display, special variable winning device 90 having a large winning opening, ordinary variable winning device 91 (so-called ordinary power) functioning as a special drawing starting port, and normal symbols provided in the normal variable winning device 91 (A so-called ordinary figure; hereinafter referred to as "ordinary figure"), an ordinary figure display device 92, a plurality of through-chucking-type ordinary figure starting gates 93, a plurality of general winning holes 94, and a plurality of hitting ball direction changing members 96 called windmills. Left and right side lamps 97, 98, an out hole 99, and the like are provided.
[0043]
  A special figure start switch 100 is provided in the winning flow path in the normal variation winning device 91, and a general figure start gate switch 101 is provided in the passage flow path in the general figure start gate 93. Further, a continuous switch 102 is provided in the continuous winning channel in the special winning opening of the special variable winning device 90, and a count switch 103 is provided in the general winning channel (see FIG. 4 for each of the above switches). .
[0044]
  In the upper part of the special figure display device 89, the above-described general winning opening 94 is arranged, and four special figure start memory displays 105 are provided. A start memory indicator 106 is provided. The general-purpose display device 92 is, for example, a display made of a liquid crystal or LED having a 7-segment display unit for displaying a single-digit number, and in this case, the normal symbol (common diagram) is a single-digit number. . The start memory displays 105 and 106 respectively display the number of start memories stored in a special figure or a common figure.
[0045]
  The special figure start switch 100 detects that the ball has won the normal fluctuation winning device 91, the normal figure start gate switch 101 detects that the ball has passed the normal figure start gate 93, and the count switch 103 has the special variable prize. All the balls that have entered the big winning opening of the device 90 are detected, and the continuation switch 102 detects the balls that have won the continuous winning (so-called V winning) among the balls that have entered the big winning opening.
[0046]
  The game area of the game board 73 is provided with a number of obstacle nails called top nails, armored nails, etc., which are omitted here to avoid congestion in the drawing. The game board 73 may be provided with other various decorative lamps, LEDs, and the like.
[0047]
  There are various types of game areas in the game board, including those belonging to the so-called “first type” and those belonging to “third type” equipped with a symbol display device. Applicable. In short, what is necessary is just to be provided with the arithmetic processing unit 200 for games which controls game control. Incidentally, the thing of this Embodiment is a type which belongs to "the 1st kind".
[0048]
・ Configuration of game control device
  FIG. 4 is a block diagram of the game control apparatus 41. The game control apparatus 41 divides the natural frequency of the game by a game arithmetic processing apparatus 200 composed of a microcomputer that performs an accessory control necessary for a pachinko game or the like. Then, an oscillator 111 that generates a predetermined clock signal and an interrupt signal generation circuit that generates a pulse signal (reset interrupt signal RST) with a period of 2 ms, for example, by further dividing the clock signal (in the figure, an RST generator) (Notation) 112, an input interface 113 for inputting various sensor signals, an output interface 114 for outputting various driving signals, a sound generator 115 for generating sound effects (mechanical sounds and / or sounds) necessary for the game, A sound effect signal from the sound generator 115 is amplified and a spy installed at a predetermined location of the gaming machine 10. An amplifier 117 that outputs to the car 116, and an external communication terminal 118 that exchanges signals between the game control device 41 and the information collection terminal device 31j (see the information collection terminal devices 31a and 31b in FIG. 1). Consists of.
[0049]
  Signals from the special figure start switch 100, the universal figure start gate switch 101, the continuation switch 102, the count switch 103, and the safe sensor 104 are input to the input interface 113. The safe sensor 104 detects a winning game ball. From the output interface 114, an external information terminal 119 for outputting game information to the information collecting terminal device 31, a display control device 120 for performing display control of the special figure display device 89, and a special prize winning device 90 which is a special variable winning device 90 are provided. Corresponds to the large winning opening solenoid 121 that opens and closes, the special figure start memory display 105, the general figure display device 92, the ordinary electric accessory solenoid 122 that drives the normal variable prize winning device 91, the general figure start memory display 106, and the winning ball Then, a control signal is output to the prize ball discharge circuit 123 for controlling the discharge of the prize ball, various decoration lamps, and LEDs (for example, ornaments including side lamps 97 and 98).
[0050]
-Configuration of the game processing unit 200
  FIG. 5 is a block diagram of the game arithmetic processing device 200. In FIG. 5, the game processing unit 200 is manufactured as a so-called amuse chip IC, and is divided into a game block 200A for performing game control and a management block 200B for managing information.
[0051]
  The game block 200A includes a CPU core 201 (corresponding to the arithmetic processing means described in the gist of the invention), a program ROM 202 (corresponding to the first storage means described in the gist of the invention), and a user work RAM 203 (second described in the gist of the invention). External bus interface 204, random number generation circuit 205, clock generator 206, reset / interrupt control circuit 207, address decoder 208, output control circuit 209, and CPU bus 210 (corresponding to the bus described in the gist of the invention) ).
[0052]
  The CPU core 201 is, for example, a Z80 core, and performs arithmetic processing for game control. The program ROM 202 stores the control program (game program), and stores validity confirmation information in a predetermined area. The legitimacy confirmation information is information in the case of performing a simple legitimacy check of the gaming arithmetic processing device 200. For example, a writing end code, initial setting information, a manufacturer code (for each gaming machine manufacturer) (Assigned unique code), authorization code, and unique ID, and a result value obtained by performing a predetermined operation (for example, an operation such as a checksum or CRC obtained by adding each information). The legitimacy confirmation information is written in a predetermined area when a third party organization or a game machine manufacturer writes a game program in the program ROM 202. The manufacturer of the gaming machineWriteIn some cases, only the result value is notified from a third party.
[0053]
  When performing a simple check of the gaming arithmetic processing device 200, when the gaming arithmetic processing device 200 is powered on, the arithmetic value calculated by the gaming arithmetic processing device 200 itself and a predetermined area of the program ROM 202 in which the gaming program is stored A configuration that enables a simple check of the arithmetic processing unit 200 for gaming by comparing and determining validity verification information (that is, a result value set in advance by a third party organization or the like) written in advance in It has become.
[0054]
  The user work RAM 203 is used as a work area (work area) when executing processing based on the game program in the game block 200A.
[0055]
  The external bus interface 204 includes a 16-bit address signal A0 to A15, an 8-bit data signal D0 to D7, a memory request signal MREQ, an input / output request signal IORQ, a memory write signal WR, a memory read signal RD, and a mode signal MODE. It performs interface processing with external signals. For example, if the data signals D0 to D7 are added while sequentially increasing the address signals A0 to A15 while the MODE signal is set to [H] level, the writing mode to the program ROM 202 is set, and the manufacturer of the gaming machine or A game program can be written by a third party. When the writing of the game program to the program ROM 202 is completed, a write end code is recorded in a predetermined area of the parameter memory 213 described later (for example, recorded by physically cutting a predetermined code or a predetermined bit). Thus, when a write end code is recorded in the parameter memory 213, the game program cannot be written to the program ROM 202.
[0056]
  The random number generation circuit 205 generates a random number related to whether or not to add a game value (for example, jackpot) in the game execution process (the random number is used for determining a jackpot or determining a symbol when stopped). A mathematical method (for example, a congruent method or an M-sequence method) for generating a uniform random number is used. In the present embodiment, information related to the model is used as a seed value when generating a random number.
[0057]
  The clock generator 206 supplies an operation clock signal to each block of the game arithmetic processing device 200 including the CPU core 201 based on the clock signal CLK from the oscillator 111.
[0058]
  The reset / interrupt control circuit 207 detects an interrupt request such as a reset interrupt signal RST from the interrupt signal generation circuit 112 and a signal from a circuit (not shown) that detects power-on to the game control device 41 to detect the CPU core. Let 201 know.
[0059]
  The address decoder 208 decodes the location of the built-in device and the built-in control / status register group by the memory mapped I / O method or the I / O mapped I / O method.
[0060]
  The output control circuit 209 controls the signal from the address decoder 208 and outputs an 8-bit chip select signal (CS0 to CS7) from the external terminal.
[0061]
  The CPU bus 210 includes a data bus, an address bus, and a control bus, and extends to the management block 200B.
[0062]
  Next, a management block 200B for managing information in the gaming arithmetic processing device 200 includes a boot ROM 212, a parameter memory 213, a bus monitor circuit 214 (corresponding to the detection means and acquisition means described in the gist of the invention), a security memory 216, It includes a management work RAM 217, a control circuit 218 (corresponding to the address generating means described in the gist of the invention), an external communication control circuit 219, a management bus 220, and a part of the CPU bus 210 on the game block 200A side.
[0063]
  The boot ROM 212 stores a boot program. When the gaming arithmetic processing unit 200 is powered on, first, the boot program starts up, performs a predetermined simple check, and if normal, a predetermined address of the gaming program (for convenience) To "start address"). The parameter memory 213 stores a write end code and initial setting information. The write end code is information indicating that the game program is written in the program ROM 202 as described above. The initial setting information is information for setting the usage (for input / output) of the chip select signals CS0 to CS7 when the game machine manufacturer writes the game program. For example, CS0, CS1, and This is information that CS2 is used for input and CS3, CS4, CS5, CS6, and CS7 are used for output.
[0064]
  The bus monitor circuit 214 monitors the state of the CPU bus 210. When the CPU bus 210 is not used by the CPU core 201, the program ROM 202 and the user work of the game block 200A are connected via the CPU bus 210 as necessary. The RAM 203 is accessed, and necessary data (game program, contents of the user work RAM 203, etc.) are taken into the management block 200B.
[0065]
  FIG. 6 is a detailed configuration diagram including the bus monitor circuit 214. In this figure, 214a is a data register (corresponding to the data holding means described in the gist of the invention) that latches data on the data bus 210a of the CPU bus 210 in response to the timing signal Sd and outputs it to the data bus 220a of the management bus 220. ) 214b latches the address of the address bus 220b of the management bus 220 in response to the timing signal Sa, and outputs it to the address bus 210b of the CPU bus 210 (corresponding to the address holding means described in the gist of the invention), A reader 214c generates the timing signals Sa and Sb based on the data request signal DATA_REQ output from the control circuit 218 of the management block 200B and the CPU refresh signal CPU_REF output from the CPU core 201 of the gaming block 200A. A timing generator.
[0066]
  Here, DATA_REQ is a signal output appropriately or periodically according to a management sequence executed by the control circuit 218, or a signal output in response to a management information request command from the external device PJ1. . CPU_REF is an appropriate signal indicating an unused state of the CPU bus 210 among various signals output from the CPU core 201. For example, in the case of the Z80 CPU, an “M1” (Machine Cycle One) signal can be used. This is because the M1 signal is often used as a timing signal for the refresh operation of the DRAM of the peripheral circuit, and the CPU bus is in a released state (a state not used by the CPU core 201) during the DRAM refresh period. Needless to say, the signal used for CPU_REF is not limited to the M1 signal. Even in the case of a CPU core of a type other than Z80, in short, an appropriate signal indicating an unused state of the CPU bus among various signals output from the CPU core may be used.
[0067]
  The security memory 216 (for example, composed of an EEPROM) has a unique ID, a manufacturer code (manufacturer's manufacturer code), and an authorization code (third party) used for identifying the gaming arithmetic processing device 200 and determining its legitimacy. Is an authorization code of a gaming machine authorized by a number assigned to a gaming machine that has passed inspection by the institution.
[0068]
  The management work RAM 217 is a storage area for holding information (such as the contents of the program RAM 202 and the contents of the user work RAM 203) of the game block 200A read through the bus monitor circuit 214.
[0069]
  The control circuit 218 executes a predetermined sequence to control the operation of the management block 200B. For example, the control circuit 218 detects the bus release period of the CPU core 201 via the bus monitor circuit 214 and detects the game block 200A during the synchronization. The contents of the program ROM 202 and the contents of the user work RAM 203 are read out and written into the management work RAM 217, or the contents of the management work RAM 217 are transferred to the outside in response to a management information request command from the external device PJ1. Or
[0070]
  The external communication control circuit 219 performs communication with the above-described PJ1 (see FIG. 2). For example, information stored in the arithmetic processing unit 200 based on a command from the outside (for example, state change information, game The program, the write end code, the unique ID, etc.) are transferred to the outside. Note that encryption processing may be performed on information transferred from the external communication control circuit 219 to the outside.
[0071]
  FIG. 7 is a flowchart showing an outline of the operation of the bus monitor circuit 214. In this figure, first, when DATA_REQ from the control circuit 218 is received, it is determined that it is an information acquisition request (read request) of the game block 200A (S1), and CPU_REF from the CPU core 201 is waited (S2). When CPU_REF is input, it is determined that it is a CPU refresh period, a timing signal Sa is generated for the address register 214b, and then a timing signal Sd is generated for the data register 214a.
[0072]
  Prior to sending DATA_REQ, the control circuit 218 generates an address of the read request target data and sets it in the address register 214b. The address of the read request target data is, for example, an arbitrary address α if the read request target data is data at an arbitrary address (for convenience α) in the game program, and the read request target data is stored in the user work RAM 203. If it is data of an arbitrary address (for convenience, β), it is the arbitrary address β.
[0073]
  Therefore, at the timing in response to CPU_REF, the address of the read request target data (for example, α or β) is transmitted from the address register 214b of the bus monitor circuit 214 to the address bus 210b of the CPU bus 210, and this transmitted data, for example, a game program The data of the arbitrary address α in the memory or the data of the arbitrary address β of the user work RAM 203 is latched in the data register 214a of the bus monitor circuit 214 via the data bus 210a of the CPU bus 210, and the data bus 220a of the management bus 220. Therefore, the control circuit 218 may capture the data and write it into the management work memory 217.
[0074]
  As described above, according to the present embodiment, the bus monitor circuit 214 detects the released state of the CPU bus 210, and when there is a read request, the CPU bus 210 in the released state is used to execute the program ROM 202 and the user work. Since the contents of the RAM 203 are read into the management block 200B, information necessary for management can be acquired in parallel with the game control without affecting the operation of the CPU core 201, that is, the operation of the game program. A special effect is obtained.
[0075]
  In the above embodiment, the target data of the read request is the contents of the program ROM 202 or the contents of the user work RAM 203, but is not limited to this. It goes without saying that all data that can be specified by an address, that is, all data existing on the address map of the CPU core 201 can be the target data.
[0076]
【The invention's effect】
  According to the present invention, the bus usage status of the CPU that executes the game program and controls the gaming machine is monitored, and the game program or the game program is being executed using the bus during the unused period of the bus. Since the data is acquired, the game program and the data being executed can be passed to the management block without intervening the CPU, thereby enabling real-time data acquisition during the game from the outside. .
  Furthermore, it becomes possible to write a game program to the program ROM from outside the game processing unit.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the overall structure of a hole.
FIG. 2 is a block diagram of PJ1.
FIG. 3 is a front view of the gaming machine.
FIG. 4 is a block diagram of a game control device.
FIG. 5 is a block diagram of a game processing unit.
FIG. 6 is a detailed configuration diagram of a main part including a bus monitor circuit.
FIG. 7 is an operation flowchart of the bus monitor circuit.
[Explanation of symbols]
  201 CPU core (arithmetic processing means)
  202 Program ROM (first storage means)
  203 User work RAM (second storage means)
  210 CPU bus (bus)
  214 Bus monitor circuit (detection means, acquisition means)
  218 Control circuit (address generating means)
  214a Data register (data holding means)
  214b Address register (address holding means)

Claims (3)

In a gaming machine equipped with a game control device configured by storing a board in a case together with a game processing unit for controlling a game state,
The gaming arithmetic processing device comprises:
It is divided into a game block that performs game control and a management block that performs information management, and is formed as an integrated circuit.
The game block is
A program ROM storing game programs;
A CPU that executes the game program and controls the gaming machine;
A user work RAM for providing a work area necessary for execution of the game program;
A CPU bus connecting the program ROM, the user work RAM, and the CPU;
An external bus interface for interfacing with the outside of the gaming processing unit using an address signal and a data signal;
Comprising
The management block is
At power-on of the gaming processor, performs predetermined Fast Check, and boot ROM that stores a boot program the simple check to pass the processing to the predetermined address of the game program if it is normal,
Monitors the state of the CPU bus, and accesses the program ROM and the user work RAM via the CPU bus when the CPU bus is not used by the CPU, and takes in necessary data to the management block side. A bus monitor circuit;
Security memory where unique ID and manufacturer code are written,
A management work RAM for holding the contents of the program ROM read through the bus monitor circuit and the contents of the user work RAM;
An external communication control circuit that transfers the information on the game block side stored in the management work RAM to the outside after performing encryption processing based on an instruction from the outside;
Controls the operation on the management block side, detects the release period of the CPU bus via the bus monitor circuit, reads the contents of the program ROM and the contents of the user work RAM, and writes them to the management work RAM And a control circuit for transferring the contents of the management work RAM to the outside in response to a command from the outside,
A management bus for connecting the bus monitor circuit, security memory, management work RAM, external communication control circuit, and control circuit;
Have
In addition, a part of the CPU bus on the game block side is included, and the boot ROM and a bus monitor circuit are connected to the CPU bus,
During the release period of the CPU bus, the contents of the program ROM and user work RAM are read and written to the management work RAM, and the written contents are transferred to the outside in response to an external command .
The gaming arithmetic processing unit, while generating the write mode of the program ROM, sequentially increments the address signal to the program ROM from the outside of the gaming arithmetic processing unit via the data signal. A gaming machine characterized by writing a gaming program . The gaming arithmetic processing device includes a recording area for storing a writing end code indicating the end of writing of the game program to the program ROM, and the recording area is obtained by physically cutting a predetermined bit. The gaming machine according to claim 1, wherein the write end code is recorded. 3. The game arithmetic processing unit according to claim 1, wherein a write mode of the program ROM is generated when a MODE signal input from the outside of the gaming arithmetic processing unit becomes H level. Gaming machine.

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