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JP4304498B2 - Semiconductor device and semiconductor module - Google Patents
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JP4304498B2 - Semiconductor device and semiconductor module - Google Patents

Semiconductor device and semiconductor module Download PDF

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JP4304498B2
JP4304498B2 JP2004296252A JP2004296252A JP4304498B2 JP 4304498 B2 JP4304498 B2 JP 4304498B2 JP 2004296252 A JP2004296252 A JP 2004296252A JP 2004296252 A JP2004296252 A JP 2004296252A JP 4304498 B2 JP4304498 B2 JP 4304498B2
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semiconductor chip
substrate
semiconductor
single crystal
isolation
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JP2006108556A (en
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敏彦 小杉
雅美 徳光
忠夫 石橋
和宏 丸山
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NTT Electronics Corp
NTT Inc
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Nippon Telegraph and Telephone Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00Waveguides; Transmission lines of the waveguide type
    • H01P3/003Coplanar lines
    • H01P3/006Conductor backed coplanar waveguides

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Description

本発明は、アイソレーション構造を有する半導体装置及び半導体モジュールに関する。特に、ミリ波帯で動作する高周波半導体集積回路チップにおける高周波信号のアイソレーション構造に関する。   The present invention relates to a semiconductor device and a semiconductor module having an isolation structure. In particular, the present invention relates to a high-frequency signal isolation structure in a high-frequency semiconductor integrated circuit chip operating in the millimeter wave band.

半導体チップにおいて、チップ上のある回路から半導体チップ内部に漏洩した高周波信号が、半導体チップ内部を長距離に渡り、あまり減衰せずに伝播し、同じチップ上の他の回路へ干渉し、半導体チップ本来の機能が損なわれるという問題がある。前記問題は、30GHz以上のミリ波帯で動作する半導体チップにおいて、特に顕著となる。   In a semiconductor chip, a high-frequency signal leaked from a certain circuit on the chip to the inside of the semiconductor chip propagates over the long distance without much attenuation, and interferes with other circuits on the same chip. There is a problem that the original function is impaired. The above problem is particularly remarkable in a semiconductor chip that operates in a millimeter wave band of 30 GHz or more.

また、ビア形成及びウェハ裏面への導体層形成を行い、半導体チップ内部を伝播する高周波信号を遮断する対策が行われていない半導体チップにおいても、前記問題は顕著となる。ここで、ビア形成とは、半導体チップの表裏を貫通する穴をあけ、前記穴の中に導電性を有する材質を埋め込む、又は、前記穴の内壁に導電性の膜を形成することをいう。   In addition, the above problem becomes significant even in a semiconductor chip in which a via is formed and a conductor layer is formed on the back surface of the wafer, and a countermeasure for blocking a high-frequency signal propagating inside the semiconductor chip is not taken. Here, the via formation means that a hole penetrating the front and back surfaces of the semiconductor chip is formed, and a conductive material is embedded in the hole, or a conductive film is formed on the inner wall of the hole.

30GHzより、十分低い周波数においても、前記問題に類似する干渉問題があるが、その原因は、ミリ波帯での問題とは異なり、容量性結合によるものが主である。従って、ミリ波帯において特に効果があるアイソレーション技術、即ち、半導体チップを通しての高周波信号の干渉を防ぐ技術が必要とされている。   Even at frequencies sufficiently lower than 30 GHz, there is an interference problem similar to the above problem, but the cause is mainly due to capacitive coupling, unlike the problem in the millimeter wave band. Therefore, there is a need for an isolation technique that is particularly effective in the millimeter wave band, that is, a technique for preventing high-frequency signal interference through a semiconductor chip.

ここで、ミリ波帯における半導体チップを通した干渉について、詳しく説明する。半導体チップは一般的には誘電体であり、半導体チップに使用される材料は、比誘電率として、Si:11.7、GaAs:12.0、InP:12.1等、比較的大きな値を持つものが多い。一方、半導体チップを誘電体でできた、1本の方形導波管とみなせば、導波管内部を伝播する最も低い遮断周波数を有するTE10モード(基本モード)の遮断周波数は、
=c/2a ・・・・・・・(1)
とあらわされる。ここで、c=(εμ)−0.5であり、εは半導体の誘電率、μは半導体の透磁率、aは方形導波管の長い方の辺の長さである。fをあらわす式に典型的な半導体チップの値を代入すると、およそ20GHz〜40GHzが遮断周波数となる。
Here, interference through the semiconductor chip in the millimeter wave band will be described in detail. A semiconductor chip is generally a dielectric, and the material used for the semiconductor chip has a relative dielectric constant such as Si: 11.7, GaAs: 12.0, InP: 12.1, and the like. There are many things to have. On the other hand, if the semiconductor chip is regarded as one rectangular waveguide made of a dielectric, the cutoff frequency of the TE 10 mode (fundamental mode) having the lowest cutoff frequency propagating inside the waveguide is:
f c = c / 2a (1)
It is expressed. Here, c = (εμ) −0.5 , ε is the dielectric constant of the semiconductor, μ is the magnetic permeability of the semiconductor, and a is the length of the longer side of the rectangular waveguide. Substituting the value of a typical semiconductor chip on a formula that represents the f c, approximately 20GHz~40GHz becomes cutoff frequency.

次に、30GHz以上で動作する半導体チップには、GaAsやInP等の、化合物半導体が多く用いられる。これら半導体チップでは、半絶縁性基板が用いられることから、高周波信号の半導体チップ内部での損失を表すtanδは、通常0.01より十分小さい。つまり、化合物半導体により製造された半導体チップにおいては、数十GHz以上の高周波信号は、基板内部を容易に伝播可能であり、かつ、損失が少ないため長距離を減衰することなく伝わる。   Next, compound semiconductors such as GaAs and InP are often used for semiconductor chips operating at 30 GHz or higher. Since these semiconductor chips use a semi-insulating substrate, tan δ representing the loss of high-frequency signals inside the semiconductor chip is usually sufficiently smaller than 0.01. That is, in a semiconductor chip manufactured by a compound semiconductor, a high frequency signal of several tens of GHz or more can be easily propagated through the substrate and is transmitted without attenuating a long distance because of a small loss.

半導体チップ内部を高周波信号が伝播可能であるため、半導体チップ上の回路から、高周波信号が半導体内部に漏洩した場合に、干渉問題が顕在化する。通常、半導体集積回路で用いられるコプレーナ線路(CPW)を伝播する高周波信号は、擬似TEMモードで伝播しており、半導体チップ内部を伝播可能なTE10モードを直接励振する効率は低い。しかし、コプレーナ線路の曲がる部分においては、TEMモードに乱れが生じるため、半導体チップ内部のTE10モードを励振することが可能となる。また、TEMモードの乱れは、コプレーナ線路の幅が広い程、顕著となる。実際の回路においては、伝送損失を抑制するために、幅の広いコプレーナ線路が随所に用いられており、かつ、コプレーナ線路は、曲がる部分を非常に多く有している。更に、半導体チップを実装した場合、高周波信号が伝送される外部回路と半導体チップ間の接続点において、組立て時の不完全さ、構造そのものが持つ線路の対象性の乱れ、または、特性インピーダンスの乱れ等により不要な電磁波の放射が起こり易くなる。複数の高周波信号用のポートを持つ半導体チップでは、ポート間の高いアイソレーションが必要となるため、しばしば半導体チップ内部の伝播によるポート間干渉の問題が生じる。 Since a high-frequency signal can propagate inside the semiconductor chip, an interference problem becomes apparent when a high-frequency signal leaks from the circuit on the semiconductor chip into the semiconductor. Usually, a high-frequency signal propagating through a coplanar line (CPW) used in a semiconductor integrated circuit propagates in a pseudo TEM mode, and the efficiency of directly exciting the TE 10 mode that can propagate through the semiconductor chip is low. However, since the TEM mode is disturbed in the bent portion of the coplanar line, the TE 10 mode inside the semiconductor chip can be excited. Further, the TEM mode disturbance becomes more prominent as the width of the coplanar line becomes wider. In an actual circuit, in order to suppress transmission loss, a wide coplanar line is used everywhere, and the coplanar line has a very large bent portion. In addition, when a semiconductor chip is mounted, imperfections during assembly, line subjectivity of the structure itself, or characteristic impedance disturbance at the connection point between the external circuit and the semiconductor chip that transmits high-frequency signals For example, unnecessary electromagnetic wave radiation is likely to occur. In a semiconductor chip having a plurality of ports for high-frequency signals, high isolation between the ports is required, so that there is often a problem of inter-port interference due to propagation inside the semiconductor chip.

上記干渉問題を防ぐための、従来技術として電波吸収体を用いる方法があり、各種の電波吸収体が市販されている(例えば、非特許文献1参照)。前記方法は、目的とする周波数帯の電磁波を吸収する電波吸収体を、半導体チップの表面、裏面又は側面に接近する形で配置し、半導体チップから漏れてくる電磁波を吸収し、ジュール熱に変換することで干渉を抑制するものである。   In order to prevent the interference problem, there is a method using a radio wave absorber as a prior art, and various radio wave absorbers are commercially available (for example, see Non-Patent Document 1). In the above method, a radio wave absorber that absorbs electromagnetic waves in a target frequency band is disposed so as to be close to the front surface, back surface, or side surface of the semiconductor chip, and electromagnetic waves leaking from the semiconductor chip are absorbed and converted to Joule heat. By doing so, interference is suppressed.

“ソリッド型電波シールド吸収体 μtect PP3100 Technical Information“、京セラ株式会社“Solid-type radio wave shield absorber μect PP3100 Technical Information”, Kyocera Corporation

電波吸収体を用いる方法において、漏洩した電磁波を効率的に吸収するためには、可能な限り半導体チップの近くに電波吸収体を配置することが必要である。しかし、回路が形成されている半導体チップの表面に接するように配置すると回路特性が劣化するため、あまり接近させることは困難である。尚、前記配置は、半導体チップのアイソレーションを改善するのではなく、半導体チップが実装されているモジュール内部の空間(キャビティー)による電磁波の共振を防ぐ目的で用いられることが多い。   In the method using the radio wave absorber, in order to efficiently absorb the leaked electromagnetic wave, it is necessary to dispose the radio wave absorber as close to the semiconductor chip as possible. However, if the circuit is arranged so as to be in contact with the surface of the semiconductor chip on which the circuit is formed, the circuit characteristics deteriorate, so that it is difficult to make it approach too much. The arrangement is often used not for improving the isolation of the semiconductor chip but for the purpose of preventing resonance of electromagnetic waves due to the space (cavity) inside the module in which the semiconductor chip is mounted.

また、半導体チップの裏面に電波吸収体を接するように配置する場合は、半導体チップと電波吸収体の接触面積を十分大きくとることができ、電磁波を効率的に吸収することが可能であるが。電波吸収体の熱抵抗により半導体チップの放熱特性が劣化する問題が生じる。市販されている電波吸収体の材質は正確には明らかにされていないが、ゴム状若しくは樹脂状の材質に、必要な添加物を加えて電波吸収作用を持たせたもの、または、セラミックスに、必要な添加物を加え電波吸収作用を持たせたもの等があり、いずれの材質も熱抵抗が高く、半導体チップの放熱効果が劣化する。このため、パワーアンプ等の低熱抵抗を必要とする半導体チップには、電波吸収体による方法を用いることは困難である。また、前記材質による電波吸収体は、厚みや平坦さを制御することが困難であり、半導体チップの裏面に電波吸収体を接するように配置した場合は、半導体チップの正確な位置合わせが困難となり、ワイヤーボンディング等の工程に問題が生じやすくなる。   In addition, when the radio wave absorber is disposed in contact with the back surface of the semiconductor chip, the contact area between the semiconductor chip and the radio wave absorber can be sufficiently large, and electromagnetic waves can be efficiently absorbed. There is a problem that the heat dissipation characteristics of the semiconductor chip deteriorate due to the thermal resistance of the radio wave absorber. Although the material of the commercially available radio wave absorber has not been clarified accurately, a rubber-like or resin-like material added with a necessary additive to have a radio wave absorption function, or ceramics, There are materials that have the effect of absorbing radio waves by adding necessary additives, and all materials have high thermal resistance, and the heat dissipation effect of the semiconductor chip deteriorates. For this reason, it is difficult to use a method using a radio wave absorber for a semiconductor chip that requires low thermal resistance, such as a power amplifier. In addition, it is difficult to control the thickness and flatness of the radio wave absorber made of the above material, and when the radio wave absorber is disposed in contact with the back surface of the semiconductor chip, accurate alignment of the semiconductor chip becomes difficult. Problems are likely to occur in processes such as wire bonding.

更に、半導体チップの側面に電波吸収体を接するように配置した場合は、接触面積が小さいため、良好なアイソレーションが得られない。本方法は、補助的手段として、他のアイソレーション技術との組合せで用いられる。   Furthermore, when the radio wave absorber is disposed in contact with the side surface of the semiconductor chip, good contact cannot be obtained because the contact area is small. The method is used as a supplementary means in combination with other isolation techniques.

電波吸収体を用いる方法の他の問題点は、使用条件に応じた電波吸収体の最適化が困難なことである。与えられた外部条件により、電波吸収体が電磁波を最も効率的に吸収する誘電率、透磁率、抵抗率、誘電損失等が存在するが、実際に入手可能な電波吸収体の種類は限られている。ミリ波帯において特に効果があり、半導体チップのアイソレーションを改善する目的に最適化した電波吸収体の入手は特に困難であり、また、前記電波吸収体のコストは高く、高周波モジュールの製造コストを増大させる原因となっている。   Another problem of the method using the radio wave absorber is that it is difficult to optimize the radio wave absorber according to the use conditions. Depending on the given external conditions, there are dielectric constant, magnetic permeability, resistivity, dielectric loss, etc. that the wave absorber absorbs electromagnetic waves most efficiently, but the types of wave absorbers that are actually available are limited Yes. It is particularly effective in the millimeter wave band, and it is particularly difficult to obtain a radio wave absorber optimized for the purpose of improving the isolation of the semiconductor chip. Further, the cost of the radio wave absorber is high, and the manufacturing cost of the high frequency module is reduced. This is the cause of the increase.

従って、本発明は、半導体チップに対し、放熱特性の劣化を招くことなく、半導体チップ上の回路及び/又は線路間での干渉を強く抑制する、即ち、高いアイソレーションを可能とする構造を有する半導体装置及び半導体モジュールを提供することを目的とする。   Therefore, the present invention has a structure that strongly suppresses interference between circuits and / or lines on a semiconductor chip, that is, enables high isolation without causing deterioration of heat dissipation characteristics of the semiconductor chip. An object is to provide a semiconductor device and a semiconductor module.

更に、高いアイソレーションを可能としつつ、使用条件に応じた調整が容易であり、また、低コストで製造可能な構造を有する半導体装置及び半導体モジュールを提供することも目的とする。   It is another object of the present invention to provide a semiconductor device and a semiconductor module that have a structure that can be manufactured at a low cost and can be easily adjusted in accordance with use conditions while enabling high isolation.

本発明における半導体装置及び半導体モジュールによれば、
半導体チップと、抵抗率が0.2Ωcm以上、かつ、10Ωcm以下である抵抗体基板とを有し、前記半導体チップには、前記半導体チップ内部を伝播可能である電磁波の伝播モードが存在し、前記抵抗体基板は、単結晶Si基板、GaAs基板、InP基板のいずれかであり、前記半導体チップの回路が形成されていない面に接して配置される構造を有することを特徴とする。
According to the semiconductor device and the semiconductor module of the present invention,
A semiconductor chip and a resistor substrate having a resistivity of 0.2 Ωcm or more and 10 Ωcm or less, the semiconductor chip has an electromagnetic wave propagation mode capable of propagating inside the semiconductor chip, and The resistor substrate is any one of a single crystal Si substrate, a GaAs substrate, and an InP substrate , and has a structure in which the resistor substrate is disposed in contact with a surface where the circuit of the semiconductor chip is not formed.

また、本発明の他の実施形態によれば、
前記半導体チップ内部を伝播可能である電磁波は、30GHz以上であることも好ましい。
Also, according to another embodiment of the present invention,
The electromagnetic wave that can propagate through the semiconductor chip is preferably 30 GHz or more.

更に、本発明の他の実施形態によれば、
前記半導体チップは、コプレーナ線路を有することも好ましい。
Furthermore, according to another embodiment of the present invention,
The semiconductor chip preferably has a coplanar line.

本発明による構造を用いることにより、良好な放熱特性、高周波特性、熱的安定性を維持したまま、半導体チップの高いアイソレーションが可能となる。また、使用条件に応じて容易に調整可能であり、かつ、実装も容易であるため、本発明によるアイソレーション構造を用いた半導体装置又はモジュールの性能の向上と低コスト化が達成できる。   By using the structure according to the present invention, it is possible to achieve high isolation of the semiconductor chip while maintaining good heat dissipation characteristics, high frequency characteristics, and thermal stability. In addition, since it can be easily adjusted according to use conditions and can be easily mounted, the performance and cost reduction of the semiconductor device or module using the isolation structure according to the present invention can be achieved.

本発明を実施するための最良の実施形態について、以下では図面を用いて詳細に説明する。   The best mode for carrying out the present invention will be described in detail below with reference to the drawings.

図1は、本発明による半導体装置及び半導体モジュールで用いるアイソレーション構造の実施形態を示す図であり、(a)は、上面図、(b)は、側面図である。図1によると、半導体チップ1の裏面に、単結晶Si基板2が接して配置されており、単結晶Si基板2の、半導体チップ1と接着されている面とは逆の面に、モジュール筐体3が接着されている。ここで、半導体チップの回路が形成されている面を表面、回路が形成されている面とは反対の面を裏面と呼ぶものとする。   1A and 1B are diagrams showing an embodiment of an isolation structure used in a semiconductor device and a semiconductor module according to the present invention, wherein FIG. 1A is a top view and FIG. 1B is a side view. According to FIG. 1, a single crystal Si substrate 2 is disposed in contact with the back surface of the semiconductor chip 1, and the module housing is disposed on the surface of the single crystal Si substrate 2 opposite to the surface bonded to the semiconductor chip 1. The body 3 is bonded. Here, the surface on which the circuit of the semiconductor chip is formed is referred to as the front surface, and the surface opposite to the surface on which the circuit is formed is referred to as the back surface.

半導体チップ1は、コプレーナ線路を配線手段として含み、また、高周波電磁波が、その内部を伝播することが可能である。既に述べたように、半導体チップ1を誘電体でできた1本の方形導波管とみなせば、式(1)で表される遮断周波数以上の電磁波が、半導体チップ1の内部を伝播するモードが存在する。   The semiconductor chip 1 includes a coplanar line as a wiring means, and high-frequency electromagnetic waves can propagate through the inside. As already described, if the semiconductor chip 1 is regarded as a single rectangular waveguide made of a dielectric, an electromagnetic wave having a cutoff frequency or higher expressed by the equation (1) propagates through the semiconductor chip 1. Exists.

図2は、半導体チップ1上に形成される回路の例を示す図である。増幅回路6にコプレーナ線路7が接続されている。図2の例では、半導体チップ1は、外部との接続点8を2箇所有している。   FIG. 2 is a diagram illustrating an example of a circuit formed on the semiconductor chip 1. A coplanar line 7 is connected to the amplifier circuit 6. In the example of FIG. 2, the semiconductor chip 1 has two connection points 8 with the outside.

本発明によるアイソレーションのための構造は、ゴム状、樹脂状又はセラッミクス状の電波吸収体に代えて、図1に示すように、単結晶Si基板2を用いることを特徴としている。   The structure for isolation according to the present invention is characterized by using a single crystal Si substrate 2 as shown in FIG. 1 instead of a rubber-like, resin-like or ceramic-like wave absorber.

Siの熱伝導率は、148W/m℃であり、従来の電波吸収体の熱伝導率0.1〜40W/m℃と比較し、極めて高い値を持つ。従って、半導体チップ1の放熱効率をほとんど劣化させず、発熱量の大きいパワーアンプ等へ適用するのに相応しい特性をもつ。また、従来の電波吸収体の比誘電率は様々な値を持つが、単結晶Si基板2の比誘電率は11.7であり、この値は、GaAsの比誘電率12.0、InPの比誘電率12.1とほぼ同じであり、半導体チップ1がSi基板、GaAs基板、InP基板により作成されている場合には、半導体チップ上に形成されたコプレーナ線路の特性インピーダンスを変化させること無く、アイソレーションが可能となる。   The thermal conductivity of Si is 148 W / m ° C., which is an extremely high value compared to the thermal conductivity 0.1 to 40 W / m ° C. of conventional wave absorbers. Therefore, the heat dissipation efficiency of the semiconductor chip 1 is hardly deteriorated, and it has characteristics suitable for application to a power amplifier having a large heat generation amount. Further, the relative permittivity of the conventional wave absorber has various values, but the relative permittivity of the single-crystal Si substrate 2 is 11.7, which is the relative permittivity of GaAs of 12.0 and InP. When the semiconductor chip 1 is made of a Si substrate, a GaAs substrate, or an InP substrate, the relative dielectric constant is approximately the same as 12.1, without changing the characteristic impedance of the coplanar line formed on the semiconductor chip. Isolation is possible.

更に、単結晶Siの熱膨張率は、2.6×10/Kであり、GaAsやInPの熱膨張率4〜6×10/Kに近い値であり、モジュール筐体3の熱履歴による半導体チップの剥がれや、ひび割れが生じにくくなるという利点もある。また、従来の電波吸収体の多くは、熱的に不安定な材質であるのに対して、単結晶Siは、500℃以上の高温でも安定な材質であり、熱履歴により生じる電波吸収体の特性変化や、電波吸収体からのアウトガスによる半導体チップの故障も問題とはならない。 Furthermore, the thermal expansion coefficient of the single crystal Si is 2.6 × 10 6 / K, which is close to the thermal expansion coefficient of 4 to 6 × 10 6 / K of GaAs or InP. There is also an advantage that the semiconductor chip is not easily peeled off or cracked. In addition, many of the conventional wave absorbers are thermally unstable materials, whereas single crystal Si is a material that is stable even at a high temperature of 500 ° C. or higher. A change in characteristics and failure of the semiconductor chip due to outgas from the radio wave absorber are not a problem.

更に、単結晶Si基板2は、Siデバイス製造用のウェハをそのまま用いることができる。よって、厚さ、平坦性、電気特性等が均一な単結晶Si基板2を容易に、かつ、安価に得ることができる。よって、従来の電波吸収体を用いた場合に生じ得る、半導体チップの正確な位置あわせが難しいといった問題も解消される。   Further, the single crystal Si substrate 2 can be a wafer for manufacturing Si devices. Therefore, the single crystal Si substrate 2 having uniform thickness, flatness, electrical characteristics, etc. can be obtained easily and inexpensively. Therefore, the problem that it is difficult to accurately align the semiconductor chip, which may occur when a conventional radio wave absorber is used, is also solved.

次に、単結晶Si基板の抵抗率と、アイソレーション効果との関係について述べる。ドープされていない単結晶Si基板2は、高周波損失が少なく、また、高濃度にドープされた単結晶Si基板2は、導体基板と類似した作用をもつようになるため、ドープ量、即ち、単結晶Si基板の抵抗率によりアイソレーション効果も変動する。   Next, the relationship between the resistivity of the single crystal Si substrate and the isolation effect will be described. The undoped single crystal Si substrate 2 has a low high-frequency loss, and the highly doped single crystal Si substrate 2 has a function similar to that of a conductor substrate. The isolation effect also varies depending on the resistivity of the crystalline Si substrate.

図3は、単結晶Si基板の抵抗率と、アイソレーション効果の関係を示す図である。図3の減衰量は、図1の半導体チップの相対する側面4−5間に、30GHz以上の電磁波を伝播させた場合の、電磁波の減衰量を示す。図3において、電磁波の波長をλ(=c/f)とし、半導体チップ1及び単結晶Si基板2の各辺の長さL1、L2,L3,及びL4は、総て2λとし、半導体チップ1の厚さdはλ/10、単結晶Si基板2の厚さeは0.6λとした。従って、以下の説明は、30GHz以上においては、周波数に依存せずに成り立つ。尚、具体例として、100GHzにおいて、半導体の誘電率εが12の場合には、λは約1.2mmであり、半導体チップ1及び単結晶Si基板2の各辺の長さは約2.4mmであり、半導体チップ1の厚さdは約0.12mmである。   FIG. 3 is a diagram showing the relationship between the resistivity of the single crystal Si substrate and the isolation effect. The attenuation amount in FIG. 3 indicates the attenuation amount of the electromagnetic wave when the electromagnetic wave of 30 GHz or more is propagated between the opposing side surfaces 4-5 of the semiconductor chip in FIG. In FIG. 3, the wavelength of the electromagnetic wave is λ (= c / f), the lengths L1, L2, L3, and L4 of each side of the semiconductor chip 1 and the single crystal Si substrate 2 are all 2λ, and the semiconductor chip 1 The thickness d of λ / 10 was λ / 10, and the thickness e of the single crystal Si substrate 2 was 0.6λ. Therefore, the following description is valid without depending on the frequency at 30 GHz or more. As a specific example, at 100 GHz, when the dielectric constant ε of the semiconductor is 12, λ is about 1.2 mm, and the length of each side of the semiconductor chip 1 and the single crystal Si substrate 2 is about 2.4 mm. The thickness d of the semiconductor chip 1 is about 0.12 mm.

図3より、抵抗率1Ωcm付近で非常に大きな減衰量を示すことがわかる。また、好ましい減衰量である20dBを閾値とした場合には、抵抗率が0.2Ωcm〜10Ωcmの間にある単結晶Si基板2を使用可能である。従来の電波吸収体と異なり、単結晶Si基板2では、Si基板のドープ量を変えることで、容易にアイソレーション効果の最適化を行うことができる。また、半導体チップ1に含まれるコプレーナ線路から、高周波信号が半導体チップ内部へ漏洩しても、半導体チップ内部を伝播する過程で減衰を受け、同じ半導体チップ上にある他の回路への干渉が効果的に抑制される。   From FIG. 3, it can be seen that a very large attenuation is exhibited around a resistivity of 1 Ωcm. In addition, when a preferable attenuation of 20 dB is used as a threshold value, a single crystal Si substrate 2 having a resistivity between 0.2 Ωcm and 10 Ωcm can be used. Unlike the conventional wave absorber, in the single crystal Si substrate 2, the isolation effect can be easily optimized by changing the doping amount of the Si substrate. Even if a high-frequency signal leaks from the coplanar line included in the semiconductor chip 1 to the inside of the semiconductor chip, it is attenuated in the process of propagating inside the semiconductor chip, and interference with other circuits on the same semiconductor chip is effective. Is suppressed.

図4は、単結晶Si基板の厚さと、アイソレーション効果の関係を示す図である。図1の構造における単結晶Si基板2の厚さeと、半導体チップの相対する側面4−5間での30GHz以上の電磁波の減衰量との関係を示したものである。図4において、単結晶Si基板2の抵抗率は、1Ωcmとし、その他の条件は、図3と同じである。半導体チップ1から単結晶Si基板2へ放射された電磁波が、総て単結晶Si基板2に吸収され、反射等により戻ってこない場合に、アイソレーション効果が最良であることを考慮すると、単結晶Si基板2は、可能な限り厚いほうが好ましい。抵抗率1Ωcmの最適条件において、減衰量20dB以上を確保するためには、厚さeは、0,3λ以上必要である。また、厚さeが、λ以上では、減衰量の変化が少なくなっていることを考慮すると、厚さeの好ましい範囲としては、0.3λ〜λが考えられる。   FIG. 4 is a diagram showing the relationship between the thickness of the single crystal Si substrate and the isolation effect. 1 shows the relationship between the thickness e of the single-crystal Si substrate 2 in the structure of FIG. 1 and the attenuation of electromagnetic waves of 30 GHz or more between the opposing side surfaces 4-5 of the semiconductor chip. In FIG. 4, the resistivity of the single crystal Si substrate 2 is 1 Ωcm, and other conditions are the same as in FIG. Considering that the isolation effect is best when all the electromagnetic waves radiated from the semiconductor chip 1 to the single crystal Si substrate 2 are absorbed by the single crystal Si substrate 2 and do not return by reflection or the like, the single crystal The Si substrate 2 is preferably as thick as possible. In order to ensure an attenuation of 20 dB or more under the optimum condition of a resistivity of 1 Ωcm, the thickness e needs to be 0.33λ or more. Further, considering that the change in attenuation is small when the thickness e is λ or more, a preferable range of the thickness e is 0.3λ to λ.

図5は、単結晶Si基板の辺の長さと、アイソレーション効果の関係を示す図である。図1の構造における単結晶Si基板2の各辺L3及びL4を同じとし、各辺の長さと、半導体チップの相対する側面4−5間での30GHz以上の電磁波の減衰量との関係を示したものである。図5において、単結晶Si基板2の抵抗率は1Ωcmとし、その他の条件は図3と同じである。図5より、長さL3、L4は、半導体チップの長さL1、L2以上であれば良好なアイソレーション特性が得られる。   FIG. 5 is a diagram showing the relationship between the side length of the single crystal Si substrate and the isolation effect. 1 shows the relationship between the length of each side and the attenuation of electromagnetic waves of 30 GHz or more between the opposing side surfaces 4-5 of the semiconductor chip with the sides L3 and L4 of the single crystal Si substrate 2 being the same. It is a thing. In FIG. 5, the resistivity of the single crystal Si substrate 2 is 1 Ωcm, and other conditions are the same as those in FIG. As shown in FIG. 5, when the lengths L3 and L4 are longer than the lengths L1 and L2 of the semiconductor chip, good isolation characteristics can be obtained.

尚、単結晶Si基板を用いる例で説明を行ってきたが、上記単結晶Siの代わりに、GaAs、InP等に不純物をドープして、Siと同程度の抵抗率を持たせた抵抗体基板を用いることで、Siほどの低熱抵抗や、低コスト化は期待できないにしても、アイソレーション効果を得ることは可能である。   Although the example using a single crystal Si substrate has been described, a resistor substrate in which impurities are doped into GaAs, InP, etc., instead of the single crystal Si, to have the same resistivity as Si. By using this, it is possible to obtain an isolation effect even though it cannot be expected to have a thermal resistance as low as Si and cost reduction.

本発明による半導体装置及び半導体モジュールが有するアイソレーション構造の実施形態を示す図である。It is a figure which shows embodiment of the isolation structure which the semiconductor device and semiconductor module by this invention have. 半導体チップ上に形成される回路の例を示す図である。It is a figure which shows the example of the circuit formed on a semiconductor chip. 単結晶Si基板の抵抗率と、アイソレーション効果の関係を示す図である。It is a figure which shows the relationship between the resistivity of a single crystal Si substrate, and the isolation effect. 単結晶Si基板の厚さと、アイソレーション効果の関係を示す図である。It is a figure which shows the relationship between the thickness of a single crystal Si substrate, and the isolation effect. 単結晶Si基板の辺の長さと、アイソレーション効果の関係を示す図である。It is a figure which shows the relationship between the length of the side of a single crystal Si substrate, and the isolation effect.

符号の説明Explanation of symbols

1 半導体チップ
2 単結晶Si基板
3 モジュール筐体
4、5 半導体チップの側面
6 増幅回路
7 コプレーナ線路
8 接続点
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Single crystal Si substrate 3 Module housing | casing 4, 5 Side surface of semiconductor chip 6 Amplifying circuit 7 Coplanar line 8 Connection

Claims (4)

半導体チップと、抵抗率が0.2Ωcm以上、かつ、10Ωcm以下である抵抗体基板とを有し、
前記半導体チップには、前記半導体チップ内部を伝播可能である電磁波の伝播モードが存在し、
前記抵抗体基板は、単結晶Si基板、GaAs基板、InP基板のいずれかであり、前記半導体チップの回路が形成されていない面に接して配置される構造を有することを特徴とする半導体装置。
Having a semiconductor chip and a resistor substrate having a resistivity of 0.2 Ωcm or more and 10 Ωcm or less,
The semiconductor chip has a propagation mode of electromagnetic waves that can propagate inside the semiconductor chip,
2. The semiconductor device according to claim 1, wherein the resistor substrate is any one of a single crystal Si substrate, a GaAs substrate, and an InP substrate , and has a structure disposed in contact with a surface of the semiconductor chip where a circuit is not formed.
前記半導体チップ内部を伝播可能である電磁波は、30GHz以上であることを特徴とする請求項1に記載の半導体装置。 The semiconductor device according to claim 1, wherein an electromagnetic wave capable of propagating through the semiconductor chip is 30 GHz or more. 前記半導体チップは、コプレーナ線路を有することを特徴とする請求項1又は2に記載の半導体装置。 The semiconductor chip is the semiconductor device according to claim 1 or 2, characterized in that it has a coplanar line. 半導体チップと、抵抗率が0.2Ωcm以上、かつ、10Ωcm以下である抵抗体基板とを有し、
前記半導体チップには、前記半導体チップ内部を伝播可能である電磁波の伝播モードが存在し、
前記抵抗体基板は、単結晶Si基板、GaAs基板、InP基板のいずれかであり、前記半導体チップの回路が形成されていない面に接して配置される構造を有することを特徴とする半導体モジュール。
Having a semiconductor chip and a resistor substrate having a resistivity of 0.2 Ωcm or more and 10 Ωcm or less,
The semiconductor chip has a propagation mode of electromagnetic waves that can propagate inside the semiconductor chip,
2. The semiconductor module according to claim 1, wherein the resistor substrate is any one of a single crystal Si substrate, a GaAs substrate, and an InP substrate , and has a structure arranged in contact with a surface on which the circuit of the semiconductor chip is not formed.
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