JP4309869B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a fine structure and a manufacturing method thereof.

  Structures using nanometer-scale fine semiconductor crystals can be applied to various devices, and have been actively reported including their fabrication methods. However, most of the conventional techniques use a special method that is not suitable for ordinary mass production of semiconductors.

  That is, in the method of forming fine crystals in the gas phase using low-pressure CVD or plasma CVD and depositing them on a substrate cooled to a low temperature, the conventional semiconductors are caused by the generation of particles that are a problem in the mass production process of fine elements. It is not consistent with the process. In addition, it is difficult for the fine crystals formed in the gas phase to be complexed on the substrate surface and to uniformly distribute the desired fine crystals.

  On the other hand, a semiconductor element called MOS has been used in a conventional large scale integrated circuit. The degree of integration increases year by year, and the gate length of 256 Mbit DRAM is 0.25 μm (1996), 1 Gbit DRAM is 0.18 μm (2000), and 4 Gbit DRAM is 0.13 μm (2005). Thus, progress in miniaturization is predicted.

  However, there is a limit to the current miniaturization technology using photolithography technology, and there are many problems in electron beam (EB) exposure and X-ray lithography, which are the next technologies of photolithography technology.

  In exposure using the EB apparatus, the radius of the electron beam reaches the order of 10 nm, but the processing limit is 50 nm at most due to the resolution limit of the resist.

  In addition, in microfabrication using X-rays, in order to use synchrotron light, enormous capital investment is required as an apparatus, and the production efficiency is not increased for that, and practical application is not realistic. . Furthermore, since X-rays are radiation, it is difficult to adversely affect the human body.

  From the above points, mass production of semiconductor elements having a gate length of 0.05 μm (50 nm) or less is considered difficult at this stage.

On the other hand, from the viewpoint of element miniaturization, a miniaturized element called a single electronic element has been studied. In this device, when the capacitance C of the device is sufficiently small and the charging energy (e ² / (2C)) stored in the tunnel junction is sufficiently large with respect to temperature fluctuation (approximately equal to kT) (e ² / (2C)> kT), which utilizes the principle of so-called Coulomb blockade, in which electron tunneling is suppressed. By utilizing this property, a threshold value is generated in the current-voltage characteristic. In addition to the characteristic of low power consumption, the existence of this threshold value has led to many proposals for various applications such as a three-terminal transistor and a memory.

In order to actually exhibit the Coulomb blockade effect, when a normal device is operated at room temperature, it is necessary to form a tunnel junction having a small capacitance of about aF (10 ⁻¹⁸ farad).

  Although there is an example in which the operation check at room temperature of the Coulomb blockade effect is performed using a special method such as that found in Non-Patent Document 1 and Non-Patent Document 2, etc., in the current normal semiconductor manufacturing technology It is extremely difficult to make such a small junction.

  However, since the Coulomb blockade effect has been confirmed to actually operate at room temperature, it is expected as a new technology that can be actually incorporated into an LSI circuit.

  However, the conventional single electronic device and the manufacturing method thereof have the following problems, and have not yet been actually applied to LSI devices.

(1) In a manufacturing method using a photomask in a normal LSI manufacturing process, it is difficult to manufacture a capacitance that is small enough to allow the Coulomb blockade to be observed at a sufficiently high temperature because of the limit of lithography miniaturization.

(2) Regarding the tunnel barrier itself that determines the intrinsic tunneling properties of Coulomb blockade, the characteristics of the tunnel barrier itself have been greatly limited from the manufacturing method, and it is not possible to produce a single electronic device having characteristics according to the circuit. It was difficult.

(3) A portion where electrons tunnel in a normal single-electron device is a tunnel junction formed using an insulator such as an oxide film or a substance having a high energy barrier in a band diagram. Due to the high, unless the thickness of the energy barrier is reduced, the tunneling probability of the electrons themselves decreases exponentially. For this reason, it is particularly necessary to control the thickness of the oxide film very delicately, which makes it more difficult to produce a uniform element.
IEDM'93-541 (Yano et al) IEDM'94-938 (Takahashi et al.)

  A first object of the present invention is to provide a method for producing a semiconductor microcrystal that can be easily incorporated into a mass-produced semiconductor manufacturing process, and to provide a semiconductor device using the method.

  The second object of the present invention is to provide a structure of a semiconductor device having a gate length of 50 nm or less, particularly a MOS device, and a manufacturing method that can be mass-produced and does not have a harmful effect on the human body.

  A third object of the present invention is to provide a single electronic device having a fine gate length and good controllability and a method for manufacturing the same.

  In order to solve the above problems, a semiconductor device of the present invention includes a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a first semiconductor microcrystal formed on the first insulating layer. At least one double semiconductor microcrystal on which a second semiconductor microcrystal is stacked via a second insulating layer, and the first insulation so as to cover the at least one double semiconductor microcrystal A third insulating layer selectively formed on the layer, a conductive layer formed on the third insulating layer and having at least two opposite sides, and along the two opposite sides of the conductive layer And a pair of impurity-doped regions formed so as to sandwich the conductive layer on the surface of the semiconductor substrate.

  Furthermore, the diameter of the double semiconductor microcrystal is 50 nm or less.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a layer of group IV atoms made of either amorphous or polycrystalline on a substrate to a thickness of 0.3 nm or more and 5 nm or less at a low temperature of 500 ° C. or less. And after the formation of the group IV atom layer, the group IV atom layer is agglomerated by heating at a high temperature of 600 ° C. or more and 850 ° C. or less to form a group IV atom, which is distributed two-dimensionally and independent of each other. And a step of forming a hemispherical fine crystal having a diameter of 50 nm or less.

  In the manufacturing method described above, it is preferable that the substrate is made of a silicon oxide film and the layer of group IV atoms is made of silicon.

  Alternatively, the substrate may be made of a silicon oxide film, and the group IV atom layer may be made of germanium.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a band-shaped silicon oxide film layer having a width of 100 nm or less on a silicon substrate, and a silicon layer made of either amorphous or polycrystalline on the substrate, The silicon layer is agglomerated at a low temperature of 500 ° C. or lower at a thickness of 0.5 to 5 nm and at a high temperature of 730 to 850 ° C., and aligned in a row on the band-shaped silicon oxide layer. And a step of forming a plurality of silicon microcrystals.

  In the method for manufacturing a semiconductor device of the present invention, the germanium thin film layer is agglomerated by a step of forming a germanium thin film crystal layer of 8 atomic layers or less on a silicon substrate and a heat treatment at 600 to 800 ° C. A step of forming a plurality of germanium microcrystals; and a step of forming a silicon crystal layer on the silicon substrate and embedding the plurality of germanium microcrystals after the formation of the plurality of germanium microcrystals. .

  The semiconductor device of the present invention (Claim 9) includes a first silicon layer containing impurities of a first conductivity type, a second silicon layer containing no impurities formed on the first silicon layer, A plurality of germanium microcrystals having a diameter of 100 nm or less formed on the second silicon layer, and a third layer that does not contain impurities and is formed to embed the plurality of germanium microcrystals on the second silicon layer. It is characterized by comprising a silicon layer and a fourth silicon layer formed on the third silicon layer and containing a second conductivity type impurity.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a first oxide film of the group IV atom on a substrate including a group IV atom, and a step of forming the group IV atom including the IV group atom on the first oxide film. 1 layer, a step of forming a second oxide film of the group IV atom on the first layer, and an amorphous or polycrystalline layer on the second oxide film. And forming the second layer of group IV atoms into a thickness of 0.3 to 5 nm at a low temperature of 500 ° C. or less, and heat-treating at 600 to 850 ° C. to agglomerate the second layer. At least, a step of forming a plurality of microcrystals having a diameter of 50 nm or less made of the group IV atoms, and using the plurality of microcrystals as a mask, the second oxide film other than the lower portion of the microcrystals, the first And a step of removing the layer by etching.

  A semiconductor device according to the present invention includes a semiconductor substrate, a first gate insulating film formed in a predetermined region of the semiconductor substrate, and a plurality of semiconductor fine particles having a diameter of 50 nm or less formed on the first gate insulating film. A structure, a second gate insulating film formed on the first gate insulating film and embedding the plurality of semiconductor microstructures, a gate electrode formed on the second gate insulating film, and the gate electrode A pair of impurity diffusion layers formed along the gate electrode on the semiconductor substrate on both sides of the semiconductor substrate, and each of the plurality of semiconductor microstructures is vertically separated through an interlayer insulating film It contains at least two semiconductor microcrystals.

  In the present invention, a semiconductor microcrystal is formed by utilizing the property that a thin film layer made of a material different from the substrate thinly deposited on the substrate is agglomerated when heated at a high temperature under the condition that the surface is not oxidized. By utilizing the agglomeration generated by heating at a high temperature in a highly clean atmosphere after depositing the thin film layer, a semiconductor microcrystal production technique having high compatibility with a normal semiconductor manufacturing process can be provided.

  In order to achieve the second object, a semiconductor device of the present invention (Claim 12) includes a semiconductor substrate and a bulk conductor having a diameter of 50 nm or less formed in a band shape on the semiconductor substrate via a gate insulating film. A gate electrode formed continuously; and first and second impurity-doped regions formed on the semiconductor substrate so as to sandwich the gate electrode along both sides of the belt-like gate electrode. And

  The method for manufacturing a semiconductor device includes a step of implanting particles so as to cross an insulating film formed in an element region on a semiconductor substrate and forming a plurality of damaged portions on the surface of the insulating film; and Forming a plurality of massive conductors having a diameter of 50 nm or less on the insulating film as nuclei, and forming the strip conductors by continuing the plurality of massive conductors.

  The step of forming the plurality of massive conductors is characterized in that after the material having a surface migration larger than the surface migration of the insulating film is uniformly grown, the material is agglomerated by heat treatment.

  When silicon is epitaxially grown after being damaged by an electron beam (EB) or the like on the insulating film (oxide film), a mass of silicon begins to grow from the damaged position in the initial stage of crystal growth. . Although the size depends on the time of crystal growth, dots having a size of less than 50 nm are formed with good controllability.

  In a MOS type semiconductor device, after forming a gate oxide film on a portion where a gate electrode is to be formed, EB is implanted so that the beam diameter of the EB is reduced so that the interval between the EBs is several tens of nm. Thereafter, this crystal growth is performed, and when the size of the dot generated in the initial stage of the growth is matched with the band of the electron beam that has been implanted, a band of silicon dots is generated. By connecting the end of the dot band to a normal electrode pad, a three-terminal MOS FET having a gate length depending on the dot size is formed.

  Since this step does not use a resist, the limit of the resist itself does not limit the gate length, and the controllability is improved. In addition, it has a large installation area and no adverse effects on the human body like X-rays, and is also characterized by excellent production technology.

  In order to achieve the third object of the present invention, a semiconductor device of the present invention is formed so as to surround a predetermined region on a semiconductor substrate, each of a plurality of protrusions each having a diameter of 50 nm or less, and the plurality of protrusions A gate electrode formed on the predetermined region including the surface of the first electrode through a gate insulating film; first and second semiconductor layers to which impurities are added opposite to the predetermined region; and the predetermined region And an inversion layer formed on the substrate surface between the plurality of protrusions when a voltage is applied to the gate electrode in the region.

  The method for manufacturing a semiconductor element includes a step of forming a plurality of damaged portions with accelerated particles in a first insulating film formed on a surface of a semiconductor substrate, and a thickness of 5 nm or less at a low temperature of 500 ° C. or less. The step of forming an amorphous layer composed of group IV atoms and high-temperature heating at 600 ° C. or higher cause the amorphous layer to be agglomerated with the damaged portion as a nucleus and separated from each other on the first insulating film. A step of forming a plurality of block conductors with a fine crystal having a size of 50 nm or less; and using the plurality of block conductors as a mask, the first insulating film is removed by etching, and an electrode layer is formed on the entire surface through the second insulating film. And a forming step.

  The step of forming the plurality of massive conductors is to uniformly grow a material having a surface migration larger than the surface migration of the first insulating film, and then to agglomerate the material by heat treatment. And

  In the single electronic device of the present invention, an island portion that requires a fine structure to accurately control the number of charges is subjected to ultra high vacuum (UHV) -CVD after being damaged by an electron beam or the like. The inversion layer region between the generated silicon fine dots is used.

  In this method, the size of the island is determined by the distance between the silicon fine dots around the island and the size of the silicon fine dots generated by UHV-CVD. Conventional island sizes are limited to the dimensions themselves due to lithography limitations.

  In the present invention, if the distance between the silicon fine dots around the island is the critical dimension of the current lithography, the size of the inversion layer island finally formed can be controlled by controlling the size of the silicon fine dots by UHV-CVD. This can be much smaller than the critical dimensions of current lithography.

  In the present invention, the tunnel barrier is a constricted portion between silicon fine dots connecting the island portion and the source or between the island portion and the drain. When viewed as a band diagram, this portion does not have the height of a potential barrier such as an oxide film, so that the tunnel probability with respect to the processing dimension can be easily controlled.

  According to the present invention, it is possible to provide a method for forming a fine semiconductor crystal on a semiconductor substrate by a technique highly compatible with an existing semiconductor mass production process. Further, by using the fine particle structure of the present invention, a high-performance light-emitting diode, semiconductor laser, memory element, or the like can be realized.

Further, the present invention utilizes the fact that silicon fine dots having a diameter of 50 nm or less are selectively formed in a controlled manner on a SiO ₂ film damaged by irradiation with an electron beam or the like. . For this reason, it is not limited to the characteristics and limits of the resist unlike the ordinary gate electrode forming method. Further, the present invention provides a semiconductor device having a gate length of the order of 10 nm without requiring defects such as X-ray lithography, which requires a large capital investment, is not versatile, is difficult to handle, and has a harmful effect on the human body as radiation. Making it possible.

  In the single electronic device of the present invention, the island portion that requires a fine structure in order to accurately control the number of charges is used for the inversion layer between the silicon fine dots, using the silicon fine dots. As an area.

  In the present invention, if the distance between the silicon fine dots around the island is the critical dimension of the current lithography, the size of the inversion layer island finally formed can be controlled by controlling the size of the silicon fine dots by UHV-CVD. This can be much smaller than the critical dimensions of current lithography. By the above method, it becomes possible to provide a single electronic device that can be sufficiently operated at room temperature and has good controllability and reproducibility.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a method of forming a semiconductor device according to the first embodiment of the present invention. In the first embodiment, fine silicon crystals are formed on a silicon substrate whose surface is thermally oxidized.

  First, a thermal oxide film 11 having a thickness of 100 nm is formed on a silicon substrate 10 having a plane orientation (100) (FIG. 1A). Subsequently, this substrate is introduced into an ultra high vacuum (UHV) CVD apparatus, and an amorphous silicon layer 12 having a thickness of 1 nm is deposited without heating the substrate (FIG. 1B).

In this case, Si ₂ H ₆ gas is used as a raw material for depositing the amorphous silicon layer 12, and the raw material gas molecules are thermally decomposed by an auxiliary heater installed at a position where the substrate position in the CVD apparatus is expected. By subsequently supplying the substrate to the test substrate, it becomes possible to form a silicon thin film even at room temperature where the raw material decomposition does not occur on the substrate surface. Details of the UHV-CVD apparatus used in the present invention are described in JP-A-7-245236.

  An amorphous silicon thin film having a thickness of 1 nm prepared by this method is extremely flat. The method for forming the amorphous thin film is not limited to the UHV-CVD apparatus described in this embodiment. For example, a thin film obtained by a molecular beam crystal growth (MBE) method in which a solid silicon raw material is heated by an electron beam and supplied to the substrate, a plasma CVD method in which a gas raw material molecule is decomposed by plasma discharge and supplied to the substrate is used. The same fine crystal can be formed. The thin film need not be amorphous. The same result can be obtained using a polycrystalline silicon thin film.

  In this case, an important problem is to suppress the entry of impurities such as oxygen into the first thin film layer. When oxygen is mixed into the initial silicon layer, the migration of silicon atoms is suppressed, so that agglomeration does not proceed. In particular, when forming the initial silicon layer, a method such as the LPCVD method in which the substrate temperature is raised and a thin film is formed by surface decomposition of the raw material molecules is not preferable because a large amount of oxygen is likely to be mixed into the interface.

  In this embodiment, the substrate temperature at the time of depositing the silicon thin film is room temperature, but there is no problem in raising the substrate temperature in a range in which oxygen in the oxide film substrate and the deposited silicon do not react. In this case, if the substrate temperature is 500 ° C. or less, the reaction between the raw material silicon and oxygen on the substrate surface can be kept low. However, when the silicon source is supplied from a high temperature source such as a heater for molecular source decomposition, the substrate temperature is desirably 300 ° C. or lower.

  Subsequently, the prepared thin film layer is heated at 800 ° C. without being exposed to the atmosphere (in a state where the surface is not oxidized). Specifically, after the amorphous thin film is formed by UHV-CVD, the auxiliary heater for decomposition of the raw material molecules is turned off, the temperature of the substrate heater is raised, and the substrate is heated in an ultrahigh vacuum for 3 minutes. The amorphous silicon layer formed flat on the thermal oxide film by this heating becomes an independent crystal 13 having a maximum diameter of 10 nm and a height of about 5 nm due to the agglomeration phenomenon (FIG. 1C). That is, silicon fine crystals can be formed on the thermal oxide film.

At this time, the density of the silicon microcrystal formed on the substrate was 3.5 × 10 ¹¹ / cm ³ . This indicates that the silicon atoms of the initial amorphous silicon layer were transformed into microcrystals by mass transfer on the substrate without desorption / evaporation into the gas phase. In this case, when the time for heating the substrate is increased, the size of one crystallite increases. However, when annealing is continued, the silicon atoms react with oxygen on the oxide film substrate and begin to desorb, and eventually the crystallites disappear. .

  In this case, the size of the fine crystal formed can be controlled by the thickness of the amorphous silicon thin film deposited first and the heating temperature for causing the agglomeration. For example, by setting the initial amorphous layer thickness to 0.5 nm and the heating temperature to 730 ° C., the maximum diameter of the fine crystal can be 5 nm and the height can be 2 nm. In this case, under the condition that the initial amorphous thickness is 0.5 nm or less, the reaction with the oxide film occurs when the annealing temperature is high (800 ° C. or higher), and some of the silicon atoms are desorbed. The agglomeration may not progress. Here, the relationship between the annealing condition (temperature and time) and the size of the microcrystal obtained is shown in FIG. 2A with respect to the initial amorphous thickness.

  The above is an example in which an amorphous silicon layer is deposited on an oxide film and microcrystals are formed by heating. Similarly, an amorphous germanium layer is deposited on an oxide film and microcrystals are formed by heating. It is also possible to squeeze. In this case, agglomeration of germanium can occur even at a temperature lower than that of silicon. Therefore, the initial amorphous thickness, annealing conditions, and the size of the obtained microcrystal are as shown in FIG.

  Conventionally, it is known that when a sufficiently thick amorphous silicon layer is heated under the condition that the surface is not oxidized, a flat surface shape is deformed by surface migration and a mushroom-like lump is formed. However, the agglomeration phenomenon that occurs when the thickness of the amorphous layer is reduced is a finding obtained by the present inventors for the first time. In order to form independent microcrystals, the interaction with the base is strong. I found that not important.

  The substrate used in this embodiment is a silicon substrate whose surface is thermally oxidized, but any substrate (for example, a silicon nitride film) can be used as long as high-temperature heating is possible and mixing with silicon does not occur. Is possible. However, in order to cause agglomeration, the surface migration of the deposit is required to be larger than the surface migration of the substrate. Furthermore, if the surface of the substrate is previously patterned with different types of thin film layers, the arrangement, size, etc. of the microcrystals can be controlled according to the pattern.

  As described above, when amorphous silicon is deposited on an oxide film and is agglomerated by heating, oxygen in the substrate and silicon atoms in the microcrystal may react and the microcrystal may disappear depending on the heating conditions. It can happen. However, this is a phenomenon peculiar when the substrate is an oxide film, and cannot occur in a substrate that does not contain oxygen (for example, a silicon nitride film). Accordingly, it is possible to form microcrystals only on the nitride film and to eliminate and extinguish the microcrystals on the oxide film on a substrate in which a part of the oxide film is patterned with a nitride film.

(Second Embodiment)
FIG. 3 is a sectional view showing a method for forming a semiconductor device according to the second embodiment of the present invention. The second embodiment relates to an element to which the fine crystal shown in the first embodiment is applied.

  First, silicon microcrystals are formed by the method of the first embodiment on a silicon substrate 20 (plane orientation (100)) having a thin thermal oxide film 22 having a thickness of about 3 nm (or less) (FIG. 3 ( a)). As in the first embodiment, an initial amorphous layer having a thickness of 0.5 nm is deposited with the substrate temperature kept at room temperature, and then the substrate temperature is heated to 730 ° C. to thereby form microcrystals having a diameter of 5 nm and a height of 2 nm. 22 is formed on the thermal oxide film 21.

  Thereafter, a silicon oxide film layer 23 is deposited by CVD, and a polycrystalline silicon layer 24 is further deposited. A schematic cross-sectional view of the laminated structure formed in this way is shown in FIG. A structure in which a silicon oxide film layer 23 including silicon microcrystals 21 on a silicon crystal substrate 20 and a polycrystalline silicon layer 24 formed thereon can be realized.

  The oxide film layer 23 and the polycrystalline layer 24 are processed into a gate size as if it were a gate oxide film and a gate electrode, respectively, and source / drain regions 26 and 27 are formed by a well-known method, thereby creating a MOSFET structure. (FIG. 3C).

  In this MOSFET, since the silicon microcrystal 22 exists in the gate oxide film 23, an operation different from that of the conventional MOSFET can be expected. That is, for example, by injecting charges into the silicon microcrystal from the substrate side, the threshold voltage of the MOSFET operation can be changed. Furthermore, since the amount of charge accumulated in one microcrystal is small, it can be used as a memory element that captures the accumulation of a minute amount of charge as a change in the threshold voltage of the MOSFET.

  A similar MOSFET structure including silicon microcrystals can be produced using conventional techniques using plasma CVD or the like, but causes various problems. FIG. 4 is a schematic view of a method for producing silicon microcrystals according to the prior art. Gas molecules containing silicon atoms, such as monosilane or disilane, are introduced into the vacuum vessel 31 to generate plasma discharge, and the source molecules are decomposed in the gas phase.

  At this time, if the partial pressure of the raw material molecules is set to an appropriate value, the silicon atoms generated by the decomposition reaction in the gas phase are further bonded to form a fine crystal 33 consisting only of silicon atoms. By depositing these microcrystals on the substrate 34 cooled to a low temperature, the silicon microcrystals can be arranged on a predetermined substrate. In FIG. 4, 32 is a gas inlet, 35 is a substrate support, 36 is a gas outlet, and 37 is an upper electrode.

  Here, when the substrate temperature is high, the microcrystals that have reached the substrate surface are further reacted and bonded to each other, so that a larger crystal is generated and the controllability of the size of the microcrystal is lowered. Usually, the substrate is often kept at a low temperature by a sink cooled with liquid nitrogen or the like.

  The process of cooling these semiconductor substrates to a temperature below room temperature is not employed in the normal semiconductor manufacturing process, and is inconsistent with the conventional manufacturing process. Further, an unnecessarily large amount of fine particles are generated in the gas phase, which is accompanied by generation of particles that cause the greatest decrease in yield in the semiconductor manufacturing process, which is not suitable for a mass production process.

  In addition, in the method based on the prior art in which the microcrystals generated in the gas phase are deposited on the substrate surface, the generated microcrystals randomly reach the substrate. A plurality of microcrystals are combined. In addition, the method based on the prior art in which semiconductor microcrystals generated in the gas phase are arranged on a substrate cooled to a low temperature has a problem that the adhesion between the deposited microcrystals and the substrate is poor.

  FIG. 5A is a schematic cross-sectional view when the microcrystals 42 are arranged on the substrate 41 based on the prior art. It becomes a form in which fine crystals close to a sphere are attached on the substrate. In such a form, when another kind of film is deposited on the substrate on which the microcrystals are arranged, for example, when the silicon oxide film 44 is deposited by the CVD method as in the previous example, the film 44 and the substrate 41 are deposited. There is a high possibility that 'su' 43 will be generated between them (FIG. 5B).

  In addition, the compounded microcrystal as in the previous example also causes 'su'. The 'su' generated in this way is ruptured or shrunk in the subsequent thermal process to destroy the surrounding structure. Troubles caused by such a cause cause a fatal defect in a highly integrated semiconductor process, resulting in a decrease in yield.

  On the other hand, in the method using agglomeration shown in the present invention, since a flatly deposited layer causes agglomeration, it is possible to dispose the microcrystals essentially homogeneously, which causes the occurrence of 'soot'. There is almost no complexation between crystals. Further, since the adhesion between the microcrystal and the substrate is high, the occurrence of 'su' can be drastically reduced in this sense.

  FIG. 6 shows an example in which a structure similar to that shown in FIG. 5B is formed by the method of the present invention. 51 is a silicon substrate, 52 is a microcrystal, and 53 is a silicon oxide film. There is no “s” as seen in FIG.

(Third embodiment)
FIG. 7 is a perspective view showing a configuration of a semiconductor device according to the third embodiment of the present invention. The third embodiment shows another application example of the semiconductor microcrystal of the present invention.

  First, on the silicon crystal substrate 61, a region 62 of a silicon oxide film layer that is partitioned in advance into a length of 1 μm, a width of 100 nm, and a thickness of 20 nm is prepared (FIG. 7A). The oxide film region 62 can be formed by a conventional method in which the entire substrate surface is thermally oxidized and then patterned by a photoetching process.

  Silicon microcrystals are formed on the processed substrate by the method shown in the first embodiment. In this case, the initial amorphous silicon layer is deposited with a thickness of 2 nm and a substrate temperature of room temperature. Thereafter, the substrate temperature is heated to 830 ° C. to form a microcrystal having a diameter of 30 nm. At this time, in a region other than the oxide film region 62 (region where the silicon crystal is exposed), the deposited amorphous silicon becomes a flat layer that is homogeneous with the base crystal by heating.

  On the other hand, when the amorphous silicon layer deposited on the strip-shaped oxide film region 62 is agglomerated by heating, in the vicinity of the boundary of the strip-shaped region 62, silicon atoms are located in the silicon crystal portion outside the oxide film portion. Moving. In addition, in the inner part away from the boundary, it accumulates in the central part of the strip-shaped region 62 to form a microcrystal.

  As a result, as in this embodiment, when the width of the region does not have a sufficient size with respect to the size of the microcrystal generated by the agglomeration, the position of the microcrystal is arranged at the center of the region. It becomes possible to do. As a result, as shown in FIG. 7B, a structure in which microcrystals are arranged in a row at the center of the oxide film region 62 becomes possible.

  As described above, the method of arranging the microcrystals in a row on the strip-shaped oxide film is based on the width (size) of the strip-shaped region, the thickness of the initial amorphous layer to be deposited, and heating for agglomeration. It can be arbitrarily controlled by a combination of temperature and the like. In the present embodiment, an oxide film is used as a region causing agglomeration, but a silicon nitride film or the like can also be used as in the first embodiment.

(Fourth embodiment)
Next, an embodiment in which a germanium quantum confinement structure is formed on a silicon crystal substrate will be described. FIG. 8 is a cross-sectional view showing the basic procedure for creating the quantum confinement structure according to the fourth embodiment.

First, a germanium thin film crystal layer 72 having a thickness of 4 atomic layers (1.23 nm) is formed on a silicon substrate 71 having a plane orientation (100). In this example, a germanium thin film crystal was prepared by a method of thermally decomposing GeH ₄ gas molecules on the substrate surface at 500 ° C. using a UHV-CVD apparatus (FIG. 8A).

  When a germanium crystal layer is formed on a silicon crystal substrate, the generation of dots is observed when the thickness of the thin film layer increases due to the effect of strain generated between the germanium crystal and the silicon crystal. It has been known. However, if the thickness is about 4 atomic layers or less under the temperature conditions used in this embodiment, a thin film crystal layer with high flatness can be obtained. In the case of an 8-atomic layer, the initial flatness is worse than that of a 4-atomic layer or less, but the size of the dots obtained by the agglomeration described below is controlled.

  After the germanium thin film crystal layer is formed, heating is subsequently performed at 750 ° C. for 10 minutes. The germanium thin film layer that has been flat by this heating becomes a fine crystal 73 by agglomeration. Under this condition, a fine crystal having a diameter of 50 nm and a height of 12 nm is formed (FIG. 8B).

The substrate temperature is set again to 600 ° C., and the silicon crystal layer 74 is grown to a thickness of 200 nm using Si ₂ H ₆ as a raw material. At this time, since the shape of the germanium microcrystal does not change, a quantum confinement structure can be created by sandwiching the germanium microcrystal portion between silicon crystals.

  Also in this embodiment, the size of the fine crystal can be controlled by the thickness of the initially formed germanium thin film layer and the heating temperature for agglomeration. By setting the thickness of the germanium thin film layer to a diatomic layer and setting the heating temperature to 700 ° C., the size of the fine crystal can be 10 nm in diameter and 2 nm in height. The size of the microcrystal is shown in FIG. 9 under various conditions. In the diatomic layer of FIG. 9, the temperature is only described at 650 ° C. or more, but the margin in the low temperature region is relatively large, and even if it is 600 ° C., a microcrystal having the same size as 650 ° C. can be obtained. .

  In addition, it is easy to carry out a method of heating and agglomerating a germanium crystal thin film layer formed flat at a low temperature, but microcrystals can also be formed by a method of supplying a germanium raw material onto a silicon substrate heated to a high temperature in advance. Is possible. For example, a germanium raw material can be supplied to a silicon substrate heated to 750 ° C. to form a microcrystal having a size of about 170 nm.

  In the above embodiment, the layer sandwiching the germanium fine crystal is a silicon layer that does not contain an impurity (dopant). . By forming a pn junction in this way, it is possible to inject a current into the germanium quantum dots and produce a light emitting diode. Next, such an example will be described.

(Fifth embodiment)
FIG. 10 is a cross-sectional view of a light-emitting diode produced using the germanium dot production method of the fourth embodiment. The same parts as those in the fourth embodiment are denoted by the same reference numerals, and redundant description is omitted.

  In the present embodiment, a silicon layer 71 containing no impurities is formed on an n-type substrate 70 using phosphorus as a dopant by a thickness of 5 nm by UHV-CVD, and germanium quantum dots 73 are further formed by the method of the fourth embodiment. Then, a 5 nm thick silicon layer 74 containing no impurities is formed again, and a p-type silicon layer 75 using boron as a dopant is formed as the uppermost layer, thereby producing a light emitting diode.

  In this case, germanium quantum dots serve as the emission center, and when the size is about 10 nm at the maximum, red to infrared emission can be confirmed.

(Sixth embodiment)
FIG. 11 shows another example of a light-emitting diode created using the germanium dot creation method of the fourth embodiment.

  On the n-type silicon substrate 81, a first silicon layer 82 having a thickness of 5 μm and containing no dopant is formed, and germanium dots 83 are formed thereon by the method of the fourth embodiment. A second silicon layer 84 having a thickness of 1 μm and containing no dopant is formed thereon, n-type impurities are ion-implanted from the surface to form an n-type region 85, and p-type impurities are further ion-implanted to form p-type. Region 86 is formed. As a result, a pin junction is formed to form a light emitting diode.

  In this method, since a normal silicon mass production process is used except for the germanium dot production process, a large amount of light-emitting diodes can be produced on a large-diameter silicon substrate, and elements can be easily integrated and combined. .

(Seventh embodiment)
FIG. 12 is a cross-sectional view showing the procedure for producing the light-emitting diode according to the seventh embodiment. In the present embodiment, an example is shown in which a germanium quantum dot region is formed on a n-type silicon substrate patterned with a silicon oxide film by using a selective growth method.

  As shown in FIG. 12A, an opening 98 having a diameter of 10 nm is provided in a thermal oxide film 92 having a thickness of 100 nm formed on an n-type substrate 91. Next, a silicon layer 93 having a thickness of 10 nm is grown in the opening 98 by a selective growth method. Further, a germanium layer 94 having a thickness of 1.5 atomic layers is laminated thereon by the same selective growth method (FIG. 12B).

  Thereafter, high-temperature heating is performed at 700 ° C. to form a germanium fine crystal 95 (FIG. 12C). Further, after a silicon layer 96 having a thickness of 10 nm is grown by a non-selective growth method, a silicon layer 97 containing a p-type dopant is formed to create a pin diode structure (FIG. 12D).

  As described above, by forming the light emitting diode portion in the region surrounded by the silicon oxide film, the light confinement structure due to the difference in refractive index can be easily formed. In addition, it is extremely advantageous because it can be configured by application of a conventional silicon process. It is also possible to form a waveguide by the shape of the surrounding oxide film or a combination with other materials by an existing semiconductor process.

(Eighth embodiment)
FIG. 13 is a cross-sectional view of a surface emitting laser according to an eighth embodiment. In the present embodiment, the structure of the seventh embodiment is formed on an SOI substrate. In addition to element isolation, light confinement can be easily performed in the vertical direction of the substrate. According to this structure, a surface emitting laser in which a large number of elements are integrated can be produced by extracting light from the substrate surface side.

  An SOI substrate having a p-type silicon layer (SOI layer) 103 with a thickness of 150 nm is prepared on a silicon substrate 101 with a silicon oxide film 102 with a thickness of 500 nm interposed therebetween. A thermal oxide film 104 having a thickness of 200 nm is formed on the surface of the substrate. At this time, the thickness of the SOI layer 103 remains 50 nm.

  Subsequently, an opening of 1 μm × 250 μm is provided in the thermal oxide film on the surface to expose the underlying SOI layer 103. As a result, a silicon layer can be grown only on the exposed silicon layer.

  A thin silicon layer is grown on the substrate to a thickness of 100 nm using a selective growth method. In this case, boron is added as an impurity to the lower 50 nm to form the p-type layer 105, and the upper 50 nm is formed to the silicon layer 106 containing no impurity.

  Further, a germanium thin film having a thickness of 3 atomic layers is formed thereon by the method described in the fourth embodiment, and is then deformed into germanium dots 107 by high-temperature heating. At this time, the typical size of the germanium dots is 10 nm. Further, in the method of the present invention, germane gas molecules are decomposed (selectively grown) only on the silicon crystal, so that no dot is formed on the oxide film.

  A silicon thin film is further grown to 400 nm thereon. At this time, it is performed in a non-selective growth mode in which thin film growth also occurs on the oxide film. Further, out of the film thickness of 400 nm, the lower layer 50 nm is a layer 108 to which no impurity is added, and the upper layer 350 nm is a layer 109 containing arsenic at a high concentration.

  The layer thus formed has a pin structure centering on the layer including the germanium quantum dots 107, and a diode capable of current injection is formed. Here, laser excitation is possible by strong excitation.

  Since the layer including the germanium quantum dots 107 is surrounded by the oxide film layer 104 prepared in advance, light confinement is possible. As for the oxide film in the light extraction direction, it is also effective to remove the corresponding portion of the oxide film 104 prepared in advance to expose the silicon layer 103 and then thermally oxidize it again.

  In general, compound semiconductor lasers use a cleaved end face to form cavities, but the configuration of this embodiment can use a thermal oxide film that is well-matched with silicon crystals, so that it is not compatible with fine mass-production processes. There is no need to combine processes.

(Ninth embodiment)
Next, a semiconductor device having two silicon fine particles stacked via a tunnel oxide film will be described. FIG. 14 is a cross-sectional view of the semiconductor device showing the production procedure.

  A polycrystalline silicon layer 112 having a thickness of 5 nm is formed on the first oxide film 111 having a thickness of 7 nm formed on the semiconductor substrate 110. However, this layer does not necessarily have to be polycrystalline. Even when an SOI substrate having a thin-film crystalline silicon layer is used, the subsequent processes are the same, and the same effects are obtained.

  Subsequently, an oxide film 113 is formed on the surface of the polycrystalline silicon layer (FIG. 14A). This oxide film may be formed by a normal thermal oxidation method, and a 1.5 nm oxide film is formed on the surface. As a result, the thickness of the polycrystalline silicon layer 112 becomes about 4.8 nm. The oxide film 113 may be a deposited oxide film formed by a CVD method.

  Subsequently, an amorphous silicon layer 114 having a thickness of 1 nm is formed on the oxide film 113 (FIG. 14B). The amorphous silicon is preferably formed at a low temperature of 500 ° C. or lower. That is, the steepness of the layer change between the substrate side oxide film 113 (tunnel oxide film) and the upper silicon layer 114 is required.

  After the amorphous silicon layer 114 is formed, the processed substrate is heated to about 800 ° C. By this heating, the uppermost amorphous silicon layer 114 is agglomerated to become fine crystals 115 having a particle diameter of about 10 nm (FIG. 14C). Specifically, hemispherical silicon fine particles having a diameter of 10 nm can be formed by applying an initial amorphous silicon layer of 1 nm and heating at 800 ° C. for 3 minutes.

  It is desirable that the steps after the formation of the polycrystalline silicon layer 112 or the lowermost oxide film 111 are continuously performed in the same processing chamber without being exposed to the atmosphere. This is because a natural oxide film is formed on the surface of the polycrystalline silicon layer 112 when exposed to the atmosphere, and the designed film thickness may not be obtained in the oxide film 113. Further, when the amorphous silicon layer 114 is heated to be agglomerated, it is necessary that the surface of the amorphous silicon layer 114 is not oxidized. Further, as described above, the steepness of the layer change between the substrate side oxide film 113 and the upper silicon layer 114 is an important factor.

  Subsequently, the substrate is taken out from the film forming apparatus, and etching is performed using the formed silicon fine particles 115 as a mask. Etching may be dry etching or wet etching. First, after removing the natural oxide film and the oxide film layer on the polycrystalline silicon layer 112 generated by taking out the air, the polycrystalline silicon layer 112 is etched away.

  At this time, the silicon microcrystal 115 serving as a mask is also etched at the same time, but by controlling the etching amount, the silicon fine particles 115 obtained by the agglomeration and the polycrystalline silicon underneath are left, and the polycrystalline silicon layer in other regions is left. 112 can be removed. In this embodiment, by etching the polycrystalline silicon layer using a silicon fine particle having a diameter of 10 nm immediately after agglomeration as a mask, the diameter of the silicon microcrystal becomes 3 nm, leaving only the polycrystalline layer below it. Was possible.

  In addition, when the polycrystalline silicon layer is etched, the etching can be stopped at the oxide film under the polycrystalline silicon layer by using an etching method that is selective to the oxide film. However, in this case, different etchings must be alternately repeated for removing the oxide film on the surface and removing the polycrystalline silicon layer.

  By the above method, a fine particle structure 116 in which silicon fine particles are stacked on an oxide film can be formed (FIG. 14D). Using the double fine particles 116 thus created, a memory element configuration as shown in FIG. 15 is possible.

  An oxide film 117 is deposited to a thickness of 25 nm by a CVD method on the substrate including the double fine particles 116, and the double fine particles 116 are embedded. After depositing the oxide film 117, a polycrystalline silicon layer 118 is formed, processed into a gate electrode, and further a source and drain region (impurity addition region) 119 is formed, thereby completing a nanocrystal memory including double fine particles. If this double fine particle is used as a floating gate, a memory capable of finer control is realized.

  Here, the operation of the nanocrystal memory shown in FIG. 15 will be described. First, a strong electric field is applied between the substrate 110 and the gate electrode 118 so that the gate electrode side has a positive potential. At this time, a tunnel current flows through the gate oxide film, and electrons are accumulated below the double fine particles 116. Once the electrons accumulated in the double fine particles are confined in the barrier of the oxide film, they are hardly released even if the electric field between the substrate and the gate electrode is weakened. When a voltage is applied between the source and the drain while electrons are accumulated in the lower part of the double particle, the current between the source and the drain is controlled due to the electric field generated by the electron in the lower part of the particle.

  Next, when a weak electric field having a positive potential on the gate electrode side is applied between the gate electrode and the substrate, the electrons existing under the double fine particles move to the top of the double fine particles. Also in this case, since the upper part and the lower part of the double fine particles are separated by the tunnel oxide film, even if the electric field between the gate electrode and the substrate is returned, the electrons stop at the upper part of the double fine particles. In this state, the electric field applied to the channel is weakened as compared with the case where electrons are accumulated under the double fine particles. Therefore, it becomes easy to flow when applying a voltage between the source and the drain to flow a current.

  That is, the ease of current flow between the source and the drain changes due to the movement of electrons to the upper or lower part of the double fine particles. This can be detected as a change in the threshold voltage of the MOSFET. The movement of electrons between the upper and lower sides of the double fine particles can be controlled by positive / negative of the voltage applied to the gate electrode.

  In the conventional nanocrystal memory, the electrons introduced from the channel through the gate oxide film to the fine particles are held in the fine particles, so that the memory retention operation is performed, so that the electrons can be easily introduced into the fine particles. There were conflicting events (ie, ease of writing and speed of storage) and stability of retention of electrons in the microparticles (ie, retention time of memory).

  On the other hand, in the present invention, since the gate oxide film between the double fine particles and the channel is set to be relatively thick as 7 nm, electrons once confined in the double fine particles can be stably held. Further, since ON / OFF of the memory is performed by movement of electrons between thin tunnel oxide films in the double fine particles, higher speed operation is possible.

(Tenth embodiment)
FIG. 16 is a cross-sectional view showing a procedure for creating a triple fine particle structure according to the tenth embodiment of the present invention, and FIG. 17 is a cross-sectional view of a finished product of this embodiment.

  On the first oxide film 121 formed on the semiconductor substrate 120, a first polycrystalline silicon layer 122 having a thickness of 5 nm, a second oxide film layer 123 having a thickness of 3 nm, and a thickness again thereon. A second polycrystalline silicon layer 124 having a thickness of 5 nm is stacked, and a third oxide film layer 125 having a thickness of 3 nm is formed as the uppermost layer (FIG. 16A).

  Next, an amorphous germanium layer 126 having a thickness of 1 nm is deposited on the third oxide film layer 125 (FIG. 16B). The subsequent processes are almost the same as those in the ninth embodiment. A heat treatment is performed under the condition that the surface of the amorphous germanium layer 126 is not exposed to the atmosphere, and germanium fine particles 127 are formed by the agglomeration phenomenon (FIG. 16C). Here, the size of the germanium fine particles is 10 nm in diameter.

  Further, using the germanium fine particles 127 as a mask, the lower oxide films 125 and 123 and the polycrystalline silicon layers 124 and 122 are etched (FIG. 17). When the lower polycrystalline silicon layer is etched using the germanium fine particles as a mask, the etching can be performed even when there are a plurality of lower silicon layers because the selectivity at the time of etching is high. This method makes it possible to create a triple particle structure 128 in which triple particles separated by a thin oxide film are stacked as shown in FIG.

  FIG. 18 shows an application example of a double fine particle structure. A plurality of double fine particles 116 separated by a thin oxide film are arranged in a row on the substrate 110, and electric charges are injected into only one fine particle on each double fine particle. At this time, due to the repulsive force between the charges, the fine particles on the same side (upper or lower) of the adjacent double fine particles on the line cannot stably hold the charges, and the fine particles on the different sides are charged. Is accumulated. Therefore, when a plurality of double fine particles are aligned, electric charges are alternately accumulated in the upper and lower fine particles (FIG. 18A).

  In this case, when the position of the charge of the double fine particle at one end of the line is reversed, the charge position of the adjacent double fine particle is also reversed. This inversion phenomenon propagates to the adjacent double fine particles on the line one after another (FIG. 18B). Therefore, if the position of the electric charge of the double fine particles located at one end on the line is inverted at a certain period (frequency), the periodic signal can be propagated one after another, and it can behave as if it is an electrical wiring.

  Next, an embodiment relating to a semiconductor element having a fine gate electrode structure to which the fine structure of the present invention is applied will be described.

(Eleventh embodiment)
19 and 20 are schematic plan views for explaining the method for forming the gate electrode of the MOS type semiconductor device according to the eleventh embodiment of the present invention. A method for manufacturing this semiconductor device will be described below.

  First, as shown in FIG. 19A, an element isolation region 132 is formed by LOCOS (Local Oxidation of Silicon) so as to surround an element region 131 where an active element is formed on a silicon substrate.

  Next, as shown in FIG. 19B, after forming a gate insulating film (not shown) in a portion where the gate of the element region 131 is formed, an electron beam is continuously implanted at an interval of 20 to 30 nm. At this time, the electron beam is linearly injected including the LOCOS region in the gate width direction. By this electron beam implantation, the crystal structure of the gate insulating film (silicon oxide film) is destroyed and a damaged portion 133 is formed.

  Next, the substrate is introduced into an ultra high vacuum (UHV) CVD apparatus, and amorphous silicon fine dots 134 are formed without heating the substrate (FIG. 19B). FIGS. 21A and 21B are enlarged perspective views for explaining the portion of the damaged portion 133 of the gate portion and the shape of the silicon fine dots formed thereon.

In this case, Si ₂ H ₆ gas is used as a raw material for producing amorphous silicon, and this raw material gas is thermally decomposed by an auxiliary heater installed at a position where the substrate surface in the CVD apparatus is viewed, and then this is used. By supplying to the substrate, an amorphous silicon thin film having a thickness of 5 nm is formed on the substrate surface. The 5 nm amorphous silicon thin film prepared by this method is extremely uniform.

  Subsequently, when heated at 850 ° C., the surface migration of the amorphous silicon is smaller than that of the silicon oxide film, so the amorphous silicon is condensed into dots having a height of about 25 nm and a diameter of about 50 nm and are electrically connected to each other. Are connected to form a strip-like gate electrode. According to this method, it is possible to form silicon fine dots even at a temperature at which raw material decomposition does not occur.

  By forming a gate electrode pad 135 formed by lithography with ordinary light at the end of the band of silicon fine dots formed in this way, a gate electrode having a gate length of 50 nm is formed. Electron concentration is increased by implanting impurity ions into the structure in which the gate electrode is formed, and a source region 136 and a drain region 137 are formed on both sides of the gate electrode. A source electrode 136a and a drain electrode 137a are formed at the end portions of the source region 136 and the drain region 137, respectively. A MOS type semiconductor device is completed by forming an upper layer wiring via an interlayer insulating film on this structure.

  The present invention can be applied to a process of creating fine electrodes for all elements used in an LSI circuit, including MOSFETs using SOI.

(Second Embodiment)
22 to 25 are views for stepwise explaining a method for manufacturing a single electronic device according to the second embodiment of the present invention. (A) of each figure is a top view, (b) is sectional drawing along the AA 'line or BB' line of a corresponding top view.

First, as shown in FIG. 22, an element region 141 surrounded by a LOCOS 142 is formed on a semiconductor substrate 140, and then the entire region is oxidized or an SiO ₂ oxide film 143 having a thickness of about 100 nm is formed by CVD. 141 is formed.

  Next, as shown in FIG. 23, four points surrounding the region 144 forming the island part of the single electron element are irradiated with an electron beam or the like to destroy the crystal structure of the oxide film 13 as a point, and the damaged portion 145 is formed. Form. Subsequently, this substrate is introduced into a high vacuum (UHV) CVD apparatus, and amorphous silicon fine dots 146 are formed without heating the substrate.

In this case, Si ₂ H ₆ gas is used as a raw material for producing amorphous silicon, and this raw material gas is thermally decomposed by an auxiliary heater installed at a position where the substrate surface in the CVD apparatus is viewed, and then this is used. By supplying to the substrate, an amorphous silicon thin film having a film thickness of 5 nm or less is formed on the substrate surface at a low temperature of 300 ° C. or less.

  In this embodiment, the substrate temperature at the time of depositing the silicon thin film is set to room temperature, but there is no problem in raising the substrate temperature as long as oxygen in the oxide film substrate does not react with the deposited silicon. In this case, if the substrate temperature is 500 ° C. or less, the reaction between the raw silicon and oxygen on the substrate surface can be kept low. However, when the silicon raw material is supplied from a high temperature source like a heater for molecular raw material decomposition, the substrate temperature is desirably 300 ° C. or lower.

  Subsequently, when heated at 730 to 850 ° C., the surface migration of the amorphous silicon is smaller than that of the oxide film, so the amorphous silicon is condensed into dots having a diameter of 50 nm or less and independent of each other. Form fine crystals.

  The formation of the fine dots is not limited to amorphous, and other group IV elements may be used instead of silicon. Also, the formation method is not limited to the UHV-CVD apparatus. For example, the molecular source crystal growth (MBE) method in which a solid silicon source is heated by an electron beam and supplied to the substrate, or the gas source molecules are decomposed and supplied to the substrate by plasma discharge. Plasma CVD may be used.

  Note that the number of damage points due to the electron beam is not limited to four, and any number may be used as long as it surrounds the island. However, the distance between the damaged portions is set to be slightly larger than the diameter of the fine dots to be formed later, for example, 100 to 200 nm in this example.

Next, as shown in FIG. 24, the SiO ₂ film 143 formed on the element region 141 is removed by etching using hydrofluoric acid. At this time, the silicon fine dots 146 are used as a mask, and the SiO ₂ layer 143 is left under the silicon fine dots 146.

  Next, as shown in FIG. 25, gate oxidation is performed on the entire device to form a gate oxide film 147 of about 5 nm. Subsequently, a gate electrode 148 such as polysilicon is formed on the portion including the island 144. The electrode material here is not limited to polysilicon but may be a metal such as aluminum.

  Next, impurity ions are implanted into the source and drain regions to increase the electron concentration in the source and drain regions. A single electronic device is completed by forming an upper layer wiring via an interlayer insulating film on this structure.

  In this embodiment, the number of silicon fine dots is four, but a large number of silicon dots may be provided so as to surround the island as described above. FIG. 26 shows an example in which the number of damaged portions is six and the number of islands in which electrons are stored is two in series in the source / drain direction as indicated by reference numerals 151 and 152. By providing the gate electrodes 153 and 154 for controlling these two islands, multi-valued logic control can be performed according to the number of electrons stored in the two islands.

  Further, as indicated by reference numerals 161 and 162 in FIG. 27, the number of islands may be two in parallel in the source / drain direction. In this case, since the total number of electrons stored in the island is two, the current capacity can be increased.

In the single electronic device of the present invention, in order to form an island portion where charges are accumulated, a region surrounding the island is damaged by an electron beam or the like, and silicon formed in the UHV-CVD apparatus centering on this damage After etching the SiO ₂ film with hydrofluoric acid or the like using the fine dots as a mask, gate oxidation and a method of forming an electrode layer such as polysilicon are employed.

  Therefore, the accuracy of the mask only requires the accuracy of the interval between the first damage points. The size of the charge storage island formed as an inversion layer (149 in FIG. 25B) in the region surrounded by the silicon dots is determined in accordance with the size of the grown silicon dots. For this reason, it is possible to form an island having a size equal to or smaller than the limit processing even by using a conventional processing technique.

  In this embodiment, since the diameter of the silicon fine dot is about 50 nm, the planar gate electrode length is about 100 nm. However, if the diameter of the silicon fine dot is 25 nm, the gate length may be about 50 nm. Is possible.

Sectional drawing of the semiconductor substrate which shows the preparation procedure of the silicon microcrystal which concerns on the 1st Embodiment of this invention In the method for producing microcrystals of the first embodiment, the relationship between the annealing conditions and the size of the microcrystals obtained with respect to the initial amorphous thickness is shown. (A) is silicon, (b) is For germanium Sectional drawing which shows the preparation procedure of the MOS type semiconductor device which concerns on the 2nd Embodiment of this invention Schematic diagram of a plasma CVD apparatus for explaining problems when a semiconductor device similar to the semiconductor device of the second embodiment is produced by the prior art Sectional view of silicon microcrystal prepared by CVD apparatus in FIG. Cross-sectional view of silicon microcrystal prepared by the present invention The perspective view for demonstrating the production method of the silicon microcrystal which concerns on the 3rd Embodiment of this invention. Sectional drawing for demonstrating the preparation method of the germanium microcrystal which concerns on the 4th Embodiment of this invention. The figure which shows the relationship between the annealing conditions and the magnitude | size of the obtained microcrystal with respect to the initial germanium thickness in the preparation method of the germanium microcrystal of 4th Embodiment. Sectional drawing of the light emitting diode incorporating the germanium microcrystal concerning the 5th Embodiment of this invention Sectional drawing of the light emitting diode incorporating the germanium microcrystal concerning the 6th Embodiment of this invention Sectional drawing which shows the preparation procedure of the light emitting diode incorporating the germanium microcrystal based on the 7th Embodiment of this invention Sectional drawing of the surface emitting laser incorporating the germanium microcrystal concerning the 8th Embodiment of this invention Sectional drawing which shows the preparation procedure of the double fine particle structure which concerns on the 9th Embodiment of this invention Sectional drawing of the memory element incorporating the double fine particle structure based on the 9th Embodiment of this invention Sectional drawing which shows the preparation procedure of the triple fine particle structure which concerns on the 10th Embodiment of this invention. Sectional drawing of the finished product of the triple fine particle structure based on the 10th Embodiment of this invention Typical sectional drawing for demonstrating the application example of the double fine particle structure of this invention Plan view for explaining a method for manufacturing a MOS semiconductor device according to the eleventh embodiment of the present invention. FIG. 19 is a plan view of the completed semiconductor element, which is the next stage of FIG. The perspective view explaining the formation method of the silicon fine dot in 11th Embodiment It is a figure for demonstrating the manufacturing method of the semiconductor element concerning the 12th Embodiment of this invention, (a) is a top view, (b) is sectional drawing along the A-A 'line of (a). Plan view and sectional view showing the next stage of FIG. Plan view and sectional view showing the next stage of FIG. FIG. 25 is a plan view and a cross-sectional view showing the next stage of FIG. The top view of the semiconductor element which has a gate electrode attached to two islands in series in the modification of 12th Embodiment, and each island A plan view of a semiconductor device having two parallel islands and one common gate electrode in a modification of the twelfth embodiment

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 11 ... Silicon oxide film 12 ... Amorphous silicon layer 13 ... Silicon microcrystal 20 ... Silicon substrate 21 ... Silicon oxide film 22 ... Silicon microcrystal 23 ... Silicon oxide film 24 ... Polycrystalline silicon film 25 ... Gate side wall Insulating film 26, 27 ... Source / drain region

Claims (3)

A semiconductor substrate;
A first insulating layer formed on the semiconductor substrate;
At least one double semiconductor microcrystal formed on the first insulating layer;
A third insulating layer formed on the first insulating layer so as to embed the at least one double semiconductor microcrystal;
A conductive layer formed on the third insulating layer and having at least two opposite sides;
A pair of impurity doped regions formed on the surface of the semiconductor substrate along the two opposite sides of the conductive layer so as to sandwich the conductive layer;
And the double semiconductor microcrystal is
A first semiconductor microcrystal formed on the first insulating layer;
A second insulating layer formed on the first semiconductor microcrystal;
A second semiconductor microcrystal formed on the second insulating layer;
A semiconductor device having a stacked structure comprising: The semiconductor device according to claim 1, wherein a diameter of the double semiconductor microcrystal is 50 nm or less. The semiconductor substrate, the first semiconductor microcrystal, and the second semiconductor microcrystal include group IV atoms, and the first insulating layer and the second insulating layer are oxide films of the group IV atoms. The semiconductor device according to claim 1.

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