JP4310797B2 - IC test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC test apparatus for testing an object to be tested based on pattern data output from a pattern memory based on an address, and to an IC test apparatus capable of easily analyzing a defect in a short time.
[0002]
[Prior art]
The IC test apparatus gives a test pattern to an object to be tested, for example, an IC, an LSI, etc., compares the output of the object to be tested with an expected value pattern, and determines pass / fail of the object to be tested. The test pattern, expected value pattern, and the like are stored as pattern data in the pattern memory, and an address is given to the pattern memory to output the pattern data. The main configuration of such an apparatus shown will be described in FIG.
[0003]
In FIG. 2 , an address generator 1 has pattern generation sequencers 11 and 12, and gives addresses to a pattern memory (not shown). The pattern generation sequencers 11 and 12 are provided with one or more index counters 110 and 120, and exclusively give addresses to the pattern memory based on instructions stored in a memory (not shown). The pattern generation sequencer 11 is suitable for continuous addresses, receives an active signal, becomes effective, and outputs an active signal. The pattern generation sequencer 12 is suitable for generating random addresses. The pattern generation sequencer 12 is activated in response to an active signal from the pattern generation sequencer 11 and outputs an active signal to the pattern generation sequencer 11. Index counters 110 and 120 count the number of instruction loops.
[0004]
The failure analysis data storage unit 2 is connected to a data bus and stores a pass / fail for each pin to be tested (not shown) (comparison result of the output to be tested and an expected value pattern), and an address generator 1 And a plurality of index storage units 21 and 22 are stored. The index storage units 21 and 22 are provided for the index counters 110 and 120, respectively, are connected to a data bus, and store the count values of the index counters 110 and 120 as index data. Here, in addition to the address given to the pattern memory, information indicating which one of the pattern generation sequencers 11 and 12 has occurred is added to the address generated by the address generation unit 1.
[0005]
The operation of such an apparatus will be described below. The pattern generation sequencer 11 generates an address based on the instruction, and the instruction counter counts the number of instruction loops. At this time, the pattern generation sequencer 12 does not generate an address. Pattern data is output from the pattern memory based on the address of the pattern generation sequencer 11, the test target is tested, and the pass / fail of each pin of the test target is determined. The pass / fail failure analysis data storage unit 2 stores the pass / fail and the address of the pattern generation sequencer 11, and the index storage units 21 and 22 of the failure analysis data storage unit 2 store the index counters 110 and 120. Stores the count value.
[0006]
By repeating such an operation, the pattern generation sequencer 11 outputs an active signal to the pattern generation sequencer 12 according to an instruction, and stops address generation. As a result, the pattern generation sequencer 12 becomes valid, generates an address based on the instruction, and counts the number of loops of the instruction with the index counter 120. With this address, pattern data is output from the pattern memory, the test target is tested, and the pass / fail of each pin under test is determined. The pass / fail failure analysis data storage unit 2 stores the pass / fail and the address of the pattern generation sequencer 12, and the index storage units 21 and 22 of the failure analysis data storage unit 2 store the index counters 110 and 120, respectively. Stores the count value. Such an operation is repeated.
[0007]
Then, the pattern generation sequencer 12 outputs an active signal to the pattern generation sequencer 11 according to an instruction, and stops address generation. Again, the pattern generation sequencer 11 starts address generation.
[0008]
When such an operation is repeated and the test is completed, data is read from the failure analysis data storage unit 2 via the data bus, and failure analysis is performed. At this time, from the count values stored in the index storage units 21 and 22, the valid ones of the pattern generation sequencers 11 and 12 are picked up, and after only the valid count values are arranged, the failure analysis is performed.
[0009]
[Problems to be solved by the invention]
As described above, when index data is read via the data bus at the time of defect analysis, it takes time to read data because there are many index storage units. Further, there is a problem that data corresponding to the pattern generation sequencers 11 and 12 that are effective for each pattern data is extracted from the read index data, and it takes time to process data such as combinations in time series.
[0010]
Therefore, an object of the present invention is to realize an IC test apparatus that can easily perform defect analysis in a short time.
[0011]
[Means for Solving the Problems]
The first aspect of the present invention is
In an IC test apparatus for testing an object under test using pattern data output from a pattern memory based on an address,
An address generation unit having at least one index counter for counting the number of loops of an instruction, and having two pattern generation sequencers that exclusively give an address to the pattern memory based on the instruction;
Among the pattern generation sequencers of this address generation unit, a selection unit that selects an index counter of the pattern generation sequencer that is giving an address;
The selection unit includes an index storage unit that stores a count value of the selected index counter.
[0012]
The second aspect of the present invention
The address generator is provided with an index controller that selects a selector based on a pattern generation sequencer that provides an address.
It is characterized by having.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same as FIG. 2 is omitted given the same reference numerals.
[0014]
In FIG. 1, an index controller 3 is provided in the address generation unit 1 and receives an active signal from the pattern generation sequencers 11 and 12 and outputs a selection signal. The multiplexer 4 is a selection unit, and selects the count values of the index counters 110 and 120 according to the selection signal of the index controller 3. The plurality of index storage units 23 are provided in the defect analysis data storage unit 2 instead of the index storage units 21 and 22, and store the count values of the index counters 110 and 120 selected by the multiplexer 4 as index data. Connect the bus.
[0015]
The operation of such a device will be described below. The pattern generation sequencer 11 generates an address based on the instruction, and the instruction counter counts the number of instruction loops. At this time, the pattern generation sequencer 12 does not generate an address. In addition, the index roller 3 causes the multiplexer 4 to select the index counter 110 at the time of activation.
[0016]
Pattern data is output from the pattern memory based on the address of the pattern generation sequencer 11, the test target is tested, and the pass / fail of each pin of the test target is determined. Then, the pass / fail failure analysis data storage unit 2 stores the pass / fail and the address of the pattern generation sequencer 11. At the same time, the index storage unit 23 of the failure analysis data storage unit 2 stores the count value of the index counter 110 from the multiplexer 4.
[0017]
By repeating such an operation, the pattern generation sequencer 11 outputs an active signal to the pattern generation sequencer 12 according to an instruction, and stops address generation. As a result, the pattern generation sequencer 12 becomes valid, generates an address based on the instruction, and counts the number of loops of the instruction with the index counter 120. The index controller 3 receives an active signal output from the pattern generation sequencer 11 and causes the multiplexer 4 to select the index counter 120.
[0018]
Pattern data is output from the pattern memory according to the address of the pattern generation sequencer 12, a test of the test target is performed, and a pass / fail of each pin of the test target is determined. Then, the pass / fail failure analysis data storage unit 2 stores the pass / fail and the address of the pattern generation sequencer 12. At the same time, the index storage unit 23 of the failure analysis data storage unit 2 stores the count value of the index counter 120. Such an operation is repeated.
[0019]
Then, the pattern generation sequencer 12 outputs an active signal to the pattern generation sequencer 11 according to an instruction, and stops address generation. Again, the pattern generation sequencer 11 starts address generation. The index controller 3 receives an active signal output from the pattern generation sequencer 12 and causes the multiplexer 4 to select the index counter 110.
[0020]
When such an operation is repeated and the test is completed, data is read from the failure analysis data storage unit 2 via the data bus, and failure analysis is performed.
[0021]
Thus, the index controller 3 causes the multiplexer 4 to select the index counters 110 and 120 based on the pattern generation sequencers 11 and 12 that give addresses, so that only valid count values are stored in the index storage unit 23 in the order of execution. Data processing time can be shortened. In addition, since only one index storage unit 23 is required, the circuit scale can be reduced.
[0023]
Note that the present invention is not limited to this, and the configuration in which the multiplexer 4 is selected using the index controller 3 is shown. However, the active signals from the pattern generation sequencers 110 and 120 are not provided without providing the index controller 3. It may be configured to switch by Alternatively, the index controller 3 may be configured to switch the multiplexer 4 by monitoring the pattern generation sequencers 110 and 120 instead of receiving the active signal.
[0024]
Moreover, although the index storage part 23 showed the example comprised by several memory, the structure which divided | segmented the area | region of one memory may be sufficient.
[0025]
In the example, the defect analysis data storage unit 2 stores all data. However, the defect analysis data storage unit 2 may be configured to store data only at the time of failure.
[0026]
【The invention's effect】
According to the present invention, since the selection unit selects the index counter based on the pattern generation sequencer that provides the address, only valid count values are stored in the index storage unit in the execution order, thereby reducing the data processing time. it can. In addition, since only one index storage unit is required, the circuit scale can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a conventional IC test apparatus.
[Explanation of symbols]
3 Index controller 4 Multiplexer
11, 12 pattern generation sequencer 23 Index storage

Claims (2)

In an IC test apparatus for testing an object under test using pattern data output from a pattern memory based on an address,
An address generation unit having at least one index counter for counting the number of loops of an instruction, and having two pattern generation sequencers that exclusively give an address to the pattern memory based on the instruction;
Among the pattern generation sequencers of this address generation unit, a selection unit that selects an index counter of the pattern generation sequencer that is giving an address;
An IC test apparatus comprising: an index storage unit that stores a count value of an index counter selected by the selection unit. 2. The IC test apparatus according to claim 1, wherein the address generation unit includes an index controller that selects the selection unit based on a pattern generation sequencer that provides an address.

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