JP4311531B2 - Manufacturing method of three-dimensional wiring and capacitive pressure sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a three-dimensional wiring and a capacitance type pressure sensor, and more particularly, through a through hole through a patterned conductive substrate bonded to the back surface of an insulating substrate and a wiring formed on the surface side. The present invention relates to a method for manufacturing connected three-dimensional wiring.
[0002]
[Prior art]
Micromachine technology is a technology that is applied to the production of various devices, parts, etc. by combining film formation, photolithography, etching, bonding, etc., which are semiconductor device manufacturing technologies, for example. Acceleration sensors and capacitive pressure sensors are It can be manufactured using this technique (Japanese Patent Laid-Open No. 2000-230877, Japanese Patent No. 2651492, etc.).
In these sensors and elements, three-dimensional electrical wiring is often required. For example, wiring is formed on both front and back surfaces of an insulating substrate, and the insulating substrate is used to electrically connect these wirings. Through holes are formed in the front and back wirings are electrically coupled through the through holes. In particular, when using micromachine technology, a combination of using glass such as Pyrex (registered trademark) glass as the insulating substrate and using a single crystal silicon substrate as the wiring material is preferably used from the viewpoint of bonding strength and workability. Yes.
[0003]
A conventional method of forming a three-dimensional wiring using micromachine technology will be described with reference to FIG. FIG. 5 shows a method of forming a wiring of an island-shaped silicon substrate partially on the lower surface of the glass substrate and forming a wiring electrically coupled to the island-shaped silicon substrate through a through hole 11 ′ on the upper surface of the glass substrate. It is a typical sectional view shown.
In the three-dimensional wiring of FIG. 5, first, a through hole 11 ′ is formed at a predetermined position of the glass substrate 1 (FIG. 5A). On the other hand, the silicon substrate 2 to be the wiring on the back surface is oxidized to form the oxide film 21 on the entire surface, and then the oxide film 21 on the silicon substrate 2 is patterned by a photolithography technique corresponding to the wiring pattern to open the window 26. Is opened (FIG. 5B). Next, impurities such as boron are diffused from the oxide film window 26 by an impurity diffusion technique to form an impurity diffusion layer 27 on a part of the surface of the silicon substrate 2 (FIG. 5C). Subsequently, the oxide film 21 on the back surface is partially removed corresponding to the wiring pattern, and the entire front surface side is removed (FIG. 5D). The silicon substrate 2 in this state is bonded to the glass substrate 1 on which the through hole 11 ′ is formed by, for example, anodic bonding (FIG. 5E).
[0004]
Next, the silicon substrate 2 is etched by immersing this substrate in EPW (ethylenediamine pyrocatechol aqueous solution) which is an etching solution of silicon. The etching rate of the EPW liquid is about 1 μm / min for non-doped or low impurity concentration single crystal silicon, whereas the etching rate for single crystal silicon diffused to a concentration of 10 ²⁰ cm ³ or more is about 1 μm / min. Since it becomes extremely low, the impurity diffusion layer 27 is hardly etched even when immersed for a long time. Therefore, only the non-doped or low impurity concentration silicon whose surface is exposed is etched, and an island-like silicon is formed immediately below the through hole 11 ′ (FIG. 5F). Thereafter, after the oxide film 21 is removed with a chemical solution such as hydrofluoric acid, the metal film 12 is formed in the through hole 11 ′ by sputtering or vapor deposition, thereby completing the three-dimensional wiring (FIG. 5G).
This method can use semiconductor manufacturing techniques such as oxide film formation, photolithography, etching and impurity diffusion as they are, and can process substrates at the wafer size. Excellent in terms of uniformity.
[0005]
[Problems to be solved by the invention]
The manufacturing method shown in FIG. 5 requires a long time impurity diffusion step at a high temperature, which is a major cause of an increase in manufacturing cost. However, if this impurity diffusion step is omitted, when the silicon substrate 2 by EPW is etched into an island shape in the subsequent step, the silicon inside the through hole 11 ′ is also etched as shown in FIG. This will cause the island-like silicon to penetrate. These cause an increase in wiring resistance and disconnection, making product manufacture impossible. On the other hand, when the silicon substrate 2 is etched, the upper surface of the glass substrate 1 may be protected with a resist or a protective sheet to protect the silicon surface inside the through hole. There is no protective sheet or the like resistant to the liquid, and therefore the impurity diffusion step is indispensable when using micromachine technology.
[0006]
In addition, since EPW contains a toxic chemical solution, there is a problem that special equipment is required. Therefore, tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) solution is used as an etching solution for silicon. Although these are preferable, the difference in etching rate between non-doped or low impurity concentration silicon and high impurity concentration silicon is small, and the impurity diffusion layer 27 cannot play the role of an etch stop layer, and the manufacturing method shown in FIG. 5 is not used.
[0007]
An example of a method for forming a three-dimensional wiring without using a micromachine technique is the method shown in FIG. Here, the silicon substrate 2 is mechanically cut using a dicer or the like (FIG. 7A), and a plurality of silicon pieces 28 to be bonded to the lower portion of the glass substrate 1 are produced (FIG. 7B). The glass substrate 1 in which the through hole 11 ′ is formed at a predetermined position and the plurality of silicon pieces 28 are joined (FIG. 7C), and then the metal film 12 is formed in the through hole 11 ′ portion of the glass substrate 1 to complete. . However, this method is difficult to cut into silicon pieces of complicated shape or minute shape, and it is extremely productive to arrange each silicon piece 28 one by one and perform alignment with high precision. There is a problem that the work is low in performance and the yield is low. As a result, the manufacturing cost increases and miniaturization is difficult.
[0008]
In such a situation, an object of the present invention is to provide a method of manufacturing a three-dimensional wiring that can improve productivity without an impurity diffusion step and can cope with further miniaturization. Furthermore, an object of the present invention is to provide a manufacturing method capable of producing a high-quality capacitive pressure sensor with a high yield.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the three-dimensional wiring manufacturing method proposed by the present invention is such that a non-through hole is formed in an insulating substrate in advance, and after the bonding and patterning with the conductive substrate are completed, the insulating substrate Is immersed in the etching solution to form the non-through hole as a through hole, and finally a conductive film is formed inside the through hole.
That is, a method of manufacturing a three-dimensional wiring in which conductive patterns formed on the front and back surfaces of an insulating substrate are connected through through holes, the step of forming non-through holes with a predetermined depth in the insulating substrate; Bonding the insulating substrate and the conductive substrate, etching the conductive substrate and patterning the conductive substrate into a predetermined shape, etching the insulating substrate until the conductive substrate is exposed, and the non-penetrating The method includes a step of penetrating a hole and a step of forming a conductive film on a side surface and a bottom surface of the through hole.
[0010]
Alternatively, a step of forming a non-through hole with a predetermined depth in the insulating substrate, and the first conductive layer or the first conductive layer of the multilayer substrate including the first conductive layer, the insulating layer, and the second conductive layer, and Etching the insulating layer and patterning the insulating layer into a predetermined shape; joining the insulating substrate and the first conductive layer; removing the second conductive layer; and The insulating substrate is etched until it is exposed to penetrate the non-through hole, and a conductive film is formed on the side and bottom surfaces of the through hole.
[0011]
In this way, when performing a deep etching for separating a conductive substrate such as a silicon substrate into an island shape, a three-dimensional wiring is formed unlike a conventional method in which a through hole is formed in an insulating substrate. The surface of the conductive substrate in this area is not etched because it is protected by the insulating substrate. Therefore, the conventional impurity diffusion process is not required, the production process is shortened and the product cost can be reduced, and the equipment cost of the diffusion furnace and the like can be reduced. Furthermore, as a silicon etching solution, for example, TMAH or KOH aqueous solution can be used instead of toxic EPW, so that the handling becomes simple and there is no need to prepare special equipment. Significant reduction can be achieved.
[0012]
The manufacturing method of the capacitance type pressure sensor according to the present invention includes the manufacturing method of the three-dimensional wiring for forming the capacitance electrode on the insulating substrate and connecting the extraction electrode and connecting the diaphragm electrode and the extraction terminal. It is characterized by being used.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
A first embodiment of the present invention is shown in FIG. FIG. 1 is a schematic cross-sectional view showing an example of a method for manufacturing a three-dimensional wiring.
First, the non-through hole 11 is formed at a predetermined position of the insulating substrate 1 such as glass (FIG. 1A). On the other hand, the conductive substrate 2 made of silicon or the like partially forms the oxide film 21 on the lower surface corresponding to the wiring pattern (FIG. 1B). After the above insulating substrate 1 and the conductive substrate 2 are bonded by, for example, anodic bonding (FIG. 1C), the substrate is immersed in an etching solution having a large etching rate ratio of the conductive substrate to the insulating substrate or the oxide film. To do. For example, when glass is used for the insulating substrate and silicon is used for the conductive substrate, for example, a TMAH or KOH solution is preferably used as the etching solution. In this case, the oxide film 21 and the insulating substrate 1 are hardly etched, only the exposed silicon portion is etched, and the silicon substrate corresponds to the pattern of the oxide film 2 when the etching amount reaches about the thickness of the silicon substrate 1. And is divided into islands (FIG. 1D).
After that, the substrate is immersed in an insulating substrate etching solution (for example, hydrofluoric acid solution) and left until the hole 11 penetrates and the surface of the internal conductive substrate (silicon) is exposed (FIG. 1E). After the cleaning, the conductive film 12 is formed in the through hole 11 ′ to complete the three-dimensional wiring (FIG. 1F).
[0014]
As described above, conventionally, for example, it has been necessary to form a layer for protecting a conductive substrate such as an impurity diffusion layer, which significantly reduces productivity and causes cost increase. According to the manufacturing method of the embodiment, it is not necessary to separately form these protective layers, and as a result, the productivity is greatly improved.
[0015]
A second embodiment of the present invention is shown in FIG. FIG. 2 is a schematic cross-sectional view showing another example of a manufacturing method for three-dimensional wiring.
In this embodiment, a laminated substrate 2 including a first conductive layer 23, an insulating layer 24, and a second conductive layer 25, such as an SOI substrate, is used instead of the conductive substrate (FIG. 2A). A mask having a predetermined pattern is formed on the surface of the first conductive layer 23 with an oxide film 21 (FIG. 2B). After the first conductive layer 23 and then the insulating layer 24 are etched, the mask is removed, and the first conductive layer 23 and the insulating substrate 1 in which the non-through holes 11 are formed are joined (FIG. 2C). Thereafter, the second conductive layer is completely removed by etching (FIG. 2D), and then immersed in the etching solution of the insulating substrate to penetrate the non-through hole 11 to expose the first conductive layer (FIG. 2E). . After the cleaning, the conductive film 12 is formed in the through hole 11 ′ to complete the three-dimensional wiring (FIG. 2F).
[0016]
The conductive substrate is required to have a predetermined thickness in order to ensure mechanical strength. Therefore, in the configuration of the first embodiment, it is difficult to form a fine wiring pattern because the conductive substrate is thick. However, by using the multilayer substrate of this embodiment, the first conductive layer that becomes the wiring is formed. Since the thickness can be reduced, a finer pattern is possible.
In this embodiment, the etching of the first conductive layer 23 and the etching of the insulating layer 24 are performed continuously. However, since the insulating layer 24 can be removed when the through hole 11 ′ is formed, it is not always possible at this time. There is no need to remove it.
[0017]
Next, a third embodiment of the present invention is shown in FIG. In the present embodiment, an example of a method for manufacturing a capacitance-type vacuum sensor using a laminated substrate of an SOI (Silicon on Insulator) substrate as a conductive substrate will be described.
First, the structure and operating principle of a capacitive pressure sensor will be described with reference to FIG. 3L. The sensor of FIG. 3L is attached to the apparatus so that the pressure measurement chamber 6 communicates with the space in the apparatus to be measured.
[0018]
The vacuum chamber (reference pressure chamber) 4 of the sensor is a space sealed in a vacuum state, and the non-evaporable getter 5 functions to absorb the gas remaining inside the vacuum chamber 4 and keep this space at a low pressure at all times. ing. The diaphragm 7 is made of silicon having a thickness of 5 to several tens of μm and a size of several mm to several tens of mm square. If there is a pressure difference between the pressure measured chamber 6 and the vacuum chamber 4, the diaphragm 7 It will be displaced according to the difference. Therefore, the pressure in the pressure measurement chamber 6 can be measured by measuring the electrostatic capacitance between the diaphragm 7 and the capacitive electrode 3 disposed opposite thereto. In addition, an electrical signal related to the capacitance can be taken out from the terminal 12a directly connected to the capacitor electrode 3 and the terminal 12b directly connected to the diaphragm.
[0019]
Next, a process for manufacturing the capacitance type vacuum sensor having this structure will be described. For example, an SOI substrate 2 is prepared in which a single crystal first silicon layer 23 having a thickness of 20 μm, an oxide film layer 24 having a thickness of 1 μm, and a second silicon layer 25 having a thickness of 600 μm are bonded in a laminated structure (FIG. 3A). First, an oxide film 21 is formed on the SOI substrate 2 and patterned into the shape of a capacitor electrode (FIG. 3B). Using the oxide film 21 as a mask, the first silicon layer 23 and then a hydrofluoric acid solution are formed by TMAH or KOH. Then, the oxide film layer 24 is etched (FIG. 3C). On the other hand, a glass substrate (for example, Pyrex (registered trademark) glass) 1 in which the non-through holes 11a and 11b and the getter housing groove 13 are formed is prepared, and this is applied to the first silicon layer 23 of the SOI substrate, for example, anodic bonding method. (FIG. 3D). Next, this substrate is immersed in an etching solution such as TMAH or KOH to remove all the second silicon layer 25 (FIG. 3E). As described above, the glass substrate 1 is completed in which the first silicon layer 23 having a thickness of 20 μm and the oxide film 2 having a thickness of 1 μm are formed immediately below the non-through hole 11.
[0020]
Next, an SOI substrate 2 ′ for forming a diaphragm electrode is prepared. As the SOI substrate, for example, a substrate including a first silicon layer 23 ′ having a thickness of 35 μm, an oxide film layer 24 ′ having a thickness of 1 μm, and a second silicon layer 25 ′ having a thickness of 600 μm is used. After forming the oxide film 21 on this substrate and patterning the oxide film on the first silicon layer 23 ′ (FIG. 3F), a vacuum chamber (reference pressure chamber) groove 4 having a depth of 28 μm is formed. 2) The oxide film 21 on the bottom surface of the silicon layer 25 ′ is patterned to open the window 26 (FIG. 3G).
[0021]
Subsequently, the glass substrate 1 of FIG. 3E and the SOI substrate 2 ′ of FIG. 3G are anodically bonded in a vacuum so that the non-evaporable getter 5 fits in the getter storage groove 13 (FIG. 3H). Thereafter, the substrate is immersed in a TMAH or KOH solution, the second silicon layer 25 ′ is etched to expose the oxide film layer 24 ′, and a groove 6 to be a pressure measurement chamber is formed (FIG. 3I). Here, when immersed in a hydrofluoric acid-based solution, the glass substrate 1 is gradually etched, and the non-penetrating groove 11 penetrates to form through holes (through holes) 11a ′ and 11b ′, and a silicon layer 23 having a thickness of 20 μm inside each of them. Then, the surface of the silicon layer 23 ′ having a thickness of 35 μm is exposed (FIG. 3K). The capacitance type vacuum sensor is completed by forming the metal films 12a and 12b in the through holes 11a ′ and 11b ′.
[0022]
In the sensor of this embodiment, the thickness of the diaphragm 7 is 7 μm, and the distance between the diaphragm 7 and the capacitive electrode 3 is 8 μm. The size and thickness of the diaphragm are appropriately selected according to the pressure region to be measured, but as described above, by using the manufacturing method of this embodiment, finer patterning becomes possible, and various characteristics are obtained. Sensors can be produced stably and with good reproducibility.
[0023]
In this embodiment, the SOI substrate is used as the diaphragm formation substrate. However, a simple single crystal silicon substrate or other conductive substrate may be used, and can be manufactured in the same manner. An example of this sensor is shown in FIG. 4A. Furthermore, in the present invention, for example, a second insulating substrate 8 having a vent 9 and larger than the conductive substrate 2 is joined to the bottom surface of the conductive substrate of the sensor of FIG. 4A (FIG. 4B), It is preferable that an O-ring is applied to a portion outside the conductive substrate on the bottom surface of the insulating substrate 8 and attached to a vacuum apparatus or the like. Thereby, the distortion which the diaphragm receives at the time of sensor attachment is suppressed, and a more accurate pressure measurement is attained. Similarly, the sensor having the structure shown in FIG. 3L preferably has a configuration in which the second insulating substrate is bonded.
[0024]
In the above embodiment, EPW or the like can be used as the silicon etching solution in addition to the TMAH and KOH solutions. Note that anodic bonding is suitably used as a bonding method between the insulating substrate and the conductive substrate.
In addition, the manufacturing method of the three-dimensional wiring of this invention is applied suitably for the various sensors, elements, etc. which have an acceleration sensor and a diaphragm structure other than an electrostatic capacitance type pressure sensor.
[0025]
【The invention's effect】
According to the present invention, a high-temperature and long-time process such as an impurity diffusion step is not required as in the prior art, and it is not necessary to use an EPW etching solution containing a toxic substance, so that the manufacturing process is dramatically simplified. This is very effective in reducing product costs, manufacturing safety, and environmental issues. Further, there is no need to use a manual method apart from micromachine technology, such as mechanically cutting a silicon substrate, arranging the silicon substrate, and bonding the silicon substrate to a glass substrate. In other words, since it is possible to use high-precision photolithographic technology and substrate alignment technology in a lump, product quality and mass productivity can be as high as those of semiconductor products.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing an example of a method for producing a three-dimensional wiring according to the present invention.
FIG. 2 is a schematic cross-sectional view showing another example of the three-dimensional wiring manufacturing method of the present invention.
FIG. 3 is a schematic cross-sectional view showing an example of a method for producing a capacitive pressure sensor of the present invention.
FIG. 4 is a schematic cross-sectional view showing a sensor to which the method for manufacturing a capacitive pressure sensor of the present invention is preferably applied.
FIG. 5 is a schematic cross-sectional view showing an example of a conventional three-dimensional wiring manufacturing method.
6 is a schematic diagram showing a defect of the three-dimensional wiring manufacturing method shown in FIG.
FIG. 7 is a schematic cross-sectional view showing another example of a conventional three-dimensional wiring manufacturing method.
[Explanation of symbols]
1 Insulating substrate (glass substrate),
2 conductive substrate (silicon substrate, SOI substrate),
3 capacitive electrodes,
4 Vacuum chamber (vacuum chamber groove),
5 Non-evaporable getter,
6 Pressure chamber (pressure chamber groove),
7 Diaphragm,
8 Second insulating substrate,
9 Vents,
11 Non-through hole,
11 'through hole (through hole),
12 Conductive film (metal film),
12a Capacitor electrode takeout terminal,
12b Diaphragm electrode takeout terminal,
13 Getter storage groove,
21 oxide film,
23 first conductive layer (first silicon layer),
24 oxide layer,
25 second conductive layer (second silicon layer),
26 Windows,
27 impurity diffusion layer,
28 Silicon pieces.

Claims (6)

Preparing a laminated substrate comprising an insulating substrate and a first conductive layer, an insulating layer, and a second conductive layer;
Forming a non-through hole with a predetermined depth on the first surface of the insulating substrate;
Etching the first conductive layer or the first conductive layer and the insulating layer of the laminated substrate and patterning them into a predetermined shape;
Bonding the second surface of the insulating substrate in which the non-through hole is formed and the first conductive layer after the patterning ;
Removing the second conductive layer after bonding the insulating substrate and the first conductive layer ;
After removing the second conductive layer, etching the insulating substrate until the first conductive layer is exposed, penetrating the non-through hole, and forming the through hole ;
Forming a conductive film on the side and bottom of the through hole;
A method for producing a three-dimensional wiring, comprising: The method for manufacturing a three-dimensional wiring according to claim 1 , wherein the insulating substrate is a glass substrate, and the laminated substrate is an SOI substrate. Capacitor electrodes on the second surface, the takeout lead terminal are formed on the first surface, both the insulating substrate is connected through the first through hole, a vacuum chamber groove in the first surface so as to sandwich the diaphragm electrode, a second A conductive substrate having a pressure measurement chamber groove formed on a surface thereof is bonded so that the capacitor electrode and the diaphragm electrode face each other, and a takeout terminal of the diaphragm electrode is connected to the first surface of the insulating substrate. A method of manufacturing a capacitive pressure sensor formed and connected through a second through hole, comprising:
Providing an insulating substrate and first and second conductive substrates;
Forming first and second non-through holes with a predetermined depth on the first surface of the insulating substrate;
Bonding the second surface of the insulating substrate in which the non-through hole is formed and the first conductive substrate;
Etching the first conductive substrate after bonding the insulating substrate and the first conductive substrate to form the capacitive electrode;
Etching the first surface of the second conductive substrate to form the vacuum chamber groove;
Bonding the second surface of the insulating substrate and the first surface of the second conductive substrate so that the capacitive electrode fits in the vacuum chamber groove;
Etching the second surface of the second conductive substrate after bonding to form the measured chamber groove to form the diaphragm; and
Etching the insulating substrate to form the first and second through holes by etching the insulating substrate after forming the diaphragm; and
Forming a conductive film on the side and bottom surfaces of the formed first and second through holes;
A method for manufacturing a capacitance type pressure sensor, comprising: 4. The method of manufacturing a capacitive pressure sensor according to claim 3 , wherein the insulating substrate is a glass substrate, and the first and second conductive substrates are silicon substrates. A laminate composed of an insulating substrate in which a capacitor electrode is formed on the second surface and a lead-out terminal is formed on the first surface and both are connected through the first through hole, and a first conductive layer, an insulating layer, and a second conductive layer A vacuum chamber groove is formed in the first conductive layer of the substrate, a pressure measurement chamber groove is formed in the second conductive layer, and a diaphragm comprising the first conductive layer between the vacuum chamber groove and the measurement chamber groove a multilayer substrate provided with the electrodes, the capacitor electrodes and the diaphragm electrode is joined so as to face the takeout terminal of the diaphragm electrode is formed on the first surface of the insulating substrate, the second through hole A manufacturing method of a capacitive pressure sensor connected through
A step of preparing an insulating substrate and first and second laminated substrates comprising a first conductive layer, an insulating layer, and a second conductive layer;
Forming first and second non-through holes with a predetermined depth on the first surface of the insulating substrate;
Etching the first conductive layer or the first conductive layer and the insulating layer of the first laminated substrate to pattern them into a predetermined shape;
Bonding the second surface of the insulating substrate in which the non-through hole is formed and the patterned first conductive layer of the first laminated substrate;
Removing the second conductive layer of the first laminated substrate after bonding the insulating substrate and the first conductive layer to form the capacitive electrode;
Etching the first conductive layer of the second laminated substrate to form the vacuum chamber groove;
Bonding the second surface of the insulating substrate and the first conductive layer of the second laminated substrate so that the capacitive electrode fits in the vacuum chamber groove;
Etching the second conductive layer of the second laminated substrate to form the measured chamber groove after bonding;
The diaphragm is formed by etching the insulating layer of the second laminated substrate in the groove to be measured, and the insulating substrate is etched to penetrate the first and second non-through holes. Forming first and second through holes;
Forming a conductive film on side and bottom surfaces of the formed first and second through holes;
A method for manufacturing a capacitance type pressure sensor, comprising: 6. The method of manufacturing a capacitive pressure sensor according to claim 5 , wherein the insulating substrate is a glass substrate, and the first and second laminated substrates are SOI substrates.

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