JP4313073B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, and more specifically, a first well of a first conductivity type, a first well of the first conductivity type, and the first well electrically isolated from the semiconductor substrate. The present invention relates to a method of manufacturing a semiconductor device having a multi-well structure formed by forming a second well of the second conductivity type surrounding the first well.
[0002]
[Prior art]
Forming a first well of a first conductivity type and a second well of a second conductivity type surrounding the first well so as to be electrically insulated and separated from the semiconductor substrate; As a method for manufacturing a semiconductor device having a multi-well structure, there is one disclosed in Patent Document 1 below. Hereinafter, the manufacturing process of the semiconductor device disclosed in Patent Document 1 will be described with reference to FIG. In the following description, the first conductivity type is P-type, and the second conductivity type is N-type.
[0003]
First, as shown in FIG. 7, an element isolation 702 is formed on a P-type silicon substrate 701 using a known technique, and a resist mask 703a is formed as an N-type well formation mask using a photolithography technique ( In FIG. 7A, phosphorus ions are implanted in an ion implantation process to form an N-type well 704, and the resist mask is removed (FIG. 7B). Further, after forming a resist mask 703b as a P-type well formation mask using photolithography technology (FIG. 7C), boron ions are implanted in an ion implantation step to form a P-type well 705, and the resist mask is formed. It is removed (FIG. 7 (d)). After forming the N-type well 704 and the P-type well 705, a resist mask 703c is formed using the buried N-type well as a formation mask by using a photolithography technique (FIG. 7E), and then phosphorus ions are formed in an ion implantation step. Is implanted to form a buried N-type well 706, and the resist mask is removed. In this way, multiple well regions are formed so as to be electrically insulated from the silicon substrate by forming wells having opposite conductivity so as to surround wells of the same conductivity type as the silicon substrate.
[0004]
As described above, after multiple well regions are formed, the oxide film on the surface of the silicon substrate is removed using hydrofluoric acid, and the gate oxide film 707 is formed after exposing the surface of the silicon substrate. After forming the gate oxide film, polysilicon is deposited and patterned by photolithography technique and dry etching technique to form the gate electrode 708. Thereafter, an N-type diffusion layer 709 and a P-type diffusion layer are formed using a known technique (FIG. 7G).
[0005]
[Patent Document 1]
JP-A-11-251449
[0006]
[Problems to be solved by the invention]
In semiconductor devices, it is a well-known fact that improving the reliability of the gate oxide film is an important issue. On the other hand, dielectric breakdown due to a high electric field applied to the gate oxide film and deterioration of the oxide film become problems, so that multiple wells A method of realizing a low voltage operation by forming a region to form a multi-well structure is generally used. However, as described below, in a semiconductor device having a multi-well structure, when oxide film etching is performed to expose the silicon substrate surface, pits are formed on the silicon substrate surface. There was a problem of causing local dielectric breakdown and deterioration of oxide film quality.
[0007]
Problems of the conventional method for manufacturing a semiconductor device will be described with reference to FIG. A first conductivity type first well 802 is formed in the first conductivity type silicon substrate 801, and has a conductivity opposite to the first conductivity type conductivity so as to surround the first well 802. A second well 803 of two conductivity type is formed. After multiple well regions are formed so that the silicon substrate 801 and the first well 802 are electrically isolated from each other, the surface of the silicon substrate before gate oxidation is exposed. A negative charge 804 is charged on the first well 802 in the process before the oxide film wet etching. Here, metal impurities having a higher redox potential than hydrogen typified by Cu are not removed by hydrofluoric acid, and conversely, if metal impurities are present in a hydrofluoric acid solution or in an oxide film, they are adsorbed to the silicon substrate. It is known that it can be explained by a redox reaction. Cu dissolved in hydrofluoric acid solution or oxide film during oxide film etching²⁺The ions 805 are attracted to the charged negative charge 804 and react as shown in the chemical reaction formula of Chemical Formula 1 to form Cu nuclei 806 on the surface of the silicon substrate 801 (FIG. 8A).
[0008]
[Chemical 1]
Cu²⁺+ 2e⁻→ Cu
[0009]
In the case of the semiconductor device having the multi-well structure as described above, the first well 802 is electrically insulated from the silicon substrate 801 by the second well 803, and the negative charge 804 accumulated in the first well 802 is silicon. Since it is not diffused into the substrate 801, it is easy to cause a reduction reaction with metal impurities, and further, the reaction proceeds and Cu 807 is deposited, and at the bottom of Cu 807 by the reaction shown in Chemical Formula 2₂808 is formed (FIG. 8B).
[0010]
[Chemical formula 2]
Si + 2H₂O → SiO₂+ 4H⁺+ 4e⁻
[0011]
This SiO₂Since 808 is etched with hydrofluoric acid, Cu is finally removed to form pits 809 on the silicon substrate (FIG. 8C). After the gate oxide film is formed, the presence of the pits 809 causes dielectric breakdown due to local electric field concentration and deterioration of the oxide film quality. As described above, the gate oxide film quality is critically affected by the oxide film etching in the process before oxidation.
[0012]
The present invention has been made in view of the above-described problems in the prior art, and an object of the present invention is to provide the first conductivity type first well and the first well on the first conductivity type semiconductor substrate. To improve a method for forming a multi-well structure or an oxide film etching method in a semiconductor device having a multi-well structure in which a second well of a second conductivity type is formed so as to be electrically insulated and separated from a semiconductor substrate. Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device that can eliminate the formation of pits on a semiconductor substrate.
[0013]
  In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention includes a first conductive type semiconductor substrate, a first well of the first conductive type, and the first well electrically connected to the semiconductor substrate. A method of manufacturing a semiconductor device having a multi-well structure formed by forming a second well of a second conductivity type having conductivity opposite to the conductivity of the first conductivity type surrounding so as to be insulated and isolated, According to claim 1 in the column of the claims, at least after the step of forming the first well in the semiconductor substrate and the step of wet etching the surface of the semiconductor substrate including the first well, Forming an insulating film on the surface of the first well;ThenForming a gate electrode of a transistor on the insulating film in the first well region;ThenAnd forming the second well in a region surrounding the side and bottom of the first well.
[0014]
  Furthermore, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a surface region of the second well in the semiconductor substrate, as described in claim 2 of the claims. After the step of forming the first well in a region other than the second well in the surface region and the step of wet etching the surface of the semiconductor substrate including the first well, an insulating film is formed on at least the surface of the first well Forming a step;ThenForming a gate electrode of a transistor on the insulating film in the first well region;ThenA buried region of the second well is formed in an inner region of the semiconductor substrate surrounding a bottom of the first well, and the first well is insulated from the semiconductor substrate by the surface region and the buried region of the second well. The second feature is to have a step of surrounding as described above.
[0015]
  According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a buried region of the second well in an inner region of the semiconductor substrate; At least the surface of the first well after the step of forming the first well region on the buried region of the second well of the semiconductor substrate and the step of wet etching the surface of the semiconductor substrate including the first well Forming an insulating film on the first well region, forming a gate electrode of a transistor on the insulating film in the first well region,ThenForming a surface region of the second well in a region other than the first well of the surface region of the semiconductor substrate;ThenA surface region of the second well is formed in a region other than the first well in a surface region of the semiconductor substrate, and the first well is insulated from the semiconductor substrate by the surface region of the second well and the embedded region. A third feature is to have a step of surrounding the substrate.
[0016]
Furthermore, in the method of manufacturing a semiconductor device according to the present invention, as described in claim 4 of the claims, in addition to the above features, the wet etching is performed with a hydrofluoric acid aqueous solution. 4 features.
[0017]
According to any of the first to third features of the method for manufacturing a semiconductor device according to the present invention, the same conductivity type semiconductor substrate and the first well are electrically insulated and separated by the opposite conductivity type second well. Since the process of wet etching the surface of the semiconductor substrate including the first well is performed in the absence of the negative charge on the semiconductor substrate surface as pointed out in the prior art, the formation of pits on the semiconductor substrate is prevented. It can be avoided.
[0018]
In the above description, the surface region is a continuous region from the surface of the substrate (or well) to the inside of the substrate (or well), and the internal region or the embedded region means a region that is not exposed on the substrate surface.
[0019]
  Furthermore, in the method for manufacturing a semiconductor device according to the present invention, as described in claim 5 of the claims, after forming the first well and the second well in the semiconductor substrate, The surface has energy larger than the band gap energy of the semiconductor crystal forming the semiconductor substrate.visible lightWet etching while irradiating, a step of forming an insulating film on at least the surface of the first well, and a step of forming a gate electrode of a transistor on the insulating film in the first well region. Is the fifth feature.
[0020]
Furthermore, in the method of manufacturing a semiconductor device according to the present invention, the semiconductor substrate is a silicon substrate, and the light irradiated in the step of wet etching the surface of the semiconductor substrate is visible light, fluorescent light emission, or 1. A sixth feature is that the light has a wavelength having an energy of 1 eV or more.
[0021]
According to the fifth or sixth feature of the method of manufacturing a semiconductor device according to the present invention, the first well and the first well are formed by the energy of light irradiated during the wet etching process of the surface of the semiconductor substrate including the first well. The negative charges and positive charges generated at the junction interface of the second well cancel the charges charged on the surface of the semiconductor substrate, so that pit formation on the semiconductor substrate as pointed out in the prior art can be avoided.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of a method for manufacturing a semiconductor device according to the present invention (hereinafter referred to as “the present invention method” as appropriate) will be described with reference to the drawings.
[0023]
<First Embodiment>
FIG. 1 shows a manufacturing process in an embodiment of the method of the present invention. First, an element isolation 102 is formed on a P-type silicon substrate (first conductivity type semiconductor substrate) 101 using a known technique. Thereafter, a resist mask 103a is formed as an implantation mask for forming a P-type well using a known photolithography technique (FIG. 1A), and then boron ion implantation is performed using an ion implanter. Then, a P-type well (first conductivity type first well) 104 is formed. Specifically, the first implantation energy is 150 keV and the implantation amount is 5.5 × 10.¹²cm^-2And the second implantation energy is 350 keV and the implantation amount is 4.0 × 10.¹²cm^-2Then, the resist mask 103a is removed. At this stage, the P-type silicon substrate 101 and the P-type well 104 are not electrically insulated and separated.
[0024]
Next, a natural oxide film, a sacrificial oxide film, and the like are removed by etching an oxide film of about 100 to 300 mm with a thermal oxide film using a hydrofluoric acid aqueous solution, and the silicon surface is exposed. Here, since the negative charge 105 charged on the P-type well 104 is diffused to the P-type silicon substrate 101, there is no charge on the surface of the P-type well 104, Cu²⁺Since the ions 106 are not attracted to the surface of the P-type well 104 and no redox reaction occurs, no pits are formed on the P-type silicon substrate 101 (FIG. 1B).
[0025]
After performing oxide film etching by the above-described method, thermal oxidation is performed to form a gate oxide film 107 having a thickness of about 30 to 200 mm, and polysilicon is deposited to a thickness of about 1000 to 3000 mm using a known technique. Patterning is performed using a photolithography technique and a dry etching technique, and a gate electrode 108 is formed on the P-type well 104.
[0026]
Next, after forming a resist mask 103b as an implantation mask for forming an N-type well using photolithography technology (FIG. 1C), phosphorus ions are implanted using an ion implanter to form an N-type well ( The second conductivity type second well) 109 is formed. Specifically, the first implantation energy is 330 keV, and the implantation amount is 2.0 × 10.¹²cm^-2The second implantation energy is 800 keV, and the implantation amount is 5.0 × 10.¹²cm^-2And the third injection energy is 3 MeV and the injection amount is 5.0 × 10¹²cm^-2As an injection. At this stage, the P-type well 104 is completely surrounded by the N-type well 109, and is electrically isolated from the P-type silicon substrate 101. Thereafter, the resist mask 103b is removed and N is removed using a known technique.⁺Diffusion layer 110 and P⁺A transistor is completed by forming the diffusion layer 111 (FIG. 1D).
[0027]
Second Embodiment
FIG. 2 shows a manufacturing process in an embodiment of the method of the present invention. First, element isolation 202 is formed on a P-type silicon substrate (first conductivity type semiconductor substrate) 201 using a known technique. Then, after forming a resist mask 203a as an implantation mask for forming an N-type well using a known photolithography technique (FIG. 2A), phosphorus ions are implanted using an ion implanter. An N-type well (surface region of the second conductivity type second well) 204 is formed. Specifically, the first injection energy is 330 keV, and the injection amount is 2.0 × 10.¹²cm^-2The second implantation energy is 800 keV, and the implantation amount is 5.0 × 10.¹²cm^-2Then, the resist mask 203a is removed (FIG. 2B).
[0028]
Thereafter, after forming a resist mask 203b as an implantation mask for forming a P-type well (FIG. 2C), boron ion implantation is performed using an ion implanter to form a P-type well (first conductivity type first mask). Well) 205 is formed. Specifically, the first injection energy is 150 keV and the injection amount is 5.5 × 10.¹²cm^-2And the second implantation energy is 350 keV and the implantation amount is 4.0 × 10.¹²cm^-2Then, the resist mask 203b is removed. At this stage, the P-type silicon substrate 201 and the P-type well 205 are not electrically insulated and separated.
[0029]
Next, a natural oxide film, a sacrificial oxide film, and the like are removed by etching an oxide film of about 100 to 300 mm with a thermal oxide film using a hydrofluoric acid aqueous solution, and the silicon surface is exposed. Here, since the negative charge 206 charged on the P-type well 205 is diffused to the P-type silicon substrate 201, there is no charge on the surface of the P-type well 205, and Cu²⁺Since the ions 207 are not attracted to the surface of the P-type well 205 and no redox reaction occurs, no pits are formed on the P-type silicon substrate 201 (FIG. 2D).
[0030]
After performing oxide film etching by the above-described method, thermal oxidation is performed to form a gate oxide film 208 having a thickness of about 30 to 200 mm, and polysilicon is deposited to a thickness of about 1000 to 3000 mm using a known technique. Patterning is performed using a photolithography technique and a dry etching technique, and a gate electrode 209 is formed on the P-type well 205. Next, a resist mask 203c is formed as an implantation mask for forming a buried N-type well by using a photolithography technique (FIG. 2E), and then phosphorus ion implantation is performed using an ion implanter, and a buried N-type well is formed. (Embedded region of second conductivity type second well) 210 is formed. Specifically, the injection energy is 3 MeV, and the injection amount is 5.0 × 10.¹²cm^-2As an injection. At this stage, the P-type well 205 is completely surrounded by the N-type well 204 and the buried N-type well 210 and is electrically isolated from the P-type silicon substrate 201. Thereafter, the resist mask 203c is removed, and an N + diffusion layer 211 and a P + diffusion layer 212 are formed using a known technique, thereby completing the transistor (FIG. 2F).
[0031]
<Third Embodiment>
FIG. 3 shows a manufacturing process in an embodiment of the method of the present invention. First, element isolation 302 is formed on a P-type silicon substrate 301 (first conductivity type semiconductor substrate) using a known technique. Thereafter, a resist mask 303a is formed as an implantation mask for forming a buried N-type well by using a known photolithography technique (FIG. 3A), and then phosphorus ion implantation is performed using an ion implanter. Then, a buried N-type well (buried region of the second conductivity type second well) 304 is formed. Specifically, the injection energy is 3 MeV, and the injection amount is 5.0 × 10.¹²cm^-2Then, the resist mask 303a is removed (FIG. 3B).
[0032]
Thereafter, after forming a resist mask 303b as an implantation mask for forming a P-type well (FIG. 3C), boron ion implantation is performed using an ion implanter to form a P-type well (first conductivity type first mask). Well) 305 is formed. Specifically, the first injection energy is 150 keV and the injection amount is 5.5 × 10.¹²cm^-2And the second implantation energy is 350 keV and the implantation amount is 4.0 × 10.¹²cm^-2Then, the resist mask 303b is removed. At this stage, the P-type silicon substrate 301 and the P-type well 305 are not electrically isolated from each other.
[0033]
Next, a natural oxide film, a sacrificial oxide film, and the like are removed by etching an oxide film of about 100 to 300 mm with a thermal oxide film using a hydrofluoric acid aqueous solution, and the silicon surface is exposed. Here, since the negative charge 306 charged on the P-type well 305 is diffused to the P-type silicon substrate 301, there is no charge on the surface of the P-type well 305, and Cu²⁺Since the ions 307 are not attracted to the surface of the P-type well 305 and no redox reaction occurs, no pits are formed on the P-type silicon substrate 301 (FIG. 3D).
[0034]
After performing oxide film etching by the above-described method, thermal oxidation is performed to form a gate oxide film 308 having a thickness of about 30 to 200 mm, and polysilicon is deposited by about 1000 to 3000 mm using a known technique. Patterning is performed using a photolithography technique and a dry etching technique, and a gate electrode 309 is formed on the P-type well 305. Next, after forming a resist mask 303c as an implantation mask for forming an N-type well using photolithography technology (FIG. 3E), phosphorus ions are implanted using an ion implanter to form an N-type well (first A surface region of the second conductivity type second well) 310 is formed. Specifically, the first implantation energy is 330 keV, and the implantation amount is 2.0 × 10.¹²cm^-2The second implantation energy is 800 keV, and the implantation amount is 5.0 × 10.¹²cm^-2As an injection. At this stage, the P-type well 305 is completely surrounded by the N-type well 310 and the buried N-type well 304 and is electrically isolated from the P-type silicon substrate 301. Thereafter, the resist mask 303c is removed, and an N + diffusion layer 311 and a P + diffusion layer 312 are formed using a known technique, thereby completing the transistor (FIG. 3F).
[0035]
<Fourth embodiment>
FIG. 4 shows the essential points of the manufacturing process in an embodiment of the method of the present invention according to claim 5 or 6. First, element isolation 402 is formed on a P-type silicon substrate (first conductivity type semiconductor substrate) 401 by using a known technique. After that, similarly to the conventional technique, a well-known photolithography technique is used to form a resist mask for well implantation, and ion implantation is performed using an ion implanter, so that multiple well regions are formed. Form. Here, the P-type well (first conductivity type first well) 403 is electrically isolated from the P-type silicon substrate 401 by the N-type well (second conductivity type second well) 404 (FIG. 4). ).
[0036]
Next, using hydrofluoric acid, the oxide film is etched by about 100 to 300 mm with a thermal oxide film to remove the natural oxide film, the sacrificial oxide film, and the like, thereby exposing the silicon surface. Here, FIG. 5 is a schematic diagram showing a schematic configuration of an apparatus used for the oxide film etching process. As shown in FIG. 5, the processing apparatus includes a hydrofluoric acid layer 501 filled with hydrofluoric acid, a washing layer 502 filled with ultrapure water, and a dry layer 503 filled with IPA (isopropyl alcohol). A fluorescent lamp 504 is installed above the processing apparatus. Some apparatuses use a buffered hydrofluoric acid layer for the hydrofluoric acid layer, an SC1 cleaning layer, an SC2 cleaning layer, and a drying layer that performs drying by putting a wafer in a cassette and rotating it. The wafers to be processed are put in a cassette 505 and loaded into a loader 506 of the processing apparatus, processed in the order of hydrofluoric acid layer → water washing layer → dry layer, and then unloaded from the unloader 507. Between the time when the wafer is loaded into the loader 506 and the time when the wafer is unloaded from the unloader 507, the fluorescent lamp is always turned on so that the wafer is irradiated with light. By irradiating light 405 by turning on a fluorescent lamp, a negative charge 406 is generated by a photovoltaic effect (known as a power generation principle of a solar cell) at a PN junction between the P-type well 403 and the N-type well 404. A positive charge 407 is generated, and the negative charge 408 on the surface of the P-type well is canceled. Therefore, there is no charge on the surface of the P-type well 403 and Cu²⁺Since the ions 409 are not attracted to the surface of the P-type well 403 and no redox reaction occurs, no pits are formed on the P-type silicon substrate 401 (FIG. 4).
[0037]
Here, the light with which the wafer is irradiated only needs to include light having a wavelength (wavelength of about 1127 nm or less) having an energy of 1.1 eV or more which is the band gap energy of silicon.
[0038]
FIG. 6 is a diagram schematically showing the wafer transfer cassette and the arrangement of the wafers. In general, when a wafer is processed, the wafer 602 is disposed and processed in the wafer transfer cassette 601 so as to ensure a necessary minimum interval. On the other hand, in the oxide film etching process for exposing the silicon surface, the wafer interval is widened so that light from more fluorescent lamps is irradiated in the wafer transfer cassette 603, and the wafer is arranged like the wafer 604. By performing the above, the effect of suppressing the formation of pits by light is further increased.
[0039]
After the oxide film etching is performed by the above-described method, the thickness is about 30 to 200 mm by performing thermal oxidation using a known technique as shown in FIG. Then, a gate oxide film 107 is formed, polysilicon is deposited to a thickness of about 1000 to 3000 mm, and patterning is performed using a photolithography technique and a dry etching technique to form a gate electrode 108 on the P-type well 104. Thereafter, the N + diffusion layer 110 and the P + diffusion layer 111 are formed using a known technique, thereby completing the transistor.
[0040]
【The invention's effect】
As described above in detail, by using the method for manufacturing a semiconductor device according to the present invention, pits can be prevented from being formed on a silicon substrate in a semiconductor device having a multi-well structure.
[Brief description of the drawings]
FIG. 1 is a process diagram showing manufacturing steps of a first embodiment of a method of manufacturing a semiconductor device according to the present invention.
FIG. 2 is a process diagram showing manufacturing steps of a second embodiment of a method for manufacturing a semiconductor device according to the present invention.
FIG. 3 is a process chart showing manufacturing steps of a third embodiment of a method for manufacturing a semiconductor device according to the present invention.
FIG. 4 is a diagram showing the main points of a manufacturing process of a fourth embodiment of a method of manufacturing a semiconductor device according to the present invention.
FIG. 5 is a schematic diagram showing a schematic configuration of an apparatus used for wet etching in a manufacturing process of a fourth embodiment of a semiconductor device manufacturing method according to the present invention;
FIG. 6 is a diagram schematically showing an arrangement of wafer transfer cassettes and wafers used in the manufacturing process of the fourth embodiment of the semiconductor device manufacturing method according to the present invention.
FIG. 7 is a process diagram showing an example of a manufacturing process of a conventional method for manufacturing a semiconductor device.
FIG. 8 is an explanatory view schematically showing a problem of a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
101 P-type silicon substrate (first conductivity type semiconductor substrate)
102 element isolation
103a, 103b resist mask
104 P-type well (first conductivity type first well)
105 negative charge
106 Cu²⁺ion
107 Gate oxide film
108 Gate electrode
109 N-type well (second conductivity type second well)
110 N-type diffusion layer
111 P-type diffusion layer
201 P-type silicon substrate (first conductivity type semiconductor substrate)
202 Element isolation
203a, 203b, 203c resist mask
204 N-type well (surface region of second well of second conductivity type)
205 P-type well (first conductivity type first well)
206 Negative charge
207 Cu²⁺ion
208 Gate oxide film
209 Gate electrode
210 Buried N-type well (buried region of second conductivity type second well)
211 N-type diffusion layer
212 P-type diffusion layer
301 P-type silicon substrate (first conductivity type semiconductor substrate)
302 Element isolation
303a, 303b, 303c resist mask
304 Embedded N-type well (embedded region of second conductivity type second well)
305 P-type well (first conductivity type first well)
306 negative charge
307 Cu²⁺ion
308 Gate oxide film
309 Gate electrode
310 N-type well (surface region of second well of second conductivity type)
311 N-type diffusion layer
312 P-type diffusion layer
401 P-type silicon substrate (first conductivity type semiconductor substrate)
402 Element isolation
403 P-type well (first conductivity type first well)
404 N-type well (second well of second conductivity type)
405 light
406 negative charge
407 plus charge
408 negative charge
409 Cu²⁺ion
501 Hydrofluoric acid layer
502 Washing layer
503 Dry layer
504 Fluorescent light
505 cassette
506 loader
507 unloader
601 and 603 cassettes
602, 604 wafer
701 P-type silicon substrate (first conductivity type semiconductor substrate)
702 element isolation
703a, 703b resist mask
704 N-type well (second well of second conductivity type)
705 P-type well (first conductivity type first well)
706 buried N-type well (second well of second conductivity type)
707 Gate oxide film
708 Gate electrode
709 N-type diffusion layer
801 Silicon substrate (first conductivity type semiconductor substrate)
802 First well
803 Second well
804 negative charge
805 Cu²⁺ion
806 Cu core
807 Cu
808 SiO₂
809 pit

Claims (4)

Forming a first well of a first conductivity type and a second well of a second conductivity type surrounding the first well so as to be electrically insulated and separated from the semiconductor substrate; A method for manufacturing a semiconductor device having a multi-well structure,
Forming the first well in the semiconductor substrate;
Wet etching the surface of the semiconductor substrate including the first well,
After the wet etching step, forming an insulating film on at least the surface of the first well;
Thereafter, forming a gate electrode of a transistor on the insulating film in the first well region;
And a step of forming the second well in a region surrounding the side and bottom of the first well. Forming a first well of a first conductivity type and a second well of a second conductivity type surrounding the first well so as to be electrically insulated and separated from the semiconductor substrate; A method for manufacturing a semiconductor device having a multi-well structure,
Forming a surface region of the second well in the semiconductor substrate;
Forming the first well in a region other than the second well in the surface region of the semiconductor substrate;
Wet etching the surface of the semiconductor substrate including the first well,
After the wet etching step, forming an insulating film on at least the surface of the first well;
Thereafter, forming a gate electrode of a transistor on the insulating film in the first well region;
Thereafter, a buried region of the second well is formed in an inner region of the semiconductor substrate surrounding the bottom of the first well, and the first well is formed by the surface region and the buried region of the second well. And a method of surrounding the substrate so as to be insulated and separated. Forming a first well of a first conductivity type and a second well of a second conductivity type surrounding the first well so as to be electrically insulated and separated from the semiconductor substrate; A method for manufacturing a semiconductor device having a multi-well structure,
Forming a buried region of the second well in an internal region of the semiconductor substrate;
Forming the first well region on the buried region of the second well of the semiconductor substrate;
Wet etching the surface of the semiconductor substrate including the first well,
After the wet etching step, forming an insulating film on at least the surface of the first well;
Thereafter, forming a gate electrode of a transistor on the insulating film in the first well region;
Thereafter, a surface region of the second well is formed in a region other than the first well in a surface region of the semiconductor substrate, and the first well is formed in the semiconductor substrate by the surface region of the second well and the buried region. And a method of surrounding the substrate so as to be insulated and separated.   The method of manufacturing a semiconductor device according to claim 1, wherein the wet etching is performed with a hydrofluoric acid aqueous solution.

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