JP4315580B2 - Printed wiring board and printed wiring board manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed wiring board on which an electronic component such as an IC chip is placed, and particularly relates to a printed wiring board with a built-in capacitor and resistor.
[0002]
[Prior art]
Usually, in the computer, the wiring distance between the power source and the IC chip is long, and the loop inductance of this wiring portion is very large. For this reason, the fluctuation of the IC drive voltage at the time of high-speed operation becomes large, which may cause an IC malfunction. It is also difficult to stabilize the power supply voltage. For this reason, a capacitor is mounted on the surface of the printed wiring board as an auxiliary to power supply.
That is, the loop inductance that causes voltage fluctuation is the wiring length from the power source shown in FIG. 26A to the power source terminal 272P of the IC chip 270 via the power source line in the printed wiring board 300, and the ground terminal of the IC chip 270. It depends on the wiring length from 272E to the power supply through the ground wire in the printed wiring board 300 from the power supply. In addition, the loop inductance can be reduced by narrowing the distance between the power lines and the ground lines, for example, between the wirings through which currents flow in opposite directions.
For this reason, as shown in FIG. 26B, by mounting a chip capacitor 298 on the printed wiring board 300, the inside of the printed wiring board 300 connecting the IC chip 270 and the chip capacitor 292 serving as a power supply source. The loop inductance is reduced by shortening the wiring length between the power line and the grounding wire and reducing the wiring interval.
[0003]
[Problems to be solved by the invention]
However, the magnitude of the voltage drop causing the IC drive voltage fluctuation depends on the frequency. For this reason, as the driving frequency of the IC chip increases, the loop inductance cannot be reduced even if the chip capacitor is mounted on the surface as described above with reference to FIG. It became difficult to keep it down.
[0004]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board capable of reducing loop inductance and a method for manufacturing the printed wiring board.
[0005]
Another object of the present invention is to provide a printed wiring board capable of achieving high integration and a method for manufacturing the printed wiring board.
[0006]
[Means for Solving the Problems]
In the printed wiring board manufacturing method according to the first to sixth aspects, the chip capacitor can be accommodated in the core substrate, and a printed wiring board with reduced loop inductance can be provided. In addition, it becomes possible to accommodate a resistor in the core substrate, and high integration of the printed wiring board can be realized. Furthermore, the wiring distance between the capacitor and the resistor can be shortened.
[0007]
It means a circuit formed by a build-up method in which an interlayer resin insulation layer is provided on a core substrate, and via holes or through holes are provided in the interlayer resin insulation layer to form a conductor circuit as a conductive layer. For them, either a semi-additive method or a full additive method can be used.
[0009]
It means a circuit formed by a build-up method in which an interlayer resin insulation layer is provided on a core substrate, and via holes or through holes are provided in the interlayer resin insulation layer to form a conductor circuit as a conductive layer. For them, either a semi-additive method or a full additive method can be used.
[0010]
It is desirable to fill the voids with resin. By eliminating the gap between the capacitor or resistor and the core substrate, the built-in capacitor or resistor is less likely to behave, and even if stress originating from the capacitor is generated, it is relaxed by the filled resin. be able to. The resin also has an effect of reducing adhesion and migration between the capacitor and the core substrate.
[0011]
According to the eighth to ninth aspects, at least a part is exposed from the covering layer of the chip capacitor and the resistor electrode and is accommodated in the printed wiring board, and the electrode exposed from the covering layer is electrically connected by plating. At this time, it is desirable that the metal exposed from the coating layer has a main component of Cu. The reason is that even if a metal layer is formed on the exposed metal by plating, the connectivity is improved and the connection resistance can be reduced.
[0012]
The metal film of the capacitor electrode is preferably provided with any one of copper, nickel, and a noble metal. This is because a layer of tin, zinc or the like in the built-in capacitor tends to induce migration at the connection portion with the via hole. Therefore, the occurrence of migration can be prevented.
[0013]
According to the tenth aspect, the electrode of the chip capacitor and the resistor is coated with a plating film, accommodated in the printed wiring board, and the electrode provided with the plating film is electrically connected by plating. Since electrical connection is established by plating on the electrode provided with the plating film, adhesion is high, and the connection reliability between the electrode and the via hole can be improved. In addition, the occurrence of migration can be prevented.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state in which the IC chip 90 is mounted on the printed wiring board 10 shown in FIG.
[0015]
As shown in FIG. 7, the printed wiring board 10 includes a chip capacitor 20A and a chip resistor 20B, a core substrate 30 that houses the chip capacitor 20A and the chip resistor 20B, and an interlayer resin insulating layer 40 that constitutes the build-up layers 80A and 80B. , 60. A via hole 46 and a conductor circuit 48 are formed in the interlayer resin insulation layer 40, and a via hole 66 and a conductor circuit 68 are formed in the interlayer resin insulation layer 60.
[0016]
As shown in FIG. 15A, the chip capacitor 20A includes a first electrode 21, a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes. A plurality of first conductive films 24 connected to the first electrode 21 side and a plurality of second conductive films 25 connected to the second electrode 22 side are arranged to face each other. The surface of the first electrode 21 and the second electrode 22 is covered with a coating layer 26. Similarly, the chip resistor 20B includes a first electrode 21 and a second electrode 22 as shown in FIG. 15B, and a coating layer 26 covers the surfaces of the first electrode 21 and the second electrode 22. Has been.
[0017]
As shown in FIG. 8, bumps 76 for connecting to pads 92S1, 92S2, 92P1, and 92P2 of the IC chip 90 are formed in the via holes 66 of the upper buildup layer 80A. On the other hand, in the via hole 66 of the lower buildup layer 80B, bumps 76 for connecting to the pads 96S1, 96S2, 96P1, and 96P2 of the daughter board 94 are disposed. A through hole 36 is formed in the core substrate 30.
[0018]
The signal pad 92S2 of the IC chip 90 is connected to the signal pad 96S2 of the daughter board 94 via the bump 76-conductor circuit 68-via hole 66-through hole 36-via hole 66-bump 76. On the other hand, the signal pad 92S1 of the IC chip 90 is connected to the signal pad 96S1 of the daughter board 94 via the bump 76-via hole 66-through hole 36-via hole 66-bump 76.
[0019]
The power supply pad 92P1 of the IC chip 90 is connected to the first electrode 21 of the chip capacitor 20A via the bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P1 of the daughter board 94 is connected to the first electrode 21 of the chip capacitor 20A via the bump 76-via hole 66-through hole 36-conductor circuit 48-via hole 46.
[0020]
The power supply pad 92P2 of the IC chip 90 is connected to the second electrode 22 of the chip capacitor 20A via the bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P2 of the daughter board 94 is connected to the second electrode 22 of the chip capacitor 20A via the bump 76-via hole 66-through hole 36-conductor circuit 48-via hole 46.
[0021]
In the printed wiring board 10 of the present embodiment, the chip capacitor 20A is disposed immediately below the IC chip 90, so the distance between the IC chip and the capacitor is shortened, and power can be instantaneously supplied to the IC chip side. Become. That is, the loop length that determines the loop inductance can be shortened.
[0022]
Further, a through hole 36 is provided to avoid the chip capacitor 20A. For this reason, it is possible to prevent reflection due to impedance discontinuity due to the high dielectric material generated when the signal is passed through the capacitor and propagation delay due to passage through the high dielectric material.
[0023]
Furthermore, the chip resistor 20B can be accommodated in the core substrate 30, and high integration of the printed wiring board can be realized. And it becomes possible to shorten the wiring distance between a capacitor | condenser and resistance, and can raise the electrical transmission speed of wiring. Further, since the chip capacitor 20A and the chip resistor 20B are accommodated in the thick core substrate 30, the thickness of the printed wiring board can be reduced.
[0024]
Note that a substrate such as ceramic or AIN could not be used for the core substrate. This is because the substrate has poor external formability and cannot accommodate a capacitor, and even if it is filled with resin, voids are generated.
[0025]
Next, a method for manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.
A resin film 40α having a metal film 41 laminated on one side is prepared (FIG. 1A). As the resin film 40α, a thermosetting resin such as epoxy, BT, polyimide, or olefin, or a mixture of a thermosetting resin and a thermoplastic resin can be used. The metal film 41 is pattern-etched to form a predetermined circuit pattern 42 (FIG. 1B). Next, the chip capacitor 20A and the chip resistor 20B are bonded to the circuit pattern 42 on the lower surface of the resin film 40α via an adhesive material 34 such as solder or conductive paste (FIG. 1C).
[0026]
On the other hand, a core substrate laminate 30α having a cavity 31 for accommodating a chip capacitor and a chip resistor is prepared (FIG. 1C). The cavity 31 is formed by bonding or injection molding of counterbore, a prepreg having a through hole and a prepreg having no through hole. As this core substrate laminate 30α, a laminate obtained by laminating a prepreg impregnated with an epoxy resin can be used. In addition to epoxies, those generally used in printed wiring boards such as those containing reinforcing materials such as BT, phenolic resin or glass cloth can be used. It is also possible to use a resin substrate that does not have a core material such as glass cloth. Then, the resin film 40α to which the chip capacitor 20A and the chip resistor 20B are attached, the core substrate resin laminate 30α, and another resin film 40α are laminated and then pressed (FIG. 1D).
[0027]
At this time, the gaps between the capacitor 20, the chip resistor 20B, and the resin film 40α are filled with the resin that oozes from the resin film 40α. Here, when this gap cannot be sufficiently filled, a filler 32α is disposed between the circuit patterns 42 on the resin film 40α side as shown in FIG. In addition, as shown in FIG. 2 (C), it is also possible to place a filler 32α on the capacitor 20A and chip resistor 20B side and fill as shown in FIG. 3 (D). .
[0028]
Thereafter, the core substrate 30 and the interlayer resin insulating layer 40 that accommodate the chip capacitor 20A and the chip resistor 20B are formed by heating and curing (FIG. 3A). In addition, it is preferable to fill the cavity 31 of the core substrate with the resin filler 32 to improve the airtightness. Further, here, the resin film 40α is laminated using a film having no metal layer, but a resin film (RCC) having a metal layer disposed on one side may be used. That is, a double-sided plate, a single-sided plate, a resin plate without a metal film, or a resin film can be used.
[0029]
Next, a via hole made of a non-through hole 43 is formed in the interlayer resin insulation layer 40 on the upper surface side by a CO2 laser, YAG laser, excimer laser, or UV laser (FIG. 3B). If necessary, smear in the via hole may be performed by a gas plasma treatment using oxygen, nitrogen or the like, a dry treatment such as a corona treatment, or a treatment by immersion using an oxidizing agent such as permanganic acid. Subsequently, through holes 33 for through holes are formed in the interlayer insulating layer 40, the core substrate 30 and the interlayer resin insulating layer 40 with a drill or a laser at 50 to 500 μm (FIG. 3C).
[0030]
After providing the palladium catalyst, the core substrate 30 is immersed in the electroless plating solution to deposit the electroless copper plating film 44 uniformly (FIG. 4A). Although electroless plating is used here, a metal layer such as copper or nickel can be formed by sputtering. Sputtering is disadvantageous in terms of cost, but has an advantage that adhesion with the resin layer can be improved. In some cases, the electroless plating film may be formed after the sputtering. This is because, depending on the resin, it is effective for the case where the application of the catalyst is not stable, and the deposition with electroless plating is more stable when formed with an electroless plating film.
[0031]
Thereafter, a photosensitive dry film is attached to the surface of the electroless plating film 44, a mask is placed thereon, exposure and development are performed, and a resist 51 having a predetermined pattern is formed. Then, the core substrate 30 is immersed in the electrolytic plating solution, and an electric current is passed through the electroless plating film 44 to deposit the electrolytic copper plating film 45 (FIG. 4B). After peeling off the resist 50 and the resist 51 with 5% KOH, the electroless plating film 44 under the resist 51 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and a via hole 46 and a conductor are formed in the interlayer resin insulating layer 40. On the other hand, the through hole 36 is formed in the through hole 33 of the core substrate 30 (FIG. 4C).
[0032]
A roughening layer is provided on the surface of the conductor layer of the conductor circuit 48, the via hole 46 and the through hole 36. The roughening layer is applied by an oxidation (blackening) -reduction treatment, an electroless plating film such as an alloy made of Cu-Ni-P, or an etching treatment such as an etching solution made of a cupric complex and an organic acid salt. The roughened layer has Ra (average roughness height) = 0.01 to 5 μm. Particularly desirable is a range of 0.5 to 3 μm. Although the roughened layer is formed here, it is also possible to directly fill the resin and attach the resin film as described later without forming the roughened layer.
[0033]
Subsequently, the resin layer 38 is filled into the through hole 36. The resin layer may be either a non-conductive resin containing a resin such as an epoxy resin as a main component or a conductive resin containing a metal paste such as copper. In this case, what is contained in the thermosetting epoxy resin to match the coefficient of thermal expansion such as silica is filled as a resin filler. After filling the through hole 36 with the resin 38, the resin film 60α is pasted (FIG. 5A). In addition, it is also possible to apply | coat resin instead of sticking a resin film. After the resin film 60α is attached, a via hole 63 having an opening diameter of 20 to 250 μm is formed in the insulating layer 60α by photo and laser and then thermally cured (FIG. 5B). Thereafter, a catalyst is applied to the core substrate and immersed in electroless plating to deposit a 0.9 μm-thick electroless plating film 64 uniformly on the surface of the interlayer resin insulation layer 60, and then a predetermined pattern is resisted 70 (FIG. 5C).
[0034]
It is immersed in an electrolytic plating solution, and an electric current is passed through the electroless plating film 64 to form an electrolytic copper plating film 65 in a portion where the resist 70 is not formed (FIG. 6A). After the resist 70 is peeled and removed, the electroless plating film 64 under the plating resist is dissolved and removed to obtain a conductor circuit 68 and a via hole 66 composed of the electroless plating film 64 and the electrolytic copper plating film 65 (FIG. 6B )).
[0035]
Immerse in chromic acid for 3 minutes to remove the palladium catalyst on the surface. Further, a roughened surface (not shown) is formed on the surfaces of the conductor circuit 68 and the via hole 66 by an etching solution containing a cupric complex and an organic acid, and Sn substitution is performed on the surface.
[0036]
Solder bumps are formed on the printed wiring board described above. After applying a solder resist composition on both sides of the substrate and performing a drying process, a photomask film (not shown) on which a circular pattern (mask pattern) is drawn is placed in close contact, and exposed to ultraviolet rays. Develop. Further, heat treatment is performed to form a solder resist layer (thickness 20 μm) 72 having an opening 72a of a solder pad portion (including a via hole and its land portion) (FIG. 6C).
[0037]
Then, a solder paste is filled in the opening 72a of the solder resist layer 72 (not shown). Thereafter, the solder filled in the opening 72a is reflowed at 200 ° C. to form solder bumps (solder bodies) 76 (see FIG. 7). In order to improve the corrosion resistance, a metal layer such as Ni, Au, Ag, or Pd can be formed on the opening 72a by plating or sputtering.
[0038]
Next, placement of the IC chip on the printed wiring board and attachment to the daughter board will be described with reference to FIG. The IC chip 90 is mounted so that the solder pads 92S1, 92S2, 92P1, and 92P2 of the IC chip 90 correspond to the solder bumps 76 of the completed printed wiring board 10, and the IC chip 90 is attached by performing reflow. Do. Similarly, the printed wiring board 10 is attached to the daughter board 94 by reflowing the pads 96S1, 96S2, 96P1, and 96P2 of the daughter board 94 to the solder bumps 76 of the printed wiring board 10.
[0039]
Next, a printed wiring board according to a first modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board of the first modification is almost the same as that of the first embodiment described above. However, in the printed wiring board of the first modified example, the conductive pins 84 are disposed and formed so as to be connected to the daughter board via the conductive pins 84. In the embodiment described above with reference to FIG. 1A, the resin film 40α having the metal film 41 laminated on one side is used. However, in the first modified example, the resin film having the metal film laminated on both sides is used. The inter-layer resin insulation layer 60 on the IC chip 90 side is manufactured by using it. That is, the circuit pattern 42 is formed by pattern etching the metal film on the upper surface. Further, the opening 42a of the circuit pattern 42 is used as a conformal mask, and a non-through hole 43 is formed by a laser to form a via hole 46.
[0040]
In the first embodiment described above, only the chip capacitor 20A accommodated in the core substrate 30 is provided. However, in the first modified example, large-capacity chip capacitors 86 are mounted on the front surface and the back surface.
[0041]
An IC chip consumes a large amount of power instantaneously and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in this embodiment, the printed circuit board is provided with a chip capacitor 20A for power supply and a chip capacitor 86. The effect of this chip capacitor will be described with reference to FIG.
[0042]
In FIG. 25, the vertical axis represents voltage supplied to the IC chip, and the horizontal axis represents time. Here, an alternate long and two short dashes line C indicates a voltage fluctuation of a printed wiring board that does not include a power supply capacitor. When the power supply capacitor is not provided, the voltage is greatly attenuated. A broken line A indicates voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. Compared with the two-dot chain line C, the voltage does not drop greatly, but the loop length becomes long, so that the rate-determining power supply cannot be sufficiently performed. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board containing the chip capacitor described above with reference to FIG. Although the loop length can be shortened, the voltage fluctuates because a large-capacity chip capacitor cannot be accommodated in the core substrate 30. Here, the solid line E shows the voltage fluctuation of the printed wiring board of the first modified example in which the chip capacitor 20A in the core substrate described above with reference to FIG. 9 and the large-capacity chip capacitor 86 are mounted on the surface. Yes. By providing the chip capacitor 20A in the vicinity of the IC chip and the large-capacity chip capacitor 86, voltage fluctuation is minimized.
[0043]
Next, a printed wiring board according to a second modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board of the second modification is almost the same as that of the first embodiment described above. However, in the printed wiring board of the second modified example, the first electrode 21 and the second electrode 22 of the chip capacitor 20A and the chip resistor 20B are directly connected to the power supply pads 92P1 and 92P2 and the bumps 76 of the IC chip 90. It is connected. In the second modification, the distance between the IC chip and the chip capacitor, and the IC chip and the chip resistor can be further shortened.
[0044]
Next, the configuration of the printed wiring board according to the second embodiment of the present invention will be described with reference to FIG.
The configuration of the printed wiring board of the second embodiment is substantially the same as that of the first embodiment described above. However, the method of accommodating the chip capacitor 20A and the chip resistor 20B in the core substrate 30 is different. That is, in the first embodiment, the first capacitor 21A and the chip resistor 20B are connected to the first and second electrodes by soldering, but in the second embodiment, the first electrode 21 and the second electrode 22 are plated. To form a via hole 46 to establish a connection.
[0045]
First, a chip capacitor used in this embodiment will be described with reference to FIG.
FIG. 15A shows the chip capacitor used in the printed wiring board of the first embodiment. The first electrode and the second electrode 22 of the chip capacitor are formed of a metallized layer formed by firing a metal mainly composed of copper, and the outer covering layer 26 is formed of Sn. The reason is the improvement of rust prevention and solderability. In the second embodiment, as shown in FIG. 15C, the metal layer is exposed from the coating layer 26 on the upper surfaces of the first electrode 21 and the second electrode 22. Further, as shown in FIG. 14, the metal layer is exposed from the covering layer 26 on the top surfaces of the first electrode 21 and the second electrode 22 of the chip resistor 20 </ b> B. For this reason, connectivity with via holes made of plating is enhanced. Further, the connection resistance can be reduced.
[0046]
The manufacturing process of the printed wiring board of 2nd Embodiment is demonstrated with reference to FIGS.
First, a through hole 37 for accommodating a chip capacitor and a chip resistor is formed in a laminated plate 30α obtained by laminating four prepregs 35 impregnated with an epoxy resin, while a laminated plate 30β obtained by laminating two prepregs 35. Is prepared (FIG. 11A). Here, as the prepreg, a material containing a reinforcing material such as BT, a phenol resin, or glass cloth other than epoxy can be used. Next, the laminated plate 30α and the laminated plate 30β are overlapped, and the chip capacitor 20A and the chip resistor 20B from which the coating 26 on the upper surfaces of the first and second electrodes 21 and 22 is removed are accommodated in the through holes 37 ( FIG. 11B). Here, it is preferable that an adhesive 32 is interposed between the through hole 37 and the chip capacitor 20A and the chip resistor 20B.
[0047]
Next, the resin film 40α, the laminated plate 30α that accommodates the chip capacitor 20A and the chip resistor 20B, the laminated plate 30β obtained by laminating two prepregs 35, and the resin film 40α are further laminated (FIG. 11C). . Thereafter, the core substrate 30 and the interlayer resin insulating layer 40 that accommodate the chip capacitor 20A and the chip resistor 20B are formed by pressure bonding and heating to cure (FIG. 11D). It is preferable that the resin filler 32 is filled in the through holes 37 of the core substrate 30 to improve the airtightness.
[0048]
Next, 300 to 500 μm through holes 33 for through holes are drilled in the interlayer resin insulation layer 40, the core substrate, and the interlayer resin insulation layer 40 (FIG. 12A). Then, non-through holes 43 reaching the first electrode 21 and the second electrode 22 of the chip capacitor 20A are formed in the interlayer resin insulating layer 40 on the upper surface side by CO2 laser, YAG laser, excimer laser, or UV laser (FIG. 12 ( B)). Thereafter, desmear processing is performed. Subsequently, after the surface palladium catalyst is applied, the core substrate 30 is immersed in the electroless plating solution, and the electroless copper plating film 44 is uniformly deposited (FIG. 12C). Here, electroless plating is used, but a metal film of copper, nickel, or the like can be formed by sputtering. Sputtering is disadvantageous in terms of cost, but has an advantage of improving adhesion with the resin. A roughened layer can be formed on the surface of the electroless copper plating film 44. The roughened layer has Ra (average roughness height) = 0.01 to 5 μm. Particularly desirable is a range of 0.5 to 3 μm.
[0049]
Then, a photosensitive dry film is attached to the surface of the electroless plating film 44, a mask is placed, exposure and development are performed, and a resist 51 having a predetermined pattern is formed (FIG. 13A). Then, the core substrate 30 is immersed in the electrolytic plating solution, and an electric current is passed through the electroless plating film 44 to deposit the electrolytic copper plating film 45 (FIG. 13B). Then, after removing the resist 51 with 5% KOH, the electroless plating film 44 under the resist 51 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and a via is formed in the non-through hole 43 of the interlayer resin insulating layer 40. Conductive circuits 48 are formed on the surfaces of the holes 46 and the interlayer resin insulation layer 40, and through holes 36 are formed in the through holes 33 of the core substrate 30 (FIG. 13C). Subsequent steps are the same as those in the first embodiment described above with reference to FIGS.
[0050]
Next, a printed wiring board according to a first modification of the second embodiment of the present invention will be described with reference to FIG. The printed wiring board 10 of the first modification is substantially the same as that of the second embodiment described above. However, in the printed wiring board of the first modified example, the chip capacitor 20A and the chip resistor 20B are formed from the first electrode 21 and the second electrode 22 to the coating layer 26 as shown in FIGS. 15D and 15E. After peeling off, a copper plating film 27 is formed.
[0051]
In the first modified example, the electrodes 21 and 22 of the chip capacitor 20A and the chip resistor 20B are coated with a copper plating film 27, and the electrodes 21 and 22 provided with the plating film 27 are electrically connected by via holes 46 made of copper plating. take. For this reason, the adhesiveness of the electrodes 21 and 22 and the via hole 46 is high, and high connection reliability is achieved.
[0052]
Next, a printed wiring board according to a second modification of the second embodiment of the present invention will be described with reference to FIG. The printed wiring board 10 of the second modified example is substantially the same as that of the second embodiment described above. However, in the printed wiring board of the second modified example, the conductive pin 84 is disposed and formed so as to be connected to the daughter board via the conductive pin 84.
[0053]
In the second embodiment described above, only the chip capacitor 20A and the chip resistor 20B accommodated in the core substrate 30 are provided. However, in the second modified example, large-capacity chip capacitors 86 are mounted on the front surface and the back surface. ing. For this reason, as described above with reference to FIG. 25, by providing the chip capacitor 20A immediately below the IC chip and the large-capacity chip capacitor 86, voltage fluctuation can be minimized.
[0054]
Next, the configuration of the printed wiring board according to the third embodiment of the present invention will be described with reference to FIG.
The configuration of the printed wiring board of the third embodiment is substantially the same as that of the second embodiment described above. However, the method of accommodating the chip capacitor 20A and the chip resistor 20B in the core substrate 30 is different. That is, in the second embodiment, the first electrode 21 and the second electrode 22 are connected only from the IC chip side, but in the third embodiment, the first electrode 21 and the second electrode 22 are connected to the IC chip side and the daughter board. Connections are taken from both sides. In this configuration, the external electrodes of the capacitor and the chip resistor have a so-called through-hole function, and the package structure can be simplified, so that it can be used for a high-frequency IC chip.
[0055]
The manufacturing process of the printed wiring board of 3rd Embodiment is demonstrated with reference to FIG.
First, a through hole 37 for accommodating a chip capacitor and a chip resistor is formed in a laminated plate 30α formed by laminating a prepreg impregnated with an epoxy resin (FIG. 18A). Here, as the prepreg, a reinforcing material such as BT, phenol resin or glass cloth is contained in addition to the epoxy. Next, the chip capacitor 20 </ b> A and the chip resistor 20 </ b> B from which the coatings of the surfaces of the first and second electrodes 21 and 22 are peeled are accommodated in the through holes 37 (FIG. 18B). Here, it is preferable that an adhesive 32 is interposed between the through hole 37 and the chip capacitor 20A and the chip resistor 20B.
[0056]
Next, the resin film 40α, the laminated plate 30α that houses the chip capacitor 20A and the chip resistor 20B, and the resin film 40α are laminated (FIG. 18C). Thereafter, the core substrate 30 and the interlayer resin insulation layer 40 that accommodate the chip capacitor 20A and the chip resistor 20B are formed by pressure bonding and heating to cure (FIG. 18D). It is preferable that the resin filler 32 is filled in the through holes 37 of the core substrate 30 to improve the airtightness.
The subsequent steps are the same as those of the second embodiment with reference to FIGS. 12 and 13 and the first embodiment described with reference to FIGS.
[0057]
FIG. 20 shows another example of the printed wiring board according to the third embodiment. As shown in FIG. 20, the first electrode 21 and the second electrode 22 of the chip capacitor 20 </ b> A and the chip resistor 20 </ b> B can be connected to the via hole 46 through an adhesive material 34.
[0058]
Next, a printed wiring board according to a first modification of the third embodiment of the present invention will be described with reference to FIG. The printed wiring board 10 of the first modification is almost the same as that of the third embodiment described above. However, in the printed wiring board of this modified example, the conductive pin 84 is disposed and formed so as to be connected to the daughter board via the conductive pin 84.
[0059]
Further, in the third embodiment described above, only the chip capacitor 20A accommodated in the core substrate 30 is provided. However, in the first modified example, large-capacity chip capacitors 86 are mounted on the front surface and the back surface. For this reason, as described above with reference to FIG. 25, by providing the chip capacitor 20A immediately below the IC chip and the large-capacity chip capacitor 86, voltage fluctuation can be minimized.
[0060]
A printed wiring board according to a second modification of the third embodiment of the present invention will be described with reference to FIG. The printed wiring board 10 of the second modified example is substantially the same as that of the third embodiment described above. However, in the modified printed wiring board, the filled via 46 is formed on the first electrode 21 and the second electrode 22 of the chip capacitor 20 </ b> A, and is connected to the bump 92 of the IC chip 90 via the filled via 66.
[0061]
A printed wiring board according to a third modification of the third embodiment of the present invention will be described with reference to FIG. The printed wiring board 10 of the third modified example is substantially the same as that of the third embodiment described above. However, in the printed wiring board of this modified example, a filled via 46 is formed on the first electrode 21 and the second electrode 22 of the chip capacitor 20A and the chip resistor 20B, and the IC is connected via the filled via 66 formed immediately above the filled via 46. The bumps 92P1 and 92P2 of the chip 90 are connected. In the third modified example, the distance between the IC chip, the chip capacitor, and the chip resistor can be further reduced.
[0062]
A printed wiring board according to a fourth modification of the third embodiment of the present invention will be described with reference to FIG. The printed wiring board 10 of the fourth modified example is substantially the same as that of the third embodiment described above. However, in this modified printed wiring board, the pad on the IC chip 90 side and the pad 96 on the daughter board 94 side are connected via the chip capacitor 20A, the first electrode 21 and the first electrode 22 of the chip resistor 20B. Yes.
[0063]
In the above-described embodiment, one chip capacitor 20A and chip resistor 20B are accommodated in one cavity or through-hole, but a plurality of them can be accommodated. Thereby, higher integration can be achieved.
[0064]
【The invention's effect】
With the structure of the present invention, the electrical characteristics due to inductance are not deteriorated.
In addition, since the resin is filled between the core substrate and the capacitor, even if stress caused by the capacitor or the like is generated, the stress is alleviated and no migration occurs. Therefore, there is no influence of peeling or dissolution on the connection portion between the capacitor electrode and the via hole.
Therefore, the desired performance can be maintained even if the reliability test is performed. Also, migration can be prevented when the capacitor electrode is covered with copper.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a printed wiring board according to a first embodiment of the present invention.
FIG. 2 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 3 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 4 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 5 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 6 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view of the printed wiring board according to the first embodiment.
FIG. 8 is a cross-sectional view of the printed wiring board according to the first embodiment.
FIG. 9 is a cross-sectional view of a printed wiring board according to a first modification of the first embodiment.
FIG. 10 is a cross-sectional view of a printed wiring board according to a second modification of the first embodiment.
FIG. 11 is a manufacturing process diagram of the printed wiring board according to the second embodiment of the present invention.
FIG. 12 is a manufacturing process diagram of the printed wiring board according to the second embodiment of the present invention.
FIG. 13 is a manufacturing process diagram of the printed wiring board according to the second embodiment of the present invention.
FIG. 14 is a cross-sectional view of a printed wiring board according to a second embodiment of the present invention.
15 (A), (B), (C), (D), and (E) are cross-sectional views of a chip capacitor and a chip resistor.
FIG. 16 is a cross-sectional view of a printed wiring board according to a first modification of the second embodiment.
FIG. 17 is a cross-sectional view of a printed wiring board according to a second modification of the second embodiment.
FIG. 18 is a manufacturing process diagram of the printed wiring board according to the third embodiment of the present invention.
FIG. 19 is a cross-sectional view of a printed wiring board according to a third embodiment of the present invention.
FIG. 20 is a cross-sectional view of a printed wiring board according to a third embodiment of the present invention.
FIG. 21 is a cross-sectional view of a printed wiring board according to a first modification of the third embodiment of the present invention.
FIG. 22 is a cross-sectional view of a printed wiring board according to a second modification of the third embodiment of the present invention.
FIG. 23 is a cross-sectional view of a printed wiring board according to a third modification of the third embodiment of the present invention.
FIG. 24 is a cross-sectional view of a printed wiring board according to a fourth modification of the third embodiment of the present invention.
FIG. 25 is a graph showing changes in voltage supplied to an IC chip and time.
FIGS. 26A and 26B are explanatory diagrams of loop inductance of a printed wiring board according to the related art.
[Explanation of symbols]
10 Printed wiring board
20A chip capacitor
20B Chip resistance
21 First electrode
22 Second electrode
27 Copper plating film
30 core substrate
31 cavities
33 through holes
36 Through hole
40 Interlayer resin insulation layer
42 Circuit pattern
43 Non-through hole
46 Bahia Hall
60 Interlayer resin insulation layer
66 Bahia Hall
68 Conductor circuit
84 Conductive pin
90 IC chip
94 Daughter Board

Claims (10)

A method for producing a printed wiring board comprising at least the following steps (a) to (c):
(A) a step of connecting a capacitor electrode and a resistor electrode to the circuit pattern via an adhesive material on a resin plate having a circuit pattern formed on one side or both sides; and (b) the capacitor and the resistor are connected to the resin plate. A step of forming a core substrate by attaching a resin substrate in which a cavity to be accommodated is formed (c) A via hole is formed by providing an opening to the circuit pattern connected to the capacitor and the resistor electrode in the resin plate. Process.   2. The method according to claim 1, wherein before and after the step (c), a step of forming a through hole in the core substrate formed by attaching the resin substrate to the resin plate is used as a through hole. Manufacturing method of printed wiring board. A method for producing a printed wiring board comprising at least the following steps (a) to (f):
(A) A step of forming a capacitor and a resistor accommodating through hole in a resin material containing a resin as a core material (b) A resin material is pasted on the resin material in which the through hole is formed, and the capacitor and the resistor A step of forming a core substrate having a receiving portion; a step of receiving a capacitor and a resistor on the core substrate; a step of attaching a resin film on both sides of the core substrate; and a step of forming a resin film on the resin film. A step of forming a via hole by providing an opening to the resistance electrode (f) A step of forming a through hole in the core substrate to form a through hole.   The method for manufacturing a printed wiring board according to claim 3, wherein the resin material is a prepreg impregnated with a reinforcing material. A method for producing a printed wiring board comprising at least the following steps (a) to (f):
(A) Step of forming capacitor and resistance housing hole in core substrate (b) Step of housing capacitor and resistor in core substrate (c) Affixing resin material to core substrate to form core substrate Step (d) Forming a via hole in the resin film on the surface side of the core substrate by providing an opening to the capacitor and the resistor electrode (f) Forming a through hole in the core substrate to form a through hole Process.   The method for manufacturing a printed wiring board according to claim 5, wherein the resin material is a prepreg impregnated with a reinforcing material.   6. The method for manufacturing a printed wiring board according to claim 3, wherein the through hole serving as the through hole is formed avoiding the capacitor. A printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
A core substrate in which another resin material is attached to a resin material having a through-hole to form a capacitor and a resistance accommodating portion;
A capacitor and a resistor housed in the capacitor and resistor housing portion of the core substrate;
A resin film attached to the surface of the core substrate,
The capacitor and the electrode of the resistor are covered with a coating layer,
The electrode exposed from the coating layer in the capacitor and the resistor by the via hole formed in the resin film is electrically connected by plating,
A printed wiring board, wherein both surfaces of the core substrate are electrically connected by through holes formed in the core substrate.   The printed wiring board according to claim 8, wherein the electrode exposed from the chip capacitor and the resistor is a metal whose main component is Cu. A printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
A core substrate in which another resin material is attached to a resin material having a through-hole to form a capacitor and a resistance accommodating portion;
A capacitor and a resistor housed in the capacitor and resistor housing portion of the core substrate;
A resin film attached to the surface of the core substrate,
The capacitor and the electrode of the resistor are covered with a plating film,
The capacitor and the electrode of the resistor are electrically connected by plating via holes formed in the resin film,
A printed wiring board, wherein both surfaces of the core substrate are electrically connected by through holes formed in the core substrate.

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