JP4323738B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test of a write mask function in a semiconductor memory device, particularly a memory having a data write mask function, and more particularly to a test of a built-in memory incorporated in an LSI.
[0002]
[Prior art]
In recent years, the scale of LSIs and the complexity of built-in functions are remarkable, and the speed of processing and the amount of memory built in LSIs are increasing regardless of the type. As the processing speed increases, the memory capacity and the number of input / output terminals continue to increase. At the same time, the importance, technical difficulty, test circuit and test time of the test relating to the operation of the LSI increase. As the number of input / output terminals increases, it is necessary to write while partially masking the input / output terminals as LSI processing. On the other hand, in the memory test, means such as DMA (Direct Memory Access) are used. Then, the number of input / output terminals is reduced, and the test is performed by decoding the reduced input / output by the address.
[0003]
[Problems to be solved by the invention]
Therefore, when performing a write mask function test using a memory test (DMA), the mask function address is prepared simultaneously with the increase in the number of address terminals corresponding to the decrease in the number of input / output terminals. The increase in number cannot be ignored. Further, the test in the actual use state cannot be sufficiently performed, and the test time is increased.
[0004]
The present invention has been made in view of such problems, and its purpose is to shorten the test time without increasing the number of terminals when testing the write mask function using a memory test (DMA). A semiconductor memory device is provided.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor memory device according to the present invention has a mask function for masking write data using a mask address signal as an input, and the number of data input / output terminals and the number of address input terminals can be varied in a test mode. to a semiconductor memory device, the mask address input pin of the semiconductor memory device, in response to a decrease in the data input-output terminal in the test mode of the address input terminals provided to decode the data input and output terminal wherein the increase in a same at least partially.
[0006]
According to this configuration, since the mask address for masking the write data becomes the address in the test mode as it is, the write operation having the mask function in the actual use state becomes the write operation in the test mode as it is. There is no need to prepare another write mask function test in the actual use state, and it is not necessary to increase the address input for that purpose.
[0007]
The semiconductor memory device according to the present invention includes a mask address signal input in a test mode and an address input terminal that the semiconductor memory device already has in order to write data from a selected data input terminal to a memory cell array during data writing. A write selection signal generation circuit for generating a write selection signal based on a normal address signal from the output circuit, and an output circuit for outputting data to the outside from an output terminal selected by the mask address signal and the normal address signal when reading data It is preferable to provide.
[0008]
According to this configuration, the address at the time of writing and the address at the time of reading can be matched, and the number of input / output terminals in the memory test can be reduced.
[0009]
In addition, the semiconductor memory device according to the present invention has an input in the test mode so that the mask address input terminal is the address input terminal in the test mode provided corresponding to the decrease in the data input / output terminals in the test mode. Instead of all mask address signals to be generated, a mask address decode signal generated by decoding a necessary number of bits of the mask address signal is selected based on the first test mode activation signal, and is used as a column address. It is preferable to provide a first mask address signal decoding circuit for outputting.
[0010]
According to this configuration, when a write mask address signal input from the outside is used as it is as an address input signal in a memory test, the mask address signal in the actual use state is not already decoded, and at the time of writing When the signal is used to specify a mask, there is no difference between the address at the time of reading in the memory test and the address at the time of writing, and when the number of mask addresses in actual use is large, the effect of reducing the number of mask addresses is particularly effective. is there.
[0011]
In addition, the semiconductor memory device according to the present invention is input in the test mode so that the mask address input terminal is an address input terminal in the test mode provided corresponding to the decrease in the data input / output terminals in the test mode. In place of all mask address signals, a mask address decode signal generated by decoding a required number of bits of the mask address signal is converted into a first test mode activation signal, an externally or internally generated command signal, It is preferable to include a second mask address signal decoding circuit that selects and outputs as a column address based on the second test mode activation signal generated by.
[0012]
According to this configuration, it is possible to select and use all input mask address signals and mask address decode signals according to the purpose of the memory test.
[0013]
Further, in the semiconductor device according to the present invention, it is preferable that all the mask address signals in the test mode are activated through the write selection signal generation circuit, and the data writing to the memory cell array is performed collectively. The second mask address signal decoding circuit preferably has a batch data writing means.
[0014]
According to this configuration, a write operation similar to that in the actual use state can be performed, and a high-speed write operation can be performed in the test mode particularly in a large-capacity memory.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention. In order to simplify the explanation and maintain the concreteness, the actual use state of the memory device and the configuration at the time of the test are illustrated as shown in FIG.
[0016]
In FIG. 1, 1 is a memory cell array, 2 is an input register, 3 is a row decoder, 4 is a column decoder, 5 is a sense amplifier, 6 is a multiplexer, 7 is an output register, and 8 is a clock generator.
[0017]
In actual use, DIN [0-127] is 128-bit input data, DOUT [0-127] is 128-bit output data, and DQM [0-7] is 16-bit input data DIN [0-127. ] Of the 8-bit mask address signal and the 16-bit address signal A [0-15], the 12-bit A [0-11] is the row address signal, and the 4-bit A [12-15] is the column. This is an address signal.
[0018]
On the other hand, in the test mode, PDIN [0-1] is 2-bit input data, PDOUT [0-1] is 2-bit output data, PDQM [0-7] is 8-bit mask address signal, of 20 bits of the address signal PA [0- 19], 12-bit PA [0-11] is a row address signal, an 8-bit PA [12-19] a column address signal.
[0019]
Here, since the input data PDIN [0-1] and the output data PDOUT [0-1] are 2 bits each in the test mode, the input can be decoded with DQM [0-7] in the actual use state. The data DIN [0-127] and DOUT [0-127] have 16 bits, whereas the column address signal PA [12-19] is increased by 4 bits to enable decoding.
[0020]
FIG. 2 is a circuit diagram showing a configuration of data input circuit 21 in input register 2 in the semiconductor memory device of FIG.
[0021]
The data input DIN [0-127], which is 128 bits in the actual use state, becomes the 2-bit data input PDIN [0-1] in the test mode, and the number of data inputs is reduced, so that the DIN [0] shown in FIG. −63] is input as PDIN [0] when the test mode activation signal PTEST is at a logic high level. Therefore, the same data as PDIN [0] is input as input data DIN [0-63], and the same data as PDIN [1] is input as input data DIN [64-127]. . When the test mode activation signal PTEST is at a logic high level, as shown in FIG. 3, a column address signal PA [16-19] input to the address input circuit 22 as described later and a mask input as described later. The position in the memory cell array 1 is selected by the mask address signal PDQM [0-7] input to the circuit 23 and supplied to the memory cell array 1. Further, the position of data from the memory cell array is selected by the same column address signal PA [16-19] and mask address signal PDQM [0-7], and is output as output data outside the memory.
[0022]
FIG. 3 is a circuit diagram showing configurations of address input circuit 22 and mask address signal input circuit 23 in input register 2 in the semiconductor memory device of FIG. In FIG. 3, when the test mode activation signal PTEST is at a logic high level, the mask address signal DQM [0-7] is prevented from transitioning to the inside by the NAND circuit 230, and the PDQM [0] by the NAND circuit 231. −7] is supplied to the inside. Therefore, the mask address signal PDQM [0-7] is supplied as the internal mask address signal IDQM [0-7] inside the memory device. The internal mask address signal IDQM [0-7] is used as a signal for selecting the input data DIN [0-127] and the output data DOUT [0-127]. The column address signal PA [12-19] is similarly supplied as the internal column address signal IA [12-19]. However, in order to select 16-bit data, the column address signal PA [12-19] is used in the test mode. Only the signal used is supplied to the corresponding terminal.
[0023]
FIG. 4 is a circuit diagram showing a configuration of output circuit 71 in output register 7 in the semiconductor memory device of FIG.
[0024]
In FIG. 4, the output data DOUT [0-63] in the actual use state includes the internal mask address signal IDQM [0-7] shown in FIG. 3 when the test mode activation signal PTEST is at the logic high level, The address decode circuit 10 shown in FIG. 7 and described later selects and outputs the internal column address signal IAD [0-15] obtained by decoding the internal column address signal IA [16-19] shown in FIG. DO [0-63] is data read out in the memory. When test mode activation signal PTEST, internal mask address signal IDQM [0], and internal column address decode signal IAD [0] are at a logic high level, read data DO [0] in the test mode is output circuit portion 710. The output impedance of the output circuit unit 711 whose output terminal is commonly connected to the output circuit unit 710 is in a high impedance state. Similarly, when the test mode activation signal PTEST, the internal mask address signal IDQM [7], and the internal column address decode signal IAD [15] are at the logic high level, the read data DO [63] is output from the output circuit unit 711. The output impedance of the output circuit portion 710 that is output and whose output terminal is commonly connected to the output circuit portion 711 is in a high impedance state, and can be selected without newly inputting an address.
[0025]
FIG. 5 is a circuit diagram showing a configuration of write selection signal generation circuit 41 in column decoder 4 in the semiconductor memory device of FIG. In FIG. 5, the write selection signal generation circuit 41 calculates the logical product of the internal column address decode signal IAD [0-15] and the internal mask address signal IDQM [0-7], thereby writing the write selection signal Y [0. -127]. The write selection signal generation circuit 41 obtains the write selection signal Y [0-127] necessary for selecting the input data DIN [0-127] by the internal mask address signal IDQM [0-7]. When the internal mask address signal IDQM [0] is at a logic high level, one of the internal column address decode signals IAD [0-15] is at a logic high level, thereby causing the input data DIN [0-7]. The selected data is written into the memory cell array 1.
[0026]
FIG. 6 is a circuit diagram showing a configuration of address decode signal generation circuit 42 in column decoder 4 in the semiconductor memory device of FIG. In FIG. 6, from an internal column address signal IA [16-19], an inverted internal column address signal IA [16-19] X, which is an inverted signal of each, is generated by an inverter circuit 420. An internal column address signal IA [16-19] and an inverted internal column address signal IA [16-19] X are input to the NAND circuit 421 provided for decoding in accordance with a combination as a selection signal, and decoding is performed. Internal column address decode signal IAD [0-15] is generated. The internal column address decode signal IAD [0-15] is input to the output circuit 71 shown in FIG. 4, functions as a selection signal, and the selected data among the read data DO [0-127] is output data (DOUT ) Is output outside the memory. The internal column address decode signal IAD [0-15] is input to the write selection signal generation circuit 41 shown in FIG. 5, functions as a selection signal, and the selected data among the input data DIN [0-127] is It is written in the memory cell array 1.
[0027]
FIG. 7 is a circuit diagram showing a configuration of mask address signal decoding circuit 10 added to the semiconductor memory device of FIG. Depending on the number of mask bits in actual use and the number of built-in input data lines and output data lines, it is necessary to reduce the number of mask address signal lines due to restrictions on equipment such as a memory tester. . Therefore, as shown in FIG. 7, it is necessary to decode a necessary number of internal mask address signals IDQM and supply them to the above-described write selection signal generation circuit 41 in the memory device.
[0028]
7 includes an internal mask obtained by inverting a necessary number of internal mask address signals IDQM [0-7] from the mask input circuit 23, for example, a 3-bit internal mask address signal IDQM [0-2]. An address signal IDQM [0-2] X is generated. By inputting the inverted internal mask address signal IDQM [0-2] X and the internal mask address signal IDQM [0-2] in a predetermined combination to the NAND circuit 101, and using the output signal of the NAND circuit as a selection signal, An 8-bit internal mask decode signal IDQMD [0-7] can be generated within the memory, and when the test mode activation signal PTEST is at a logic high level, the internal mask decode signal IDQMD [0-7] is internally generated. It becomes possible to supply to. When test mode activation signal PTEST is at a logic low level, internal mask address signal IDQM [0-7] is supplied to the inside as it is as a signal having the same phase.
[0029]
FIG. 8 is a circuit diagram showing a modification of the mask address signal decoding circuit of FIG. 8 differs from FIG. 7 in that a test mode activation signal PTEST 2 is generated by a test mode activation signal PTEST and an externally or internally generated command signal and supplied to the mask address signal decoding circuit 11. In the point. When test mode activation signal PTEST2 is at a logic low level, internal mask address signal IDQM [0-7] is supplied as it is inside the memory, and when test mode activation signal PTEST2 is at a logic high level, an internal mask address signal is supplied. A signal obtained by decoding IDQM [0-2] is supplied into the memory as internal mask decode signal IDQMD [0-7]. In the actual use state, the test mode activation signal PTEST is selected to the logic low level, and the test mode activation signal PTEST2 is selected to the logic high level.
[0030]
FIG. 9 is a circuit diagram showing a further modification of the DQM signal decoding circuit of FIG. 9 differs from FIG. 7 in that the test mode activation signal PTEST2 is generated from the test mode activation signal PTEST by an external or internal command signal and supplied to the mask address signal decoding circuit 11. The final input 2-input NAND circuit that outputs the internal mask decode signal IDQMD [0-7] is a 3-input NAND circuit, and the signal AWT is supplied to one input terminal of the 3-input NAND circuit.
[0031]
When the signal AWT is set to the logic low level, all IDQMD [0-7] are set to the logic high level in the active state. On the other hand, when signal AWT is at a logic high level and test mode activation signal PTEST2 is at a logic high level, a signal obtained by decoding internal mask address signal IDQM [0-2] is an internal mask decode signal IDQMD. [0-7] is supplied into the memory. As a result, by setting the signal AWT to the logic low level, it becomes possible to perform a write operation similar to that in the actual use state, and it becomes possible to perform a high-speed write operation in the test mode particularly in a large-capacity memory. .
[0032]
【The invention's effect】
As described above, according to the present invention, when the write mask function test is performed using the memory test (DMA), the number of terminals exceeds the increase in the number of address terminals corresponding to the decrease in the number of input / output terminals. A test in actual use of the mask function can be sufficiently performed without causing an increase. In addition, writing in a form close to the actual use state can improve the quality level and shorten the test time.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a configuration of a data input circuit 21 in an input register 2 in the semiconductor memory device of FIG. 3 is a circuit diagram showing configurations of an address input circuit 22 and a mask address signal input circuit 23 in the input register 2 in the semiconductor memory device of FIG. 1. FIG. 4 is an output circuit 71 in the output register 7 in the semiconductor memory device of FIG. FIG. 5 is a circuit diagram showing a configuration of a write selection signal generating circuit 41 in the column decoder 4 in the semiconductor memory device of FIG. 1. FIG. 6 is a circuit diagram of the column decoder 4 in the semiconductor memory device of FIG. FIG. 7 is a circuit diagram showing a configuration of an address decode signal generation circuit 42. FIG. 7 shows a configuration of a mask address signal decode circuit added to the semiconductor memory device of FIG. FIG. 8 is a circuit diagram showing a modification of the mask address signal decoding circuit in FIG. 7. FIG. 9 is a circuit diagram showing a further modification of the mask address signal decoding circuit in FIG.
DESCRIPTION OF SYMBOLS 1 Memory cell array 2 Input register 21 Data input circuit 22 Address input circuit 23 Mask address signal input circuit 3 Row decoder 4 Column decoder 41 Write selection signal generation circuit 42 Address decode circuit 5 Sense amplifier 6 Multiplexer 7 Output register 71 Output circuit 8 Clock generator 10, 11, 12 Mask address signal decoding circuit

Claims (6)

A semiconductor memory device having a mask function for masking write data using a mask address signal as an input, and varying the number of data input / output terminals and the number of address input terminals in a test mode,
Mask address input terminals of said semiconductor memory device, and at least part of in response to a decrease in the data input-output terminal in the test mode increment of the address input terminals provided to decode the data input and output terminal the semiconductor memory device which is a same. The semiconductor memory device
At the time of data writing, in order to write data from the selected data input terminal to the memory cell array, the mask address signal input in the test mode and the normal address signal from the address input terminal that the semiconductor memory device already has A write selection signal generating circuit for generating a write selection signal based on
2. The semiconductor memory device according to claim 1, further comprising an output circuit that outputs data to the outside from an output terminal selected by the mask address signal and the normal address signal when reading data. The semiconductor memory device
In order to make the mask address input terminal the address input terminal in the test mode provided corresponding to the decrease in the data input / output terminals in the test mode, all the mask address signals inputted in the test mode Instead, the mask address decode signal generated by decoding the required number of bits of the mask address signal is selected based on the first test mode activation signal, and is output as the column address. 2. The semiconductor memory device according to claim 1, further comprising a signal decoding circuit. The semiconductor memory device
In order to make the mask address input terminal the address input terminal in the test mode provided corresponding to the decrease in the data input / output terminals in the test mode, all the mask address signals inputted in the test mode Instead, a mask address decode signal generated by decoding a required number of bits of the mask address signal is generated by a first test mode activation signal and an externally or internally generated command signal. 2. The semiconductor memory device according to claim 1, further comprising a second mask address signal decoding circuit which selects and outputs as a column address based on the test mode activation signal.   3. The semiconductor memory device according to claim 2, wherein all the mask address signals in the test mode are activated through the write selection signal generation circuit, and data writing to the memory cell array is performed at once. .   4. The second mask address signal decoding circuit includes means for collectively writing data into the memory cell array with all the mask address signals in a test mode in an active state. Semiconductor memory device.

Images