JP4327701B2 - Laser voltage probe measuring element and potential waveform measuring method inside semiconductor integrated circuit using the same - Google Patents

Description

  The present invention relates to a method and an element for measuring a potential waveform inside a semiconductor integrated circuit using a laser voltage probe, and more particularly to a method and an element suitable for improving the observability of an element structure for measuring a laser voltage probe. About.

  As a method for detecting an electric field in an active region in a semiconductor integrated circuit, the description in Patent Document 1 is referred to. FIG. 14 is a diagram for explaining the method described in Patent Document 1. In FIG. As shown in FIG. 14, the function of focusing the laser beam 701 near the PN junction 702 such as the drain of the MOS transistor and the intensity of the laser beam reflected from the oxide film interface 703 and the metal 704 behind the PN junction 702 are increased. A function of measuring with the detector 705 is provided. When the laser beam 701 passes through the PN junction 702, the wavelength of the light absorption edge of the semiconductor or the insulator is shifted to the longer wavelength side by applying a strong electric field (Franz-Keldysh effect). It is partially absorbed by the visible effect), and its light absorption rate becomes a magnitude corresponding to the electric field strength of the PN junction 702. Therefore, it is possible to detect a change in electric field strength at the PN junction 702 from a change in reflected light intensity measured by the detector 705.

  When laser irradiation is performed on the drain of the transistor, the electric field strength of the PN junction depends on the drain potential, so that LVP (Laser Voltage Probing) measurement for measuring the drain potential of the transistor can be performed by the above method. For this reason, the measurement method is useful for timing verification and failure analysis of a digital integrated circuit. Further, since laser irradiation is performed from the back surface of the chip, it is possible to analyze even a flip chip, which is difficult to analyze using a conventional EB (Electron Beam) apparatus, and this can be said to be extremely effective.

JP-T-2002-522770 Publication (FIG. 4)

  However, the above-described conventional method has a problem that observation becomes difficult due to the reduction in the size of the circuit element. For example, in the method described in Patent Document 1, it has been reported that when laser irradiation is performed on silicon, the change in light absorption rate is the largest when the wavelength of laser light is 1065 nm at room temperature.

  This is because when the energy of photons in the laser light is close to the band gap energy of silicon, the change in the light absorptance becomes large. In other words, when LVP measurement is performed on a silicon integrated circuit, it is necessary to use an infrared laser having a wavelength of about 1000 nm.

  Accordingly, the focused spot diameter of the laser beam is at least about several hundred nm due to the influence of the diffraction limit.

  On the other hand, in the case of a 90 nm technology node semiconductor integrated circuit, the minimum size transistor is about several hundred nm, which is approximately the same size as described above. That is, if the element size is further reduced in the future, the laser spot diameter is larger than the element size, and it may be difficult to selectively perform laser irradiation on only one transistor. That is, since the arrangement interval of the transistors is narrow, the transistor adjacent to the observation position is necessarily included in the laser spot.

  When the LVP measurement is performed in this state, the potential waveforms of a plurality of transistors are mixed and observed, and it is difficult to use for a purpose such as failure analysis.

  In addition, lowering the voltage of the power supply of the semiconductor integrated circuit is one factor that makes LVP measurement difficult. That is, when the amplitude of the signal voltage is reduced by lowering the voltage of the power source, the change in the light absorptance due to the Franz-Keldish effect is also reduced, making LVP measurement difficult.

As a technique for solving the problem that the LVP measurement becomes difficult due to the element size reduction and the power supply voltage reduction as described above, a method using an LVP measurement element can be easily inferred. This is a method in which a structure having a relatively large area and high LVP observability is formed in advance in a semiconductor integrated circuit. For example, when it is desired to measure the potential of a certain metal wiring, the metal wiring and the n + diffusion layer (heavily doped n ⁺ region, also simply referred to as “n ⁺ region”) 706 in FIG. 14 are connected using a contact. Keep it. The n + diffusion layer 706 and the p-type semiconductor substrate form a diode structure, and the electric field strength of the junction surface changes depending on the potential of the n + diffusion layer 706. Therefore, by performing LVP measurement using the n + diffusion layer 706 as an observation position, A potential waveform of the wiring can be obtained.

  Accordingly, it is an object of the present invention to provide a measuring method and a measuring element in which the change in light absorption rate due to the Franz-Keldish effect is large as compared with such a conventional structure.

  Another object of the present invention is to provide a method and an element capable of reducing the element size.

  A method according to one aspect of the present invention for achieving the above object is to connect a measurement target region of a potential waveform to a measurement element having an impurity diffusion region and a gate and having a channel structure, and a laser is connected to the measurement element. By measuring the reflected light by irradiating light, the potential of the region to be measured is measured. More specifically, the method according to the present invention includes an impurity diffusion region provided in a substrate surface layer, and a gap between the impurity diffusion regions provided on a substrate via a gate insulating film and extending between the impurity diffusion regions. A measuring element having at least one gate is provided in the semiconductor device, and a region for measuring a potential waveform in the semiconductor device is connected to at least one of the impurity diffusion region and the gate; Measure the potential by irradiating the laser beam at the laser irradiation position and measuring the reflected light, and at that time, based on the signal transition of the region to be measured, orthogonal to the extending direction of the gate of the measuring element A band gap is inclined on both sides or one side of the gate along the direction to change the light absorption rate.

  An element according to another aspect of the present invention is a measurement element having an impurity diffusion region and a gate and having a channel structure, wherein a region to be measured for a potential waveform is connected to the gate or the impurity diffusion region, The measurement element is irradiated with laser light, and the potential of the measurement target region is measured by measuring the reflected light. A measurement element for performing laser voltage probe measurement as a laser irradiation position, the impurity diffusion region provided on a substrate in a gap between the impurity diffusion region provided on a substrate surface layer and the impurity diffusion region via a gate insulating film A region to be measured of a potential waveform in the semiconductor device is connected to at least one of the impurity diffusion region and the gate, and the region to be measured has at least one gate extending between the regions; On the basis of the signal transition, a band gap is inclined on at least one side of the gate along a direction orthogonal to the extending direction of the gate of the measuring element, and a change in optical absorptance occurs. .

In the present invention, a region to which a potential waveform is measured by the laser voltage probe measurement is connected to one of the impurity diffusion region and the gate to apply a signal, and the other of the impurity diffusion region and the gate is applied. In addition, a signal having a phase opposite to that of the signal applied to the one side is applied.
[Principle of the Invention]

  The present invention provides an LVP measurement element structure for facilitating potential waveform measurement by LVP, two impurity diffusion regions, a gate polysilicon region sandwiched between them, and a conductor that short-circuits the two impurity diffusion regions. It has a structure consisting of wiring. This is the same shape as a normal MOS capacitor, but is configured such that a signal to be measured is applied to the impurity diffusion region and a signal having a logic opposite to that of the impurity diffusion region is applied to the gate region. This is different from ordinary MOS capacitors.

  This structure does not have any function as a digital circuit element, but has a feature that the LVP observability when the center of the MOS capacitor is the laser irradiation position is higher than that of an inverter or the like.

  Therefore, by using the element structure for LVP measurement of the present invention, potential waveform measurement by LVP is possible even when the voltage amplitude is small.

  In addition, since the LVP measurement element structure of the present invention has a larger change in light absorption than the conventional element structure, the element size can be reduced.

  In the element structure for LVP measurement according to the present invention, the band gap is horizontal when the channel is in the ON state, but when the channel is in the OFF state, the steep band gap is formed in a relatively narrow region on both sides of the gate. An inclination occurs, and the light absorption rate changes in this region.

  Therefore, according to the present invention, it is possible to obtain a potential waveform by performing LVP measurement with the center of the gate as the laser irradiation position and measuring the reflected light intensity.

  In the MOS transistor of the inverter element, since the source is fixed to the power supply or ground potential, the band gap tilt is generated only in the region between the gate and the drain.

  In contrast, in the LVP measurement element of the present invention, the band gap inclination is generated on both sides of the gate, so that the change in the reflected light intensity when irradiated with the laser light is the MOS transistor of the inverter element. Compared to the above, the LVP observability is high.

  For the same reason, the LVP observability of the LVP measuring element of the present invention is higher than that of the CMOS logic circuit element.

  According to the present invention, since the change in the light absorptance is large as compared with a conventionally proposed measuring element structure of the same kind, the LVP observability is high. Therefore, potential waveform measurement inside the semiconductor integrated circuit using the laser voltage probe measurement method is possible even when the power supply voltage is lowered and the voltage amplitude of the signal waveform is reduced due to future advances in the semiconductor integrated circuit manufacturing process. It is said.

  Further, according to the present invention, it is possible to make the size smaller than that of a similar structure proposed in the past.

  Embodiments of the present invention will be described below. FIG. 1 is a diagram for explaining the structure and operating principle of a measurement element according to the first embodiment of the present invention, and FIG. 1A is a plan view showing the configuration of an LVP measurement element 101. .

  Referring to FIG. 1A, the LVP measurement element 101 of the present embodiment has a layout configuration of a drain region 103, a source region 105, a gate region 107, an n-well region 109, a contact 111, Metal wirings 113-1 and 113-2 are provided.

  The drain 103 and the source 105 are formed on the surface of the n-well 109, and the gate 107 is made of a conductive member formed in a region between the drain 103 and the source 105 via a gate insulating film (oxide film) (not shown). The n-well 109 is fixed to the power supply potential of the integrated circuit and forms a p-channel MOS transistor as a whole. Note that the drain region 103, the source region 105, and the gate region 107 are also referred to as the drain 103, the source 105, and the gate 107. The gate 107 made of a conductive member is also called a gate electrode, for example, made of polysilicon. In this case, it is also called a polysilicon gate.

  Further, the drain 103 and the source 105 are short-circuited by the contact 111 and the metal wiring 113-1, and the LVP measuring element 101 as a whole forms a pMOS capacitor. The gate 107 is connected to the metal wiring 113-2.

  In the present embodiment, a region (not shown) for measuring a potential waveform by LVP is connected to the metal wiring 113-1 in FIG. 1A, and the metal wiring 113-1 is connected to the metal wiring 113-2. The circuit is configured so that an inverse logic digital signal is applied. That is, a signal under measurement is applied to the drain 103 and the source 105, and a digital signal having a logic opposite to that of the signal under measurement is always applied to the gate 107. Such a configuration is one of the characteristics of the present embodiment, and is a characteristic point different from the conventional digital circuit element.

  Next, the operation of this embodiment will be described. By using the vicinity of the center of the LVP measuring element 101 as an observation point, waveform measurement by LVP is possible.

  Further, the LVP measurement element has an advantage that the waveform observation is easy because the change in the amount of light absorption due to the presence or absence of an electric field is larger than that of a normal CMOS logic circuit element transistor. The reason for this will be described later.

  In contrast to the example described with reference to FIG. 1A, the measurement target region of the potential waveform is connected to the metal wiring 113-2 by LVP, and the metal wiring 113-1 is opposite to the metal wiring 113-2. Even if the circuit is configured so that a logic digital signal is applied, it can be operated in the same manner.

  For convenience of explanation, the LVP measurement element 101 is a p-channel MOS transistor. However, even if an n-channel MOS transistor is used, the LVP measurement element 101 can function similarly.

  Next, the reason why the light absorption amount of the LVP measurement element 101 is larger than that of a normal transistor will be described.

  LVP measurement uses the property that the light absorption coefficient changes as the band gap tilts as the measurement principle. That is, when the band gap is tilted by the electric field, the light absorption coefficient also changes. By irradiating this region with laser light, the electric field and the potential waveform can be measured from the change in the reflected light intensity.

  On the other hand, it is clear from the examination result (to be described later) of the applicant of the present application that the horizontal band gap inclination on the channel surface of the transistor contributes most to the change in the amount of light absorption during the LVP measurement. ing.

  FIG. 1B shows a cross-sectional structure and a band gap of the channel surface in the region between the AA ′ lines in FIG. 1A (the gate length direction perpendicular to the gate electrode extending direction (gate width direction)). It is a figure showing inclination, and shows a mode that the shape of a band gap changes with the electric potential of the gate 107. FIG. In the cross-sectional view of FIG. 1B, the gate insulating film (oxide film) provided on the substrate in the region between the drain 103 and the source 105 is not shown, and only the gate 107 (gate electrode) is shown. ing.

  For example, 121 in FIG. 1B is a band gap when the potential of the gate 107 is at a low level, and 123 in FIG. 1B corresponds to a band gap when the potential of the gate 107 is at a high level. .

  When the potential of the gate 107 is at a low level, the potential of the channel region 115 is lowered by the electric field from the gate 107, and the band gap 121 of the channel region 115 moves to the higher energy level side. Further, since the drain 103 and the source 105 are at a high level, the band gap 121 moves to a lower energy level, and as a result, the band gap 121 has a horizontal shape.

  On the other hand, when the potential of the gate 107 is at a high level, the potential rises in the channel region 115, and the band gap 123 of the channel region 115 is bent toward the lower energy level to form an energy barrier. At this time, the transistor is turned off, and the channel region 115 has high resistance. However, since the drain 103 and the source 105 are at the low level, the band gap 123 is bent to the higher energy level, and as a result, the gate 107 The slope of the band gap 123 becomes steep on both sides.

  At this time, the focused spot diameter in the laser irradiation region of the LVP is about several hundred nm, whereas the length of the gate 107 is 100 nm or less in the recent advanced semiconductor integrated circuit manufacturing process. It is possible to capture both of the band gap inclinations on both sides of the laser irradiation region.

  As a comparative example of the present invention, in the case of a normal CMOS inverter device as shown in FIG. 2A, the band gap of the channel surface has a shape as shown in FIG.

  FIG. 2A shows the structure of a 1 W size inverter, where 103 is the drain of the p-channel MOS transistor, 105 is the source of the p-channel MOS transistor, and 107 is the gate of the p-channel MOS transistor. , 109 represents an n-well. 131 is a drain of the n-channel MOS transistor, 133 is a source of the n-channel MOS transistor, and 135 is a gate of the n-channel MOS transistor. The source 105 of the p-channel MOS transistor is connected to the power supply via the metal wiring 113, the source 133 of the n-channel MOS transistor is connected to the ground via the metal wiring 113, and the gate 107 of the p-channel MOS transistor The gate 135 of the n-channel MOS transistor is commonly connected to the metal wiring 113-3, and the drain 131 of the p-channel MOS transistor and the drain 131 of the n-channel MOS transistor are commonly connected to the metal wiring 113-4. The overall structure of FIG. 2A has a function of outputting the potential applied to the metal wiring 113-3 from the metal wiring 113-4 after logical inversion. Also, the p-channel MOS transistor in FIG. 2A and the LVP measurement element 101 in FIG. 1A have the same size.

  FIG. 2B shows a cross-sectional view of a region between BB ′ corresponding to the channel surface of the pMOS in FIG. 2A and a band gap shape, and 121 is a band when the gate potential is at the low level. It is a gap and 123 is a case of a High level. Comparing the bandgap shapes of FIG. 2B and FIG. 1B, the inverter of FIG. 2 has a steep band only on one side of the gate 107 (the drain 103 side) because the potential of the source 105 is fixed. No gap tilt occurs.

  In contrast, in the LVP measurement element 101 of the present embodiment, the slope of the band gap 123 becomes steep on both sides of the gate 107 (see FIG. 1B). Therefore, the LVP measurement element 101 in FIG. 1A has higher LVP observability than an inverter of the same size.

  Next, the reason why it is possible to determine that what is observed by the LVP is the horizontal band gap inclination in the channel surface of the transistor will be described.

  In the past, the applicant of the present application has studied by measurement which part of the transistor has an electric field observed by LVP. FIG. 3 shows the structure of the p-channel MOS transistor 201 used for this study. This transistor is a p-channel MOS transistor formed on the n-well 109. The technical node of the manufacturing process is 90 nm and the physical gate length is 65 nm. The source 105 is connected to a power supply via a metal wiring 113, and the power supply potential is 1V. Further, the gate 107 and the drain 103 are connected to the metal wiring 113, respectively, and a digital signal of a high level (+1.0 V) or a low level (0 V) can be applied from the outside.

  FIG. 4 shows the result of LVP measurement performed on the center of the transistor 201 in FIG. In FIG. 4A, as shown in the “Circuit” column, LVP measurement is performed when a clock signal is applied to the drain of the transistor 201 and the gate is fixed at the power supply potential VDD. At this time, the waveform of the clock signal is 301 shown in the column of the LVP waveform in FIG. 4A, but the voltage has a high level of 1V and the low level is 0V.

  FIG. 4B shows a case where the drain is fixed at the power supply potential VDD and the clock signal is applied only to the gate, contrary to FIG. 4A.

  FIG. 4C shows a case where a clock signal is applied to the gate and a signal waveform having a logic opposite to that of the gate is applied to the drain. FIG. 4 (c) can be said to simulate the operation state of the inverter because the drain and gate are always in reverse logic.

  It can be seen from the LVP waveforms in FIGS. 4A and 4B that LVP measurement is possible even when a signal is applied only to the gate and drain of the transistor.

  Further, comparing FIG. 4A and FIG. 4B, it can be seen that the logic of the LVP waveform is reversed. That is, when a clock signal is input to the drain, in FIG. 4A, the signal waveform and the LVP waveform are in reverse logic (reverse phase).

  When a clock is input to the gate, the logic of the signal waveform and the LVP waveform match in FIG.

  Furthermore, it is also clear that the LVP waveform in FIG. 4C has a larger amplitude than the others.

  The column of “Band Gap Inclination” in FIG. 4 indicates the horizontal band gap of the channel surface in the region of CC ′ line (the gate length direction orthogonal to the gate electrode extending direction (gate width direction)) in FIG. It represents the slope. Reference numeral 121 denotes a case in which the input clock signal is at a low level, and 123 corresponds to a case in which it is at a high level.

  Here, as described above, assuming that the LVP detects the slope of the band gap in FIG. 4, the logic of the LVP waveform is reversed in FIGS. 4 (a) and 4 (b). Explain why.

  That is, in FIG. 4A, when the applied voltage is at the low level, the band slope increases at (121), whereas in FIG. 4B, when the applied voltage is at the high level, at (123). The slope of the band is large.

  In FIG. 4C, when the input is at the low level, the band gap 121 is substantially horizontal. When the input is at the high level, the channel-drain region 303 has a steep slope of the band gap 123. Occurs.

  Compared with FIG. 4 (a) and FIG. 4 (b), the change of the band gap inclination is large. That is, it can be explained that the amplitude of the LVP waveform in FIG. 4C is larger than that in FIGS. 4A and 4B because the change in the band gap inclination is large. That is, the larger the difference between the slope of the band gap 121 formed in the channel-drain region 303 and the slope of the band gap 123, the higher the LVP observability. That is, when a signal waveform having an inverted logic between the gate and the drain is applied to only one of the gate and the drain, the difference in the band gap is increased and the LVP observability is further improved.

  In FIG. 4A, when the input is at a high level, the band gap does not become completely horizontal even in (123), so that the amount of change in the band gap inclination becomes small.

  In FIG. 4B, since only the gate changes the potential, the amount of change in the band gap inclination is small.

  For the above reason, it can be said that what is observed by LVP is the band gap inclination in the horizontal direction of the channel surface. Therefore, LVP observability can be improved by using the structure as shown in FIG. 1 as the LVP measurement element.

  Note that, as shown in FIG. 14 as the prior art, the diode structure of the counter substrate formed only by the impurity diffusion region does not have a structure such as a gate and a channel. In comparison, the LVP observability deteriorates. FIG. 5 is a diagram schematically showing a cross-sectional view of the anti-substrate diode structure of FIG. 14 used for explaining the prior art. In FIG. 5, 141 is an impurity diffusion region, 109 is a well region, 111 is a contact, and 113 is a metal wiring. Reference numeral 143 denotes STI (Shallow Trench Isolation). A PN junction surface exists between the impurity diffusion region 141 and the well region 109. The impurity concentration of the junction surface of this part is determined by the acceleration voltage at the time of impurity implantation, and therefore, the impurity concentration gradient is gentle. Become. Therefore, the slope of the band gap does not become steep, and the observability by LVP becomes low.

  On the other hand, according to the present invention, for example, the junction surface between the channel and the drain is formed by self-alignment of the gate, so that the concentration gradient is large and the band gap inclination is steep, so that the LVP observability is high. .

  Further, the side surface of the impurity diffusion region 141 in FIG. 5 is in contact with the STI region 143, and since this is a material having a large band gap, the change in the light absorption rate due to the Franz-Keldish effect is small. Therefore, the electric field at this site is difficult to detect with LVP.

  Next, a second embodiment of the present invention will be described. The second embodiment of the present invention is an LVP measurement element structure similar to that of the first embodiment, and its basic shape is the same as 101 in FIG. The difference between the first embodiment and the present embodiment is that, in the first embodiment, a reverse potential waveform is applied to the impurity diffusion regions 103 and 105 and the gate region 107, whereas In the embodiment, a potential waveform is applied to any one of the impurity diffusion region (drain) 103, the impurity diffusion region (source) 105, and the gate region 107.

  Even in such a structure, since the electric field between the channel and the impurity diffusion region is larger than that of the conventional diode structure (FIGS. 5 and 14), the LVP measurement element described in the present embodiment has the conventional diode structure (FIGS. 5 and 5). The LVP observability is higher than that in FIG.

  However, as shown in FIG. 4, when a potential waveform is applied only to one of the impurity diffusion regions 103 and 105 and the gate region 107, the change in the band gap inclination of the channel surface becomes small, so the Franz-Keldish effect. The change in the light absorption coefficient due to becomes small. Therefore, as compared with the first embodiment, the amplitude of the LVP waveform is reduced and the observability is lowered.

  Next, a third embodiment of the present invention will be described. FIG. 6A is a plan view showing the configuration of the LVP measurement element according to the third embodiment of the present invention. In the present embodiment, as in the first embodiment, a signal to be measured and a signal obtained by logically inverting the signal to be measured are applied to the metal wirings 113-1 and 113-2, and the center of the LVP measurement element is positioned at the laser irradiation position. As a result, the potential waveform can be measured.

  The difference between the first embodiment and this embodiment is that the LVP measurement element 101 of the first embodiment includes only one gate 107, whereas in this embodiment, 3 A plurality of gates 107 are included, and a plurality of gates 107 and impurity diffusion regions 151 are alternately arranged.

  In this embodiment, since a digital signal having an inverse logic is applied to the gate 107 and the impurity diffusion region 151, a band gap inclination similar to that in the first embodiment is generated, and this can be measured by LVP. .

  FIG. 6B shows an example in which the gate 107 of FIG. 6A is formed in a ring shape so as to surround the impurity diffusion region 151, but the same effect can be obtained even in this shape.

  This embodiment corresponds to future transistor size reduction.

  According to ITRS (INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS), it is said that the transistor size will be halved in the next six years. It is impossible. Therefore, when the transistor size is reduced, in the LVP measurement element of the first embodiment shown in FIG. 1, the element area becomes smaller than the area of the laser irradiation region, and it is difficult to easily observe the potential waveform by the LVP. there's a possibility that.

  In the present embodiment, by alternately arranging the gates 107 and the impurity diffusion regions 151, an electric field and a Franz-Keldish effect are generated in a wide area range. Therefore, even when the transistor size is reduced, the potential waveform can be observed by LVP.

  Next, a fourth embodiment of the present invention will be described. FIG. 7A is a plan view showing a configuration of an LVP measurement element according to the fourth embodiment of the present invention. Also in the fourth embodiment of the present invention, as in the first embodiment, the signal to be measured and a signal obtained by logically inverting it are applied to the metal wirings 113-1 and 113-2, and the LVP measurement element By performing LVP measurement with the center as the laser irradiation position, the potential waveform can be measured.

  As a difference between the first embodiment and the present embodiment, the LVP measurement element 101 of the first embodiment has the drain region 103 and the source region 105 as constituent elements. The LVP measuring element uses only one impurity diffusion region 151 instead of the above. Therefore, in this embodiment, the impurity diffusion region 151 is arranged in a U shape around the gate 107. Even in such a shape, a band gap inclination similar to that in FIG. 1B occurs between AA ′ in FIG. 7A, so that the LVP waveform measurement similar to that in the first embodiment is performed. Is possible.

  FIG. 7B shows an example in which the number of gates 107 is plural. In the example shown in FIG. 7A, the number of gates 107 is one, whereas in the example shown in FIG. 7B, a plurality of gates are provided to increase the area of the LVP measurement element. be able to. Therefore, even when the transistor size is reduced in the future, it is possible to maintain good LVP observability.

  Next, a fifth embodiment of the present invention will be described. FIG. 8 is a plan view showing the configuration of the present embodiment. The purpose of this embodiment is to improve the LVP observability by slightly changing the shape of the inverter element as shown in FIG.

  In FIG. 8, 103 is a p-channel drain, 105 is a p-channel source, 107 is a gate, 109 is an n-well, and these form a p-channel MOS transistor as a whole. 131 is an n-channel drain, 133 is a source, and 135 is a gate, which form an n-channel MOS transistor. Further, the p-channel source 105 is connected to the power supply via the metal wiring 113, and the n-channel source 133 is connected to the ground via the metal wiring 113. As a whole in FIG. The digital signal applied to -3 is logically inverted and an inverter circuit that outputs the signal from 113-4 is formed. All connections between the drain / source / gate and the metal wiring are made by contacts 111.

  For example, in the inverter element of FIG. 8A, a protrusion 501 protruding from the edge of the gate 107 in the direction perpendicular to the longitudinal direction is added to the gate 107 of the p-channel MOS transistor. Since both sides of the protrusion 501 are drains, a band gap inclination similar to that in FIG. 1B occurs between A-A ′ in FIG.

  Therefore, by performing the LVP measurement with the protruding portion 501 as the laser irradiation position, the potential waveform measurement can be performed as in the first embodiment.

  In FIG. 8A, two protrusions 501 are provided, but the same effect can be obtained even if this is one place. Further, if the number is three or more, the observability can be further improved.

  FIG. 8B shows an example in which an LVP measuring element 101 is additionally arranged in the CMOS inverter element.

  The LVP measurement element 101 in FIG. 8B has the same structure as that described in the first embodiment. However, the gate of the LVP measuring element 101 is connected to the gate 107 of the p-channel MOS transistor of the inverter. The drain and source of the LVP measuring element 101 are connected to the output of the CMOS inverter via the metal wiring 113-4. For this reason, a reverse digital signal is applied to the diffusion (drain / source) and gate of the LVP measuring element 101.

  Therefore, the band gap shape of the A-A ′ region in FIG. 8B also has the same shape as in FIG. 1B, and LVP measurement is possible as in the first embodiment.

  In FIG. 8, the LVP observability is improved by changing the shape of the p-channel MOS transistor, but the same effect can be obtained by changing the shape of the n-channel MOS transistor.

  Further, although the shape of the CMOS inverter element is changed in FIG. 8, this technique can be applied to most CMOS logic circuit elements.

  Next, a sixth embodiment of the present invention will be described. In the first embodiment, it is necessary to apply a signal having an inverse logic to the signal under measurement to the LVP measurement element. In the sixth embodiment of the present invention, an inverter is used to generate an inverse logic signal. Yes.

  FIG. 9 is a plan view showing a layout configuration according to the sixth embodiment of the present invention. In the present embodiment, an inverter element 601 is added to the LVP measurement element 101 described in the first embodiment. The inverter 601 has a function of logically inverting and outputting a digital signal applied to the input terminal 113-3, as in a normal case, but the output of the inverter is LVP measured via the metal wiring 113-1. The inverter input 113-3 is connected to the gate 107 of the LVP measuring element 101 via the metal wiring 113-2. 9 is represented by a circuit diagram (equivalent circuit), the configuration shown in FIG. 10 is obtained. An inverter 601 and an LVP measurement element 101 (MOS capacitor) having a source and a drain connected to the output of the inverter 601 and an input terminal 113-3 of the inverter 601 connected to a gate are provided.

  When a signal to be measured is applied to the input terminal 113-3 of the inverter, the signal to be measured is directly applied to the gate 107 of the LVP measuring element 101, and a digital signal having a logic opposite to that of the signal to be measured is applied to the drain 103 and the source 105. Therefore, the potential waveform can be measured by performing LVP measurement with the center of the LVP measurement element 101 as the laser irradiation position.

  In contrast to FIG. 9, the same operation can be achieved by connecting the input 113-3 of the inverter to the drain 103 and the source 105 and connecting the output of the inverter to the gate 107.

  Next, a seventh embodiment of the present invention will be described. The seventh embodiment of the present invention is an example in which an inverter is used to generate a signal having a logic opposite to that of the signal under measurement, as in the sixth embodiment. However, in the seventh embodiment of the present invention, , A composite gate in which the LVP measuring element 101 and the inverter 601 are combined. FIG. 11 is a plan view showing the configuration of the seventh exemplary embodiment of the present invention.

  In FIG. 11, 103 is a p-channel drain, 105 is a source, 107-1 is a gate, 109 is an n-well, and these form a p-channel MOS transistor as a whole. 131 is an n-channel drain, 133 is a source, and 135 is a gate, which form an n-channel MOS transistor. Further, the p-channel drain 103 and the n-channel drain 131 are connected by a metal wiring 113-1, and as a whole, the digital signal applied to the metal wiring 113-3 corresponding to the input is logically inverted and then the metal is inverted. An inverter circuit that outputs from the wiring 113-1 is formed.

  In FIG. 11, since the impurity diffusion region 151 is connected to the metal wiring 113-1, a potential waveform whose input is logically inverted is also applied to the impurity diffusion region 151. Therefore, when a signal under measurement is applied to the input (metal wiring) 113-3 (input terminal of the CMOS inverter), a digital signal obtained by logically inverting the signal under measurement is applied to the drain 103 and the impurity diffusion region 151 of the p-channel MOS transistor. The signal under measurement is applied as it is to the gate 107-2 in the meantime. That is, in this region, digital signals having opposite logics are applied to the gate 107-2 and the impurity diffusion region 151, respectively.

  In this state, it can be said that the p-channel drain 103 and the impurity diffusion region 151 and the gate 107-2 therebetween play a role of the LVP measurement element 101 in FIG. Therefore, the potential waveform of the signal under measurement can be measured by performing LVP measurement with the vicinity of 611 in FIG. 11 as the laser irradiation position.

  FIG. 12 is a diagram for explaining a cross section of the region between the D-D ′ lines in FIG. 11 and the band gap shape. The band gap inclination in the region between the D-D 'lines in FIG. 11 has the shape of FIG. In FIG. 12, 121 is a band gap inclination when the potential of the input (metal wiring) 113-3 is at a low level, and 123 corresponds to the case when the input is at a high level.

  As shown in FIG. 12, there are three regions where the band gap 123 has a steep slope between DD ′, and the distance is concentrated in a range of about 400 nm (technical node is 90 nm). in the case of). Therefore, it is possible to capture all the three band gap inclinations in the LVP laser irradiation region.

  FIG. 13A shows a structural diagram of a 2W size CMOS inverter having the same size as FIG. This inverter element has a function of logically inverting the potential applied to the metal wiring 113-3 and outputting it from the metal wiring 113-4.

  FIG. 13B shows a cross-sectional structure diagram and a band gap shape of the E-E ′ region of FIG.

  Comparing FIG. 13B and FIG. 12, the 2W inverter of FIG. 13B has two points where the slope of the band gap becomes steep, whereas the LVP measuring element described in this embodiment As shown in FIG. 12, the band gap has a steep slope in three regions.

  Therefore, the LVP measuring element of the present embodiment has an advantage that the change in the light absorptance due to the Franz-Keldish effect is larger than that of the 2 W inverter having the same area, and therefore the LVP observability is improved.

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the configuration of the above embodiment, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, modifications are included.

(A) is a top view which shows the structure of the 1st Embodiment of this invention, (b) represents a mode that the cross-section of A-A 'line and a band gap inclination change. (A) shows the structure of a conventional 1 W size inverter element, and (b) shows the cross-sectional structure of the B-B ′ line and the change in the band gap inclination in the same region. It is a top view of a p-channel MOS transistor of 2W size. FIG. 4 is a diagram illustrating an LVP waveform and a band gap shape when a clock signal is applied to the pMOS of FIG. 3 under various conditions. FIG. 4A is a diagram in which a clock is applied only to the drain with the gate fixed at a power supply potential. In this case, (b) corresponds to the case where the drain is fixed to the power supply potential and a clock is applied to the gate, and (c) corresponds to the case where an inverse logic signal is applied to the gate and drain. It is sectional drawing of the conventional diode structure shown by FIG. (A), (b) is a top view which shows the structure of the 3rd Embodiment of this invention. (A), (b) is a top view which shows the structure of the 4th Embodiment of this invention. (A), (b) is a top view which shows the structure of the 5th Embodiment of this invention. It is a top view which shows the structure of the 6th Embodiment of this invention. It is a figure which shows the equivalent circuit of FIG. It is a top view which shows the 7th Embodiment of this invention. It is the figure which showed the cross-section and band gap shape of the D-D 'area | region of FIG. (A) is a top view which shows the structure of the conventional 2W size inverter element, (b) is sectional drawing and band gap shape of the E-E 'line of (a). It is a figure which shows the structure disclosed by special table 2002-522770.

Explanation of symbols

101 LVP measuring element 103 pMOS drain 105 pMOS source 107 pMOS gate 109 n well 111 contact 113 metal wiring 115 channel 121 band gap (when input voltage is low level)
123 Band gap (when input voltage is High level)
131 drain of nMOS 133 source of nMOS 135 gate of nMOS 141 impurity diffusion region of diode element 143 STI region 151 impurity diffusion region 201 p-channel MOS transistor 301 input potential waveform 303 region between channel and drain (region with steep band gap slope)
501 Projection 601 Inverter element 611 Laser irradiation position 701 Laser beam (laser beam)
702 pn junction 703 oxide film 704 conductor (metal)
705 Photodetector 706 n + diffusion region (n + diffusion layer)

Claims (22)

One of the impurity diffusion region and the gate electrode of the measuring element having an impurity diffusion region and a gate electrode and having a channel structure is connected to a region to be measured for a potential waveform, and a first signal is applied,
By applying a second signal having a logic opposite to the first signal to the other of the impurity diffusion region and the gate electrode , irradiating the measuring element with laser light and measuring reflected light, A method for measuring a potential waveform in a semiconductor device, comprising: measuring a potential of a region to be measured. A measurement element having an impurity diffusion region provided in a substrate surface layer and at least one gate electrode provided via a gate insulating film on a substrate in a gap between the impurity diffusion regions and extending between the impurity diffusion regions In the semiconductor device,
A region to be measured for a potential waveform in the semiconductor device is connected to at least one of the impurity diffusion region and the gate electrode ,
Connecting a region to be measured of the potential waveform to one of the impurity diffusion region and the gate electrode, and applying a first signal;
A second signal having a logic opposite to the first signal is applied to the other of the impurity diffusion region and the gate electrode;
Measuring the potential by irradiating a laser beam with the measuring element as a laser irradiation position and measuring the reflected light,
At that time, based on the signal transition of the region to be measured, the band gap is inclined on at least one side of the gate electrode along the direction orthogonal to the extending direction of the gate electrode of the measuring element to absorb light. A method for measuring a potential waveform inside a semiconductor device, wherein the rate is changed. Each includes a plurality of gate electrodes extending the region between the impurity diffusion regions,
One end of the plurality of gate electrodes is commonly connected, the other end of the plurality of gate electrodes is a free end or commonly connected,
The common first signal is applied to the plurality of impurity diffusion regions,
The method of measuring a potential waveform in a semiconductor device according to claim 1, wherein the second signal is applied to the plurality of gate electrodes . Two impurity diffusion regions are provided on both sides of the gate electrode in the extending direction, or one impurity diffusion region surrounds both sides of the gate in the extending direction and one end of the gate electrode. 3. The method for measuring a potential waveform inside a semiconductor device according to claim 1, wherein the potential waveform is measured inside the semiconductor device. The one impurity diffusion region surrounds both sides in the extending direction of the plurality of gate electrodes and one end of the plurality of gate electrodes , and the other ends of the plurality of gate electrodes are connected in common. 3. A method for measuring a potential waveform inside a semiconductor device according to 1 or 2. A protrusion projecting in a direction perpendicular to a longitudinal direction from an edge of the gate electrode of the at least one MOS transistor at a gate electrode of at least one of the two MOS transistors constituting the inverter element; 3. The method for measuring a potential waveform inside a semiconductor device according to claim 1, wherein an impurity diffusion region of the at least one MOS transistor is provided on both sides of the semiconductor device. 3. The potential waveform inside the semiconductor device according to claim 1, wherein an input of the inverter element is connected to a gate electrode of the measuring element, and an output of the inverter element is connected to the impurity diffusion region. Measuring method. A plurality of gate electrodes of at least one of the two MOS transistors constituting the inverter element are arranged in parallel, and the plurality of gate electrodes are connected in common,
At least one of the impurity diffusion regions provided on both sides in the extending direction of the plurality of gate electrodes is connected to a power source, and the other impurity diffusion regions are commonly connected to the output of the inverter. The method for measuring a potential waveform inside a semiconductor device according to claim 1 or 2. A plurality of gate electrodes are arranged in parallel for each of the first and second MOS transistors constituting the inverter element, and the plurality of gate electrodes are connected in common,
At least one of the impurity diffusion regions provided on both sides in the extending direction of the plurality of gate electrodes of the first MOS transistor is connected to a first power supply, and the other impurity diffusion regions are connected to the inverter. Connected to the output,
At least one of the impurity diffusion regions provided on both sides in the extending direction of the plurality of gate electrodes of the second MOS transistor is connected to a second power supply, and the other impurity diffusion regions are connected to the inverter. 3. The method of measuring a potential waveform inside a semiconductor device according to claim 1, wherein the potential waveform is connected to an output. A potential waveform measuring method inside a semiconductor integrated circuit in which a measuring element capable of observation by laser voltage probe measurement is connected to a conductor wiring in a semiconductor integrated circuit, and laser voltage probe measurement is performed with the measuring element as a laser irradiation position In
A MOS capacitor structure having a gate electrode and an impurity diffusion region, a circuit for applying a potential waveform of a measurement location to one of the impurity diffusion region and the gate electrode, and the other of the impurity diffusion region and the gate electrode , It said circuitry for indicia pressurizing the potential waveform and reverse logic of the digital signal waveform of the measured point, the elements of the structure provided with the, used as the measuring device, a semiconductor integrated circuit inside the voltage waveform measurements, characterized in that Method. 11. The method of measuring a potential waveform in a semiconductor integrated circuit according to claim 10 , wherein the gate electrode is made into a plurality of two or more, and the gate electrode and the impurity diffusion region are alternately arranged. 11. A semiconductor integrated circuit according to claim 10 , wherein a protrusion directed toward the drain region is provided with respect to the gate electrode of the MOS transistor of the CMOS logic circuit element, and the protrusion is used as an element for measuring a laser voltage probe. Potential waveform measurement method. 11. A potential waveform inside a semiconductor integrated circuit, wherein the measurement element according to claim 10 is added to a CMOS logic circuit element, and a potential waveform is measured with a laser voltage probe on the measurement element. Measuring method. 11. The method for measuring a potential waveform in a semiconductor integrated circuit according to claim 10 , wherein an inverter element is used to obtain a digital signal waveform obtained by logically inverting the potential waveform at the location to be measured. 15. The method of measuring a potential waveform in a semiconductor integrated circuit according to claim 14 , wherein the inverter and the laser voltage probe measuring element are combined to form a composite gate shape. A laser voltage probe measuring element of a semiconductor integrated circuit that performs laser voltage probe measurement by connecting a laser voltage probe measuring element to a measurement target region of a potential waveform in a semiconductor integrated circuit and using the measuring element as a laser irradiation position. ,
A MOS capacitor structure comprising a gate electrode and an impurity diffusion region;
A signal to be measured of the measurement target region is applied to one of the impurity diffusion region and the gate electrode, and a digital signal waveform having a logic opposite to that of the signal to be measured is applied to the other of the impurity diffusion region and the gate electrode. And a circuit to
An element for measuring a laser voltage probe, comprising: A laser voltage probe measuring element of a semiconductor integrated circuit that performs laser voltage probe measurement by connecting a laser voltage probe measuring element to a measurement target region of a potential waveform in a semiconductor integrated circuit and using the measuring element as a laser irradiation position. ,
A drain region, a source region, a gate electrode, a first metal wiring that short-circuits the drain region and the source region, and a second metal wiring connected to the gate electrode,
The measurement target region is connected to one of the first metal wiring and the second metal wiring and a signal to be measured is applied, and the other of the first metal wiring and the second metal wiring is applied to the other. A circuit for applying a digital signal having an inverse logic to the signal under measurement;
  An element for measuring a laser voltage probe, comprising: Two or more gate electrodes are used,
18. The laser voltage probe measuring element according to claim 16, wherein gate electrodes and impurity diffusion regions are alternately arranged. 18. A CMOS logic circuit element comprising a MOS transistor gate electrode provided with a protrusion directed to a drain region, and constituting the laser voltage probe measuring element according to claim 16. element. 18. A CMOS logic circuit element to which the element structure for measuring a laser voltage probe according to claim 16 is added. An inverter element is added to the laser voltage probe measuring element according to claim 16 or 17 ,
An element for measuring a laser voltage probe, wherein a digital signal waveform obtained by logically inverting a potential waveform in the measurement target region is obtained using the inverter element. The laser voltage probe measuring element according to claim 21 , wherein the inverter and the laser voltage probe measuring element are combined to form a composite gate shape.

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