JP4332013B2 - Pseudo multi-port memory device and pixel readout method of pseudo multi-port memory device - Google Patents

Description

The present invention relates to a multi-port memory device, and is used in particular for motion vector detection in inter-frame image encoding processing of moving images, and writes a plurality of pixels to a continuous address at a time and extracts a plurality of pixels from unrelated addresses. those related to the pseudo multi-port memory device and a pixel reading way method can be read simultaneously.

  The detection of a motion vector is to detect which pixel block in another image has moved from a pixel block in an image (called a macro block in MPEG-2 or MPEG-4, hereinafter referred to as a template). This is processing for extracting the position information. The position information is called a motion vector, and a block matching method is generally used for the detection.

  In this method, a difference absolute value is calculated between a pixel block cut out from the search area (hereinafter referred to as a search target block) and a corresponding pixel of the template, and a total sum (hereinafter referred to as difference absolute value sum) is obtained. . The position information of the search target block that minimizes the sum of absolute differences is set as a motion vector. In addition, you may obtain | require what becomes the minimum difference square value sum instead of a difference absolute value sum.

  The configuration of the motion vector detector 1 is shown in FIG. The motion vector detector 1 includes a difference absolute value sum calculation circuit 2, a minimum value detection circuit 3, and a reference memory 4. An image is held in the external frame memory 5, an area where a motion vector may exist from the external frame memory 5 (hereinafter referred to as a reference area) is copied to the reference memory 4, and pixels in the reference memory 4 are copied. Perform a search operation.

  When the reference area is transferred from the external frame memory 5 to the reference memory 4, the number of transfer pixels is reduced by utilizing the fact that the reference areas of two adjacent templates are mostly overlapped. An example of reference regions of two adjacent templates is shown in FIG.

  The template 8 and the template 9 are included in the same slice 7 in the image 6 and are adjacent to each other. The reference area 10 of the template 8 is shifted from the reference area 11 of the template 9 to the right by the number of pixels in the horizontal direction of the template. For this reason, the width of the non-overlapping area (hereinafter referred to as the update area) 12 matches the number of pixels in the horizontal direction of the template.

  When the motion search of the template 9 is started after data is transferred from the external frame memory 5 only to the update area 12, the reference area origin is changed from (0, 0) of the reference area 10 to (0, 0) of the reference area 11. Replace with '. In this way, the transfer rate from the external frame memory 5 to the reference memory 4 can be reduced by reading only the update area 12 and updating the reference area.

  Here, the full search method is known as the search method with the highest motion detection accuracy, but the full search method requires a huge amount of calculation. On the other hand, a telescopic search method is known as a search method that can obtain almost the same image quality as the full search method even though the amount of calculation can be reduced in inverse proportion to the distance between images (for example, paragraph of Patent Document 1). 0028-0032).

  In the telescopic search method, paying attention to the fact that the movement of the object is continuous in time, the amount of calculation is reduced. This telescopic search method will be described with reference to FIG. FIG. 3 is an explanatory diagram showing a telescopic search method. In the figure, images 14 to 17 are four images that are temporally continuous, and image 17 is an image that is a motion vector detection target. Image 16, image 15, and image 14 are images one screen before, two screens, and three screens ago, respectively.

  The rectangular block 13 moves from the image 14 to the image 15 with the motion vector mv3, and similarly, moves from the image 15 to the image 16 and from the image 16 to the image 17 with the motion vectors mv2 and mv1, respectively. Therefore, the motion vector of the rectangular block 13 from the image 14 to the image 17 is “mv3 + mv2 + mv1”.

  In the telescopic search method, in order to obtain a motion vector from the image 14 to the image 17, the search block 20 in the image 16 is first searched by using the rectangular block 13 in the image 17 as a template to detect the motion vector mv1. In this case, the motion vector at the center of the search area 20 is (0, 0).

  Next, the search area 19 in the image 15 is searched to detect the motion vector mv2. If the motion vector from the image 16 to the image 17 regarding the rectangular block 13 is considered, the motion vector at the center of the search area 19 is mv1. Finally, the search area 18 in the image 14 is searched to detect the motion vector mv3. When the motion vector from the image 15 to the image 17 regarding the rectangular block 13 is considered, the motion vector at the center of the search area 18 is “mv1 + mv2”.

  In the telescopic search, when searching for the motion vectors mv2 and mv3, only the search regions around the motion vectors mv2 and mv3 are searched by the full search method, not the entire reference region. For this reason, the amount of calculation can be reduced in inverse proportion to the distance between images as compared with the case of searching all reference regions. In addition, since the individual search areas are searched by the full search method, almost the same image quality as that obtained by searching the motion vectors between images separated in time by the direct full search method can be obtained.

  However, in the telescopic search, since a narrow range full search is repeatedly performed based on the previous search result, the search area is not determined until just before starting each full search. For this reason, if only the area to be truly searched is read into the reference memory 4, the address of the area to be searched next must be calculated and read after the previous full search is completed. For example, in FIG. 3, after the motion vector mv1 is determined, the address of the search area for the motion vector mv2 is calculated and read based on mv1.

  In this configuration, since the reading of the search area and the calculation of the sum of absolute differences are performed sequentially, an idle time occurs in the differential absolute value sum calculation circuit 2. However, this problem can be solved by reading the entire reference area into the reference memory 4. Although the reference memory 4 becomes large, when the reference area is transferred from the external frame memory 5 to the reference memory 4, the reference areas of two adjacent templates are mostly overlapped as shown in FIG. By transferring only the update area 12, the number of transfer pixels can be reduced. However, even in this improved transfer method (hereinafter referred to as the improved transfer method), the position of the search area to be searched next is determined after the previous full search is completed. There is no change in what cannot be done.

  When the reference area is wide, the calculation throughput of the motion vector detector 1 can be improved by parallelizing the difference absolute value sum calculator. FIG. 4 shows an example of parallelization when a divided one-dimensional TMSB (Template-pixel mapping method with search-area-pixel broadcasting) shown in Non-Patent Document 1 is used as a difference absolute value sum calculator. The search area in this case is shown in FIG.

FIGS. 4 and 5 are examples in which the template size is 4 pixels × 4 lines, the search range is horizontal −4 / + 3 (the number of blocks to be searched in the horizontal direction is 8), and the vertical direction is ± 2. . Search areas 23 and 24 are searched in parallel by difference absolute value sum calculation circuits 21 and 22, respectively. In the divided one-dimensional TMSB, it is necessary to supply two pixels in the search area at the same time. However, if the search areas 23 and 24 are partially overlapped, the pixels to be supplied simultaneously can be reduced to three pixels. For example, by supplying the pixel x _2,0 and the pixel x _{o, 8} to the difference absolute value sum calculation circuits 21 and 22, respectively, and supplying the pixel x _1,4 to both the difference absolute value sum calculation circuits 21 and 22, , The difference absolute value sum calculation circuits 21 and 22 can be operated in parallel. Similarly, when the difference absolute value sum calculation circuit is operated in parallel, it is sufficient to supply five pixels in the search region simultaneously.

  In order to supply the plurality of pixels to the difference absolute value sum calculation circuit, it is conceivable to use a multi-bank divided memory composed of a plurality of banks. However, in the improved transfer method for the reference memory, the address of the search area is determined after mapping the reference area on the reference memory. For this reason, it is extremely difficult to perform memory mapping so that pixels in the search area can be read simultaneously for the number of banks.

  FIG. 6 is a block diagram of a pseudo multi-port memory that can solve this problem (see, for example, paragraphs 0049 to 0054 of FIG. 2 and FIG. 2). 1-port memories 25 and 26 divided into two banks, a pixel rearrangement circuit 30 for inputting and rearranging and outputting eight pixels, and shift registers 27 to 29 in units of pixels for three pixels.

  If this pseudo multi-port memory is used, three pixels can be simultaneously supplied to the two parallel absolute difference sum calculation circuits 21 and 22 shown in FIG. Pixels with numbers 00 to 03, numbers 08 to 11, numbers 16 to 19, and numbers 24 to 27 are stored at addresses 0, 1, 2, and 3, respectively, of the 1-port memory 25. Also, pixels of numbers 04 to 07, numbers 12 to 15, numbers 20 to 23, and numbers 28 to 31 are stored at addresses 0, 1, 2, and 3, respectively, of the 1-port memory 26.

  Here, for example, when setting the pixels of numbers 22 to 25 across the 1-port memories 25 and 26 in the shift register 27, first, the pixels of numbers 24 to 27 are read at a time from the address 3 of the 1-port memory 25, and 1 Pixels 20 to 23 are read from address 2 of the port memory 26 at a time. Next, these eight pixels are rearranged by the pixel rearrangement circuit 30, and the pixels of numbers 22 to 25 are selected. That is, of the 8 pixels to be read, when a pixel with a lower number is stored in the 1-port memory 26, the address of the 1-port memory 25 is calculated by adding 1 to the address of the 1-port memory 26. On the other hand, of the 8 pixels to be read, when a pixel with a lower number is stored in the 1-port memory 25, the same address as that of the 1-port memory 25 is given to the 1-port memory 26. As a result, it is possible to read out four pixels having consecutive numbers starting from a pixel having an arbitrary number.

  Then, it is rearranged by the pixel rearrangement circuit 30 and set in the shift registers 27-29. However, since the pixels cannot be set simultaneously in the shift registers 27 to 29 and are set over 3 clocks (CK), there is a difference in setting timing. This difference in setting timing is corrected by making a difference in the number of shift stages of the shift registers 27 to 29, and three pixels are output simultaneously. As described above, the pseudo multi-port memory can simultaneously read a plurality of pixels from unrelated addresses without performing special memory mapping.

  In signal processing, an address generation method called modulo addressing is frequently used. Modulo addressing is to repeatedly generate an address limited between the minimum address and the maximum address while incrementing the address by one.

  FIG. 7 is a diagram for explaining modulo addressing in a memory divided into 16 banks (see, for example, FIG. 6 of Patent Document 2). B1 is an interbank address (0 to AF), B2 is an intrabank address (0 to A), and B3 is a bank number (0 to F).

  The inter-bank address is the address when the entire memory is viewed at once, the in-bank address is the address when each bank is viewed independently, and each bank matches the remainder when the inter-bank address is divided by the number of banks The bank number is given as follows. This relationship is expressed by the following equation.

[Inter-bank address] = [In-bank address] x [Number of banks] + [Bank number]
When reading data at consecutive inter-bank addresses from each bank, a reference inter-bank address is given, and each bank address is an intra-bank address of the inter-bank address (hereinafter referred to as a reference inter-bank address). .)) By adding the displacement.

Specifically, the modulo address can be generated by the following method (for example, refer to page 6, upper left column 4th line to lower left column 11th line of Patent Document 2, see FIG. 3).
(1) When the inter-bank address increases by one, the bank number increases by one from 0 toward F, and when it exceeds F, it returns to 0. At this time, the in-bank address increases by one. Therefore, when the bank number returns from F to 0 in the middle of the data group to be read, 1 is added as a displacement to the reference bank address at that point.
(2) However, when the reference bank address matches the bank modulo end address, 1 is not added, but the bank modulo address width is subtracted.

  For example, as shown in FIG. 7, when generating a modulo address between “minimum bank address = 3” and “maximum bank address = 8” for each bank, “reference bank address = 3-7 ", the bank address of the bank having a bank number smaller than the bank number obtained from the reference inter-bank address (hereinafter referred to as the reference bank number) is 1 as a displacement to the reference bank address. Are added to the bank, and the bank having the bank number equal to or higher than the reference bank number is given the address in the reference bank as it is.

  On the other hand, when “in-reference bank address = 8”, an in-bank address of a bank having a bank number smaller than the reference bank number is generated by subtracting 5 from the in-reference bank address, and a bank greater than or equal to the reference bank number is generated. The bank having the number is given the address in the reference bank as it is.

In this way, a modulo address of a plurality of banks can be generated only by giving a reference inter-bank address.
JP 2000-242554 A JP-A-1-311341 Toshihiro Minami, Toshio Kondo, Kazuhito Murashishi, Ryota Kasai, “Proposal of a one-dimensional systolic array-type full search motion vector detector”, IEICE (D-1), vol.J78-D-1, no.12 , Pp913-925, Dec. 1995.

  In the example of the prior art shown in FIG. 6, numbers 0 to 03 and numbers 04 to 07 are assigned to the addresses 0 of the 1-port memories 25 and 26, and numbers 08 to 11 and number 12 are assigned to the addresses 1 of the 1-port memories 25 and 26, respectively. ~ 15 pixels are stored. This can be considered that addresses are assigned to the 1-port memories 25 and 26 in units of pixels. This is hereinafter referred to as a virtual one-dimensional address.

  When a virtual one-dimensional address (hereinafter referred to as a representative address) of the lowest one of the four pixels cut out by the pixel rearrangement circuit 30 is given to the pseudo multi-port memory, the shift registers 27 to 29 to 3 are changed as follows. Output pixels simultaneously.

  (1) When the representative address exists in the 1-port memory 25, an address obtained by discarding the lower 3 bits of the representative address is given to both the 1-port memories 25 and 26. On the other hand, when the representative address exists in the 1-port memory 26, the 1-port memory 26 has an address obtained by truncating the lower 3 bits of the representative address. Give the increased address. For example, when reading from address 22 to address 25, since the representative address is in the 1-port memory 26, data at address 2 is read from the 1-port memory 26, and data at address 3 is read from the 1-port memory 25.

  (2) The pixel rearrangement circuit 30 rearranges and sets the shift register 27 to 29 so that the pixel of the representative address among the cut out eight pixels is output earliest. For example, when the pixels from address 22 to address 25 are read out, the representative address is address 22, and the pixels stored at address 22 are rearmost and the pixels stored at address 25 are rearranged to the left. .

  (3) The four pixels rearranged in this way are set in the shift registers 27-29. However, there is a difference in timing when four pixels are set in the shift registers 27 to 29. This setting timing shift is corrected by making a difference in the number of shift stages of the shift registers 27 to 29, and three pixels are output simultaneously.

  By the above method, it is possible to simultaneously output a plurality of pixels stored at unrelated addresses from the pseudo multi-port memory only by giving a representative address.

  However, in the improved transfer method for the reference memory 4, only the update area is transferred from the external frame memory 5, and the origin (0, 0) of the reference area is changed when a new template motion search is started. In order to read out pixels from the pseudo multi-port memory, an address (hereinafter referred to as a two-dimensional logical address) whose correspondence with the actual address of the 1-port memories 25 and 26 changes each time the origin is changed is representative. It needs to be converted to an address.

  Further, in the telescopic search method shown in FIG. 3, not only the reference region (search region) 18 of the image to be finally detected, but also the reference region (search region) 19 of the intermediate images 15 and 16, 20 also needs to be read into the reference memory 4. If a small-capacity memory is provided for each of these reference areas (search areas) 18-20, division loss occurs and the chip area increases. Therefore, these reference areas (search areas) 18-20 have a large capacity. It is desirable to store them together in a shared memory.

  Therefore, under the condition that all reference areas are stored in the shared pseudo multi-port memory, the update area for each reference area is written to the pseudo multi-port memory without destroying the individual reference areas. There is a problem that the above-described replacement of the origin (0, 0) must be realized for each reference area, and the two-dimensional logical address must be converted into a representative address.

  In order to solve this problem, it is conceivable to apply the modulo address generation method in the memory divided into multiple banks described in the example of the prior art. That is, it is conceivable to determine the minimum address and the maximum address for each reference area and generate an address within the range. However, although the modulo address described in the prior art example is a one-dimensional address, there is a problem that an image has a two-dimensional address in the horizontal direction and the vertical direction.

  The present invention has been made to solve such a conventional problem, and its object is to improve the reference memory 4 under the condition that all reference areas are stored in a shared large-capacity pseudo multi-port memory. The object is to provide a pseudo multi-port memory device capable of realizing the transfer method.

  In order to solve the above problem, the first aspect of the present invention is a pseudo multi-port memory device capable of simultaneously reading out a plurality of pixels from unrelated addresses, and having a word width capable of storing m (m is a natural number) pixels. Two-dimensional logical address assigning means for providing a two-dimensional logical address comprising n (n is a natural number) 1-port memory, a horizontal logical address having a finite size, and a vertical logical address having a finite size; Two-dimensional virtual address generation means for generating a two-dimensional virtual address by converting a logical address into a horizontal virtual address having an integer multiple of m × n and converting the vertical logical address into a vertical virtual address as it is; , The base address of the area to which the two-dimensional virtual address is assigned, the horizontal virtual address, and the vertical virtual address A virtual one-dimensional address generating means for generating a virtual one-dimensional address assigned to each of the n one-port memories by a pixel by adding a value obtained by multiplying the flat virtual address, and the virtual one-dimensional address ( a representative real address generating means for generating a representative real address by dividing by m × n), and a remainder obtained as a result of dividing the virtual one-dimensional address by (m × n) is further divided by m. A representative real bank number generating means for generating a bank number; a real address generating means for generating a real address to be given to each one-port memory from the representative real address and the representative real bank number; and the real address group. Input not more than m × n pixels output from the n one-port memories, and the horizontal logical address given by the two-dimensional logical address assigning means. If the address is the lowest horizontal logical address, then output mx (n-1) or less pixels having consecutive horizontal logical addresses on the upper side in ascending or descending order of the horizontal logical addresses. Or when the horizontal logical address given by the two-dimensional logical address assigning means is the highest horizontal logical address, not more than m × (n−1) pixels having consecutive horizontal logical addresses on the lower side. Comprising a plurality of shift registers each having a predetermined number of shift stages arranged in parallel to the pixel rearranging means. The pixel groups sequentially output from the means are held in order by each shift register, and a plurality of pixels constituting each pixel group are stored one by one in each shift register. Output timing adjustment means for adjusting the output timing by sequentially shifting the output from the shift registers, and simultaneously outputting desired pixels from each shift register in parallel.

  The second aspect of the present invention is the pseudo multi-port memory device according to the first aspect of the present invention, wherein the two-dimensional virtual address generation means is in a range of 0 to (horizontal virtual address size / m-1). A value corresponding to the difference between the horizontal virtual address and the horizontal logical address is calculated based on the cyclic value, and a value corresponding to the difference between the horizontal virtual address and the horizontal logical address is added to the horizontal logical address. When the size of the horizontal virtual address is exceeded, the horizontal logical address is converted to a horizontal virtual address having an integer multiple of m × n by subtracting the size of the horizontal virtual address from the result. And

  Further, the third aspect of the present invention is the pseudo multi-port memory device according to the first aspect of the present invention or the second aspect of the present invention, wherein the real address generation means is a horizontal logic provided by the two-dimensional logical address assignment means. If the address is the lowest horizontal logical address, the representative real bank is not the highest real address in the real address range to which the vertical virtual address may be translated. A one-port memory having a real bank number smaller than the number is given a real address obtained by adding 1 to the representative real address, while the representative real address is a real address where the vertical virtual address may be converted When it is the highest real address in the range, the vertical virtual address is not included in the 1-port memory having a real bank number smaller than the representative real bank number. Is given the lowest real address in the real address range that can be converted, and the horizontal logical address given by the two-dimensional logical address assigning means is the highest horizontal logical address, 1 port having a real bank number larger than the representative real bank number when the representative real address is not the lowest real address in the real address range to which the first given vertical virtual address may be translated The memory is given a real address obtained by subtracting 1 from the representative real address, while the representative real address is the lowest in the real address range to which the first given vertical logical address may be converted The one-port memory having a larger real bank number than the representative real bank number is given the representative real address first. Characterized in that a vertical virtual address is a real address generating means for providing the real address of the top level in the real address range that can be converted.

  The present invention can configure a pseudo multi-port memory device that can simultaneously read out a plurality of pixels from unrelated addresses by using a plurality of large-capacity one-port memories. By storing the area, the telescopic search motion vector detection device can be reduced in size.

  Hereinafter, embodiments of the present invention will be described. FIG. 8 is a diagram showing the sizes of the reference areas 33 to 35 for the telescopic search in the embodiment of the present invention. Assume that the size of the template is 4 pixels × 4 lines, and each search range for each screen is + 8 / −7 in the horizontal direction and ± 4 in the vertical direction.

  Similarly to the example described with reference to FIG. 3, it is assumed that the image that is the target of finally detecting the motion vector is separated from the image including the template 32 by 3 frames. In this case, the size of the reference region 33 of the image one frame away from the image including the template 32 is 20 pixels × 12 lines, and the size of the reference region 34 of the image two frames away is 36 pixels × 20 lines, The size of the reference area 35 of the image to be finally detected as a motion vector is 52 pixels × 28 lines.

  Here, since the individual search range for each screen is horizontal + 8 / −7, the number of pixels in the horizontal direction of the reference area is not actually a multiple of 4. However, the number of pixels in the update region is the same as the number of pixels in the horizontal direction of the template and is four pixels. Then, the update area is transferred to the reference memory as a group from the external frame memory. For this reason, the number of pixels in the horizontal direction of the reference area on the reference memory is assumed to be a multiple of four. In this case, the motion vector detection range by the telescopic search is horizontal + 24 / -21 and vertical ± 12.

  FIG. 9 is a diagram showing the mapping of the reference areas 33, 34, and 35 on the reference memory. The reference area 33 is mapped from address 0, the reference area 34 is mapped between the reference areas 33 and 35, and the reference area 35 is mapped to the higher address side.

  FIG. 10 is a block diagram showing the configuration of the motion vector detector 42 in the embodiment of the present invention. Reference numeral 36 is a reference memory, and 43 is an external frame memory. The motion vector detector 42 includes four difference absolute value sum calculation circuits 37 to 40. As the difference absolute value sum calculation circuits 37 to 40, a divided one-dimensional TMSB is used, the search range is divided into four in the horizontal direction, and each divided absolute value sum calculation circuit 37 to 40 is evaluated one by one. Shall.

  FIG. 11 is a block diagram of the pseudo multi-port memory in the embodiment of the present invention. In the present embodiment, the word widths of the 1-port memories 44 to 47 are made to coincide with the number of pixels in the horizontal direction of the update area. As a result, the write circuit in the update area can be simplified. However, the word width may be set to 1 / n (n is an integer) such as half of the number of pixels in the horizontal direction of the update region, 1/4, or the like. 11 shows an example in which 12 pixels are read out from the 1-port memories 44 to 47 and 8 pixels are cut out. However, when 4 1-port memories having a word width of 4 pixels are used, 16 pixels are read out to 12 pixels. It is also possible to adopt a configuration of cutting out pixels.

  The search area in this embodiment is shown in FIG. 12, and the pixels supplied to the 4-parallel absolute difference sum calculation circuits 37 to 40 are shown in FIG. As shown in FIG. 13, in this embodiment, it is necessary to simultaneously supply 5 pixels from the pseudo multi-port memory to the difference absolute value sum calculation circuits 37 to 40. This is realized by using four 1-port memories having a word width of 4 pixels, reading out 12 pixels from 3 of them, and cutting out 8 pixels.

That is, x _0,0 ~x _{0, 7} are read from the 1-port memory 44 through 47 in the first CK (CK = 0), x 0,0 ~x 0,3 to shift register 49, the shift register 50 x Set _{0,4 to} x _0,7 . Next, after 4 CK (CK = 4), x _1,0 to x _1,7 are read from the 1-port memories 44 to 47, x _1,0 to x _1,3 are read into the shift register 49, and x are sent to the shift register 50. setting the _1,4 ~x _1,7. Since the shift register 50 has four delay registers, x _0,4 to x _0,7 are output with a delay of _{4 CK} from x _0,0 to x _0,3 .

Accordingly, as shown in FIG. 13, the corresponding pixel of the x _{1, 0} ~x _{1, 3} and x _{0, 4} ~x _{0, 7} are simultaneously outputted. Furthermore, after 3CK in (CK = 7) reads the x _{0, 8} ~x _{0, 15} 1-port memory 44 to 47, x ₀ in the shift register 51 x _0,8 ~x _0,11, the shift register 52 _{, 12 to} x _0,15 are set, and after 1 CK (CK = 8), x _2,0 to x _2,7 are read from the 1-port memories 44 to 47, and x _2,0 to x are read into the shift register 49. _2,3, and sets the x _{2, 4} ~x _{2, 7} to the shift register 50. Since the shift register 51 having one registers for _delay, x _2,0 ~x _2,3, respectively corresponding pixels of x _1,4 ~x _1,7, and x _{0, 8} ~x _{0, 11} Output simultaneously.

Furthermore, after 3CK in (CK = 11) reads the x _{l, 8} ~x _{1, 15} from the 1-port memory 44 to 47, x ₁ to the shift register 51 x _1,8 ~x _1,11, the shift register 52 _{, 12 to} x 1,15 are set, and after ₁ CK (CK = 12), x _3,0 to x _3,7 are read from the 1-port memories 44 to 47, and x _3,0 to x are read into the shift register 49. ₃ , ₃ , x _3,4 to x _3,7 are set in the shift register 50. Since the shift register 51 and the shift register 52 have 1 and 5 registers for delay, respectively, x _3,0 to x _3,3 , x _{2,4 to} x _2,7 , x _{1,8 to} x _{1, 11,} and the corresponding pixel of the x _{0, 12} ~x _{0, 15} are simultaneously outputted.

In addition, after reading 2CK the (CK = 13) to x _{0, 16} ~x _{0, 18} 1-port memory 44 through 47, set in the shift register 53, after its 1CK (CK = 14) x _2,8 the ~x _{2, 15} is read from the 1-port memory 44 to 47, x _{2, 8} ~x _{2, 11} in the shift register 51, sets the x _{2, 12} ~x _{2, 15} to shift register 52, after which 1CK (CK = 15) to read the x _{4, 0} ~x _{4, 7} from 1-port memory 44 to 47, x _{4, 4} ~x the shift register 49 x _4,0 ~x _4,3, the shift register 50 Set ₄ and ₇ .

Since the shift register 53 having two registers for _{delay, x 4,0 ~x 4,3, x 3,4} ~x 3,7, x 2,8 ~x 2,11, x 1,12 ~x _1,15, and the corresponding pixel of the x _{0, 16} ~x _{0, 18} are simultaneously outputted. For example, x _4,0 , x _3,4 , x _2,8 , x _1,12 , and x _{0,16 marked} in FIG. ₁₂ are output simultaneously.

  In the present invention, the horizontal search range is determined so that the number of horizontal pixels in each reference area is an integral multiple of the number of horizontal pixels in the update area, and the reference is made in units of the number of horizontal pixels in the update area. The area is virtually divided in the horizontal direction. Each divided block is called a logical bank, and the above-described update of the origin (0, 0) is performed for each reference area in units of logical banks.

  FIG. 14 is a diagram illustrating assignment of a two-dimensional logical address to a pixel in the reference area 34 and division into logical banks. The number of pixels in the horizontal direction of the logical bank is the same as the number of pixels in the horizontal direction of the update area.

  In the present invention, before starting the search for the motion vector of the next template on the right side, the pixels in the update area are transferred from the external frame memory to the reference memory. When the search for the motion vector of the current template is completed and the search for the motion vector of the next template on the right is started, the horizontal logical address (hereinafter referred to as the horizontal logical address) and the logical bank number are updated. . However, the logical address in the vertical direction (hereinafter referred to as the vertical logical address) is not changed.

  For example, in the reference area 34 shown in FIG. 14, the horizontal logical addresses 0 to 31 after the update are replaced with the horizontal logical addresses 4 to 35 before the update, and the horizontal logical addresses 32 to 35 after the update are assigned to the updated pixels. It is done. Similarly, the logical bank numbers 0 to 7 after the update are replaced with the logical bank numbers 1 to 8 before the update, and the logical bank number 8 after the update is assigned to the update area.

  Here, in the present invention, when the number obtained by adding the number of banks in the update area to the number of logical banks obtained by dividing the reference area in the horizontal direction is not an integral multiple of the number of banks in the 1-port memories 44 to 47, the empty area And is mapped to the 1-port memories 44 to 47 so as to coincide with an integral multiple of the number of banks of the 1-port memory.

  FIG. 15 is a diagram showing a state in which the two-dimensional logical address of the reference area 34 shown in FIG. 14 is mapped to the pseudo multi-port memory. In FIG. 15, a logical bank number and a vertical logical address are combined to represent a mapping state in the form of (logical bank number, vertical logical address). The 1-port memories 44 to 47 are assigned real bank numbers 0 to 3, respectively. Since the reference area 33 is stored at addresses 0 to 23 of the 1-port memories 44 to 47, the reference area 34 is stored at addresses 24 to 63, which are higher addresses.

  In the mapping state of FIG. 15, the lower side of the horizontal logical address is mapped to the lower side of the actual address (hereinafter referred to as the real address) of the 1-port memories 44 to 47 and the side with the smaller actual bank number. The upper side of the horizontal logical address is mapped to the higher side of the real address and the side with the larger real bank number.

  The two-dimensional logical address, horizontal logical address, vertical logical address, and logical bank number in this state are called a two-dimensional virtual address, horizontal virtual address, vertical virtual address, and virtual bank number, respectively, which are updated from the external frame memory. Is transferred and the two-dimensional logical address is updated, it will not change.

  FIG. 16 is a diagram showing a state where the update area is transferred five times from the mapping state of FIG. 15 and the two-dimensional logical address is updated. In the state of FIG. 16, the pixels included in the logical banks with logical bank numbers 0 to 3 and the pixels included in the logical banks with logical bank numbers 5 to 8 in the mapping state of FIG. 15 are the same. In the state of FIG. 16, the pixels included in the logical banks of logical bank numbers 4 to 8 are newly transferred from the external frame memory after searching for motion vectors in the state of FIG.

  FIG. 17 is a diagram showing the mapping of the pixels included in the reference area 34 in the state shown in FIG. 16 to the pseudo multi-port memory. As shown in FIGS. 16 and 17, in the present invention, the correspondence between the vertical logical address and the vertical virtual address is fixed even when the two-dimensional logical address is updated, and only the correspondence between the horizontal logical address and the horizontal virtual address is changed. To do.

  Therefore, for example, when reading 8 pixels stored in the vertical logical address = 1, horizontal logical address = 22 to 29 (logical bank number = 5 to 7), in the mapping state of FIG. 12 pixels are read out from the real address = 28, and the pixel rearrangement circuit 48 cuts out 8 pixels.

  On the other hand, in the mapping state of FIG. 17, 8 pixels are read from the real address = 29 of the 1-port memories 46 and 47 and 4 pixels are read from the real address = 27 of the 1-port memory 44, and 8 pixels are cut out by the pixel rearrangement circuit 48. .

  That is, the horizontal virtual address is circulated within a certain range of the vertical virtual address. As described above, in this embodiment, even if the two-dimensional logical address is the same, the real address given to the one-port memories 44 to 47 depends on the mapping state of the two-dimensional logical address on the one-port memories 44 to 47. May be different.

  FIG. 18 is a diagram showing the correspondence between horizontal virtual addresses and real addresses. In the present invention, the total number of virtual banks is an integral multiple of the number of real banks (1-port memories 44 to 47). For this reason, the horizontal virtual address is cycled in such a way that the real address corresponding to the lowest one of the eight pixels cut out by the pixel rearrangement circuit 48 (hereinafter referred to as a representative real address) is within the range where the vertical virtual address is constant. If it is not the upper real address, add +1 to the representative real address, and if the representative real address is the highest real address within the fixed vertical virtual address range, This can be realized by replacing with the lowest real address.

  However, unlike the above example, if the total number of virtual banks is not an integral multiple of the number of banks of 1-port memory, 8 pixels stored in vertical logical address = 1 and horizontal logical address = 22-29 are simultaneously displayed. Cannot read. FIG. 19 shows a mapping state corresponding to FIG. 17 when the total number of logical banks is not an integral multiple of the number of banks of the 1-port memories 44 to 47.

  One port includes both vertical logical address = 1, horizontal logical address = 22 and 23 (logical bank number = 5), and vertical logical address = 1, horizontal logical address = 28 and 29 (logical bank number = 7). Since they are stored in the memory 46, the 8 pixels stored in the vertical logical address = 1, horizontal logical address = 22 to 29 (logical bank number = 5 to 7) cannot be read at a time. The reason why the eight pixels with consecutive horizontal logical addresses can always be read from the pseudo multi-port memory according to the present invention is because the total number of virtual banks is an integral multiple of the number of banks of the one-port memory.

  FIG. 20 shows a virtual one-dimensional address of the reference area 34. As shown in FIG. 11, the virtual one-dimensional address is an address assigned to the 1-port memories 44 to 47 in units of pixels, and 00 to 03, respectively, at addresses 0 of the 1-port memories 44, 45, 46, and 47. 04 to 07, 08 to 11, 12 to 15, and 1-port memories 44, 45, 46, and 47 are assigned as addresses 16 to 19, 20 to 23, 24 to 27, and 28 to 31, respectively. Since the reference area 33 is mapped to addresses 0 to 383 of the virtual one-dimensional address, the lowest virtual one-dimensional address (hereinafter referred to as a base address) of the reference area 34 is 384.

  As described above, in the present invention, a two-dimensional logical address is converted into a real address via a two-dimensional virtual address and a virtual one-dimensional address. First, a method for converting a two-dimensional logical address to a two-dimensional virtual address will be specifically described below.

If the inter-image distance from the image including the template to the image including each reference area is df, the number of pixels in the horizontal direction of the reference area including the update area and the empty area, that is, the horizontal virtual address size MAXX (df) Is
MAXX (df) = (2 × 8 × df + 4 × 4)
It becomes.

  Further, the virtual bank number of the current update area is assumed to be rvk (df). When the search for the motion vector of the current template is completed and the search for the motion vector of the next template on the right is started, rvk (df) increases by +1, but cycles in the range of 0 to (4 × df + 3) And

  In the present embodiment, rvk (df) is stored, and based on this, a two-dimensional logical address is converted into a virtual two-dimensional address. If the horizontal logical address is lxa (df) and the horizontal virtual address is vxa (df), it can be converted from lxa (df) to vxa (df) by the following equation.

vxa (df) = lxa (df) +4 {rvk (df) +3};
if vxa (df) ≧ MAXX (df)
vxa (df) = vxa (df) −MAXX (df);
However, 4 {rvk (df) +3} is an example of a method for calculating the difference between the horizontal virtual address and the horizontal logical address. For example, the virtual bank number corresponding to the logical bank with logical bank number = 0 is stored. Alternatively, the difference between the horizontal virtual address and the horizontal logical address may be calculated by multiplying the virtual bank number by the number of pixels in the horizontal direction of the virtual bank.

  Next, a method for converting a two-dimensional virtual address into a one-dimensional virtual address will be described. If ya (df) is a vertical virtual address (= vertical logical address) and BASE (df) is a base address in a reference area included in an image separated from the image including the template by an inter-image distance df, a horizontal virtual address vxa ( The virtual one-dimensional address vadr on the reference memory can be calculated from the following equation from df) and ya (df).

vadr = BASE (df) + vxa (df) + ya (df) × MAXX (df);
As described above, if the virtual bank number rvk (df) of the current update area is stored, the two-dimensional logical address (lxa (df), ya (df)) can be converted into the virtual one-dimensional address vadr. it can.

  The least significant 2 bits of the virtual one-dimensional address vadr are the pixel number pn (0-3) in the word of each bank in the pseudo multi-port memory, and the third and fourth bits counted from the least significant bit. The real bank number rb (0 to 3) and the higher order bits correspond to the real address ra.

  Finally, a method for generating a real address for each bank from the representative address, that is, the virtual one-dimensional address of the lowest one of the eight pixels cut out by the pixel rearrangement circuit 48 will be specifically described. When the representative address is vadr and the real bank number assigned to the 1-port memories 44 to 47 is bn, the real address ba (bn) given to the 1-port memories 44 to 47 is calculated by the following equation.

If (bn <rb) {
If (MAXX (df) −vxa (df) ≦ 16)
ba (bn) = ra-df;
else ba (bn) = ra + 1;
}
else ba (bn) = ra;
Here, (MAXX (df) −vxa (df) ≦ 16) is the lowest real address (hereinafter referred to as a representative real address) ra of the eight pixels cut out by the pixel rearrangement circuit 48, and its vertical logic. This means that the address ya (df) is the highest address in the real address range that may be converted.

  For example, in FIGS. 16 and 17, when reading 8 pixels of lxa (2) = 22 to 29 and ya (2) = 1, the representative real address is ra = 29. At this time, the real address range in which ya (2) = 1 may be converted is addresses 27 to 29, and ra = 29 is the highest address. In this case, the real bank number bn = 0 of the 1-port memory 44 is smaller than the real bank number rb = 2 of the lowest one of the 8 pixels cut out by the pixel rearrangement circuit 48. 0) = ra-df = 29-2 = The real address of address 27 is given.

  Of the 12 pixels read from the 1-port memories 44 to 47, 8 pixels are cut out by the pixel rearrangement circuit 48, and the lowest one of the 8 pixels cut out by the pixel rearrangement circuit 48 is output earliest. Rearranged and set in the shift registers 49-53.

  By reading out 8 pixels of horizontal logical addresses consecutively from the address specified by the two-dimensional logical address (lxa (df), ya (df)) by the above method and adjusting the output timing by the shift registers 49 to 53, the pseudo-multiple Five pixels can be output simultaneously from the port memory.

  In the above embodiment of the present invention, the template size is 4 pixels × 4 lines, and each search range for each screen is described as horizontal direction + 8 / −7 and vertical direction ± 4. However, the template has 8 pixels. A rectangular block such as × 4 lines or 8 pixels × 8 lines may be used, and the search range can be set arbitrarily in both the horizontal and vertical directions. However, when the number of pixels in the horizontal direction of the search range is not an integer multiple of the number of pixels in the horizontal direction of the template, the present invention is applied by expanding the search range so as to be an integer multiple of the number of pixels in the horizontal direction of the template. .

  In addition, the distance between the image that finally becomes the target of detecting the motion vector and the image including the template is not limited to three frames, but can be any number of frames.

  Furthermore, in the embodiment of the present invention described above, the virtual one-dimensional address having the lowest horizontal logical address among the 8 pixels cut out by the pixel rearrangement circuit 48 is used as the representative address. The virtual one-dimensional address having the highest horizontal logical address in the pixel may be used as the representative address.

  In this case, the real address having the highest horizontal logical address among the eight pixels extracted by the pixel rearrangement circuit 48 is within the real address range in which the vertical logical address ya (df) may be converted. 1 port memory having a real bank number larger than the real bank number obtained from the representative address is given a real address obtained by subtracting 1 from the real address obtained from the representative address. , One port having a real bank number larger than the real bank number obtained from the representative address when the vertical logical address ya (df) is the lowest real address in the real address range that may be converted In the memory, the vertical logical address ya (df) is the highest in the real address range that may be converted. Address is given.

  FIG. 21 is a diagram showing a configuration example of a pseudo multi-port memory device according to the present invention. The pseudo multi-port memory device includes n (n is a natural number) 1-port memories 44 to 47 having a word width capable of storing m pixels (m is a natural number), and an input horizontal logical address and vertical logical address as 1 An address conversion unit 100 that converts the real addresses of the port memories 44 to 47, a pixel rearrangement unit 200 that rearranges the pixels read from the 1-port memories 44 to 47, and a shift register or the like for the output timing of the rearranged pixels. Output timing adjusting means 300 for adjusting the output timing.

  The pixel rearrangement means 200 is constituted by the pixel rearrangement circuit 48 shown in FIG. 11 and is provided with m × n output from the n one-port memories 44 to 47 when the real address group is given by the address conversion means 100. The number of pixels is inputted, and the horizontal logical address given by the two-dimensional logical address assigning means 110 is set as the lowest horizontal logical address, and m × (n−1) or less having the continuous horizontal logical address on the upper side. Are rearranged in the ascending or descending order of the horizontal logical addresses and output.

  The output timing adjustment unit 300 includes a plurality of shift registers (for example, shift registers 49 to 53 in FIG. 11) each having a predetermined number of shift stages arranged in parallel to the pixel rearrangement unit 200. Are sequentially held in each shift register, and the output timing is adjusted by sequentially shifting out the plurality of pixels constituting each pixel group from each shift register. Desired pixels are simultaneously output in parallel.

  FIG. 22 shows a detailed configuration example of the address conversion unit 100 shown in FIG. The two-dimensional logical address assigning means 110 of the address conversion means 100 comprises a horizontal logical address register 111 that holds a horizontal logical address and a vertical logical address register 112 that holds a vertical logical address. The two-dimensional virtual address generation means 120 includes a horizontal virtual address generation circuit 121 that converts a horizontal logical address into a horizontal virtual address that is an integer multiple of m × n, and a horizontal virtual address register that holds the generated horizontal virtual address 122 and a vertical virtual address register 123 that holds a vertical logical address as a vertical virtual address as it is. The vertical virtual address register 123 may be omitted.

  The horizontal virtual address generation circuit 121 corresponds to a difference between a horizontal virtual address and a horizontal logical address based on a value (that is, a virtual bank number) that circulates in a range of 0 to (horizontal virtual address size / m−1). A value is calculated, and a value corresponding to the difference between the horizontal virtual address and the horizontal logical address is added to the horizontal logical address. If the result exceeds the horizontal virtual address size, the horizontal virtual address size is calculated from the result. By subtracting the length, the horizontal logical address is converted into a horizontal virtual address having an integer multiple of m × n.

  The virtual one-dimensional address generation means 130 includes a multiplier 131 that multiplies the horizontal virtual address and the vertical virtual address, a base address register 132 that holds a base address of an area to which the two-dimensional virtual address is assigned, and a horizontal virtual address. The adder 133 adds the address, the multiplication result of the multiplier 131, and the base address, and the virtual one-dimensional address register 134 that holds the output of the adder 133 as a virtual one-dimensional address.

  The representative real address generation means 140 includes a constant memory 141 that holds a value of m × n, a divider 142 that divides a virtual one-dimensional address by (m × n), and a representative real address that holds the quotient as a representative real address. And an address register 143. The representative real bank number generation means 150 also includes a constant memory 151 that holds the value of m, a divider 152 that divides the remainder of division output by the divider 142 by m, and the division result of the divider 152 as a representative real number. It consists of a representative real bank number 153 held as a bank number.

  The real address generation means 160 includes a real address generation circuit 161 that generates a real address to be given to each of the 1-port memories 44 to 47 from the representative real address and the representative real bank number. When the horizontal logical address given by the two-dimensional logical address assigning unit 110 is the lowest horizontal logical address, the real address generation circuit 161 may convert the representative real address into a vertical virtual address. When it is not the highest real address in a certain real address range, a one-port memory having a real bank number smaller than the representative real bank number is given a real address obtained by adding 1 to the representative real address, while the representative When the real address is the highest real address in the real address range to which the vertical virtual address may be converted, the 1-port memory having a real bank number smaller than the representative real bank number has no vertical virtual address. Gives the lowest real address in the real address range where the address may be translated.

  Further, the real address generation circuit 161, when the horizontal logical address given by the two-dimensional logical address assigning means 110 is the highest horizontal logical address, the representative real address is given as the vertical virtual address given first. 1 is subtracted from the representative real address for a 1-port memory having a real bank number larger than the representative real bank number when the real address is not the lowest real address in the real address range that may be converted When a real address is given, while the representative real address is the lowest real address in the real address range to which the first given vertical logical address may be converted, the representative real bank number For a 1-port memory having a larger real bank number, the vertical virtual address to which the representative real address is given first can be converted. Give the real address of the most significant in the real address range where there is a gender.

It is a figure which shows the structure of a motion vector detector. It is a figure which shows the example of the reference area | region of two adjacent templates. It is explanatory drawing which shows a telescopic search method. It is a figure which shows the example which parallelizes a difference absolute value sum calculator. It is a figure which shows the search area | region in the case of parallelizing a difference absolute value sum calculator. It is a figure which shows the block diagram of pseudo multi-port memory. It is a figure explaining the modulo addressing in the memory divided | segmented into 16 banks. It is a figure which shows the magnitude | size of the reference area of a telescopic search. It is a figure which shows the mapping of the reference area on a reference memory. It is a block diagram which shows the structure of a motion vector detector. It is a block diagram of a pseudo multi-port memory. It is a figure which shows a search area | region. It is a figure which shows the pixel supplied to 4 parallel difference absolute value sum calculation circuits. It is a figure which shows allocation of the two-dimensional logical address with respect to the pixel of a reference area, and the division | segmentation into a logical bank. It is a figure which shows one state which mapped the two-dimensional logical address of the reference area to the pseudo multi-port memory. It is a figure which shows the state by which the two-dimensional logical address was updated. It is a figure which shows the mapping to the pseudo multi-port memory of the pixel contained in a reference area. It is a figure which shows a response | compatibility with a horizontal virtual address and a real address. It is a figure which shows the mapping state in case the total number of logical banks is not the integral multiple of the number of banks of 1 port memory. It is a figure which shows the virtual one-dimensional address of a reference area. It is a figure which shows the structural example of the pseudo multi-port memory device by this invention. It is a figure which shows the example of the address conversion means shown in FIG.

Explanation of symbols

1,42 Motion vector detector 2,21,22,31,37,38,39,40 Difference absolute value sum calculation circuit 3,41 Minimum value detection circuit 4,36 Reference memory 5,43 External frame memory 6,14, 15, 16, 17 Image 7 Slice 8, 9 Template 10, 11, 33, 34, 35 Reference area 12 Update area 13 Rectangular block 18, 19, 20, 23, 24, 54, 55, 56, 57 Search area 25, 26, 44, 45, 46, 47 1-port memory 27, 28, 29, 49, 50, 51, 52, 53 Shift register 30, 48 Pixel rearrangement circuit 32 Template B1 Interbank address B2 In-bank address B3 Bank number 100 Address conversion means 110 Two-dimensional logical address assignment means 120 Two-dimensional virtual address generation means 130 Temporary 1-dimensional address generating means 140 representative real address generation means 150 representative actual bank number generating section 160 real address generation means 200 pixel rearrangement unit 300 output timing adjusting means

Claims (4)

A pseudo multi-port memory device capable of simultaneously reading a plurality of pixels from unrelated addresses,
n (n is a natural number) 1-port memory having a word width capable of storing m (m is a natural number) pixels;
Two-dimensional logical address assigning means for giving a two-dimensional logical address composed of a finite size horizontal logical address and a finite size vertical logical address;
Two-dimensional virtual address generation for generating a two-dimensional virtual address by converting the horizontal logical address into a horizontal virtual address having an integer multiple of m × n and converting the vertical logical address into a vertical virtual address as it is Means,
By adding the base address of the area to which the two-dimensional virtual address is allocated, the horizontal virtual address, and a value obtained by multiplying the vertical virtual address by the horizontal virtual address, the n one-port memories are added. Virtual one-dimensional address generation means for generating a virtual one-dimensional address assigned in pixel units;
Representative real address generating means for generating a representative real address by dividing the virtual one-dimensional address by (m × n);
Representative real bank number generating means for generating a representative real bank number by further dividing the remainder obtained by dividing the virtual one-dimensional address by (m × n) by m;
Real address generating means for generating a real address to be given to each one-port memory from the representative real address and the representative real bank number;
When the real address group is given, m × n pixels or less outputted from the n one-port memories are inputted, and the horizontal logical address given by the two-dimensional logical address assigning means is the lowest horizontal In the case of a logical address, m × (n−1) or less pixels having continuous horizontal logical addresses on the upper side are rearranged in the ascending or descending order of the horizontal logical address, or the two-dimensional logic is output. If the horizontal logical address given by the address assigning means is the highest horizontal logical address, m × (n−1) or less pixels having consecutive horizontal logical addresses on the lower side are assigned to the horizontal logical address. Pixel rearrangement means for rearranging and outputting in ascending or descending order;
A plurality of shift registers each having a predetermined number of shift stages arranged in parallel to the pixel rearranging means, each of the pixel groups sequentially output from the pixel rearranging means is held in each shift register, and each pixel group The output timing is adjusted by sequentially shifting and outputting a plurality of pixels constituting each pixel from each shift register, and output timing adjusting means for simultaneously outputting desired pixels from each shift register in parallel is provided. A pseudo multi-port memory device. The pseudo multi-port memory device according to claim 1,
The two-dimensional virtual address generation means calculates a value corresponding to a difference between the horizontal virtual address and the horizontal logical address based on a value that circulates in a range from 0 to (horizontal virtual address size / m−1). , Add a value corresponding to the difference between the horizontal virtual address and the horizontal logical address to the horizontal logical address, and if the result exceeds the size of the horizontal virtual address, subtract the size of the horizontal virtual address from the result Thus, the pseudo multi-port memory device is characterized in that the horizontal logical address is converted into a horizontal virtual address having an integer multiple of m × n. The pseudo multi-port memory device according to claim 1 or 2,
The real address generating means
When the horizontal logical address given by the two-dimensional logical address assigning means is the lowest horizontal logical address, the representative real address is in the real address range in which the vertical virtual address may be converted. 1 port memory having a real bank number smaller than the representative real bank number is given a real address obtained by adding 1 to the representative real address, while the representative real address is When the vertical virtual address is the highest real address in the real address range that can be converted, the vertical virtual address is converted to a 1-port memory having a real bank number smaller than the representative real bank number. Give the lowest real address in the real address range that can be
When the horizontal logical address given by the two-dimensional logical address assigning means is the highest horizontal logical address, the representative real address may be converted to the vertical virtual address given first. When it is not the lowest real address in the address range, a 1-port memory having a real bank number larger than the representative real bank number is given a real address obtained by subtracting 1 from the representative real address, while the representative 1 port having a real bank number larger than the representative real bank number when the real address is the lowest real address in the real address range to which the first given vertical logical address may be converted The memory contains the highest virtual address in the real address range to which the vertical virtual address given the representative real address first may be converted. Pseudo multi-port memory device which is a real address generation means for providing a real address. A pixel reading method stored in a pseudo multi-port memory device having n (n is a natural number) 1-port memory having a word width capable of storing m (m is a natural number) pixels,
A process of inputting a two-dimensional logical address consisting of a finite size horizontal logical address and a finite size vertical logical address;
Generating a two-dimensional virtual address by converting the horizontal logical address into a horizontal virtual address having an integer multiple of m × n, and converting the vertical logical address into a vertical virtual address as it is;
By adding the base address of the area to which the two-dimensional virtual address is allocated, the horizontal virtual address, and a value obtained by multiplying the vertical virtual address by the horizontal virtual address, the n one-port memories are added. Generating a virtual one-dimensional address assigned in pixel units;
Generating a representative real address by dividing the virtual one-dimensional address by (m × n);
A process of generating a representative real bank number by further dividing the remainder obtained by dividing the virtual one-dimensional address by (m × n) by m;
A process of generating a real address to be given to each one-port memory from the representative real address and the representative real bank number;
When the real address group is given and m × n pixels or less output from the n one-port memories are input, and the input horizontal logical address is the lowest horizontal logical address, Output not more than m × (n−1) pixels having consecutive horizontal logical addresses on the upper side in ascending or descending order of horizontal logical addresses, or the input horizontal logical address is the highest horizontal logic If it is an address, a process of rearranging and outputting m × (n−1) or less pixels having consecutive horizontal logical addresses on the lower side in ascending or descending order of the horizontal logical addresses;
The pixel groups that are sequentially rearranged are sequentially held by a plurality of shift registers each having a predetermined number of shift stages, and the plurality of pixels constituting each pixel group are sequentially shifted and output from each shift register. A method of reading out a pixel of a pseudo multi-port memory device, comprising: adjusting a timing and simultaneously outputting a desired pixel from each shift register in parallel.

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