JP4333538B2 - 電子部品の実装方法 - Google Patents
電子部品の実装方法 Download PDFInfo
- Publication number
- JP4333538B2 JP4333538B2 JP2004269539A JP2004269539A JP4333538B2 JP 4333538 B2 JP4333538 B2 JP 4333538B2 JP 2004269539 A JP2004269539 A JP 2004269539A JP 2004269539 A JP2004269539 A JP 2004269539A JP 4333538 B2 JP4333538 B2 JP 4333538B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- electronic component
- reflow
- substrate
- mounting method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Description
図1は、本発明の第1実施形態に係る電子部品の実装構造の概略断面構成を示す図である。
本実施形態の種々の変形例を示しておく。
上記第1実施形態にて述べた実装方法を採用すれば、はんだリフロー時におけるはんだ20の飛散を適切に抑制することができるが、完全に抑制することはなかなか難しい。
図8は、本実施形態の第1の変形例を示す概略断面図である。はんだ20とランド40との間を保護キャップにより遮断することは、図8に示されるように、ランド40側を覆うように保護キャップ300を設けてもよい。はんだ20(電子部品30)とランド40とが近すぎて、はんだ20側に保護キャップが置けないような場合に有効である。
Claims (2)
- 基板(10)上に電子部品をはんだ(20)を介して搭載した後、前記はんだ(20)をリフローさせることにより、前記基板(10)上に前記電子部品(30)をはんだ付けするようにした電子部品の実装方法において、
前記リフロー工程では、前記はんだ(20)中に含まれる水分の蒸発温度を上昇させるために不活性ガス雰囲気中で加圧した状態で前記はんだ(20)のリフローを行うものであり、
前記加圧した状態とは、前記蒸発温度がリフロー最高温度と同じ温度となるような圧力を印加するものであることを特徴とする電子部品の実装方法。 - 前記不活性ガスは窒素ガスであることを特徴とする請求項1に記載の電子部品の実装方法。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004269539A JP4333538B2 (ja) | 2004-09-16 | 2004-09-16 | 電子部品の実装方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004269539A JP4333538B2 (ja) | 2004-09-16 | 2004-09-16 | 電子部品の実装方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006086330A JP2006086330A (ja) | 2006-03-30 |
| JP4333538B2 true JP4333538B2 (ja) | 2009-09-16 |
Family
ID=36164582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004269539A Expired - Fee Related JP4333538B2 (ja) | 2004-09-16 | 2004-09-16 | 電子部品の実装方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4333538B2 (ja) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009212431A (ja) * | 2008-03-06 | 2009-09-17 | Seiko Epson Corp | リフロー装置及び半導体装置の製造方法 |
| EP3163601B1 (en) * | 2009-01-23 | 2020-03-11 | Nichia Corporation | Method of producing a semiconductor device by directly bonding silver on a surface of a semiconductor element with silver oxide on a surface of a base |
-
2004
- 2004-09-16 JP JP2004269539A patent/JP4333538B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006086330A (ja) | 2006-03-30 |
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