JP4334041B2 - Manufacturing method of optical semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an optical semiconductor device and an optical semiconductor module on which the optical semiconductor device is mounted, and in particular, prevents resistance value fluctuations and semiconductor chip cracks caused by stress applied to a resistor incorporated in the optical semiconductor device. .
[0002]
[Prior art]
In general, in order to improve the degree of integration of semiconductor devices, the density and size of elements are increased, and the packages tend to be smaller and thinner. However, when a large element is sealed with a conventional resin, a crack is generated on the surface of the element, and a crack is also generated in the resin as the thickness is reduced. Even in the state where no crack is generated, the IC circuit is distorted, and particularly the resistance value fluctuates greatly.
[0003]
Therefore, for example, as disclosed in JP-A-57-56854, a filler is mixed in the resin sealing body. This filler is a rubber particle in this publication, but in addition, inorganic fillers such as glass fiber, glass particle (powder), and quartz glass particle (powder) are also employed, and crack resistance and resistance value fluctuation resistance Is increasing.
[0004]
On the other hand, multimedia devices such as sub-notebook computers, personal digital assistants, and electronic still cameras have made remarkable progress. Especially, 7 million mobile devices are sold annually, and about 80% are infrared based on IrDA (Infrared Data Association) standards. The method is adopted. In other words, transmission / reception between the external device and the main body via an infrared signal is required, and a light emitting element for emitting infrared light and a light receiving element for receiving infrared light have been required.
[0005]
For example, as a light emitting element, Japanese Patent Laid-Open No. 5-145120 is detailed.
As a light receiving element, there is a photodiode IC shown in FIG.
[0006]
In this IC chip 10, a light receiving area 11 made of a PIN photodiode is formed in one area of the chip, and an IC area 12 in which a driving circuit for driving the photodiode is mounted is formed in another area. And it adheres on the island 13 which comprises a lead frame via solder, silver paste, etc., and the whole is sealed with the resin sealing body 14. FIG.
[0007]
The sealing body 14 is made of a resin material having transparency to predetermined light, for example, a transparent epoxy resin.
[0008]
FIG. 8 shows a package adopted for IrDA. The left chip is an optical IC chip 10 and the right chip 15 is a light emitting element such as a light emitting diode or a laser diode. However, when a laser diode is used, the side emission of the chip is required and the side of the chip needs to face up.
[0009]
[Problems to be solved by the invention]
In the module described above, if the filler 16 is mixed into the sealing resin in consideration of cracks in the sealing resin and cracks in the chip, the incident light 17 and the emitted light 18 are scattered. There is a problem that the transmittance of the light 17 is lowered and the light receiving intensity is lowered. Therefore, there is a problem that high-precision detection cannot be performed when light with low intensity is incident. Further, in the light emitting diode 15, the emitted light 18 is scattered in the resin sealing body, the intensity of the emitted light is lowered, and there is a problem that the light cannot be emitted far away.
[0010]
For this reason, it is necessary not to mix the filler 16 in the sealing resin or to reduce the mixing rate, but this time, the resin stress increases, and the resistor constituting the driving circuit of the IC chip. There is a problem that the value of fluctuates greatly and cracks occur in the chip.
[0011]
[Means for Solving the Problems]
The present invention has been made in view of the above-described problems, and the resistors constituting the driving circuit are arranged in a direction intersecting with the side of the chip at 45 degrees, and the semiconductor chip is back-ground by the one-pass method. It is solved by being.
[0012]
The resistor is solved by arranging the orientation flat on the (100) plane wafer so that the orientation flat is the [011] axis and intersects the axis at 45 °.
[0013]
Further, the filler mixing rate of the first resin sealing body is made smaller than the filler mixing rate of the second resin sealing body, and the resistor constituting the driving circuit is crossed at 45 degrees with respect to the side of the chip. The semiconductor chip is solved by being back-ground by the one-pass method.
[0014]
In order to improve the light transmittance, the filler mixing rate is reduced or zero, and even when the stress generated in the sealing resin is increased, the resistor 20 is disposed obliquely as shown in FIG. 1 or FIG. The rate of change of the resistance value can be reduced, and the wafer is shaved with a one-pass back grind so that the orientation flat [011] axis and the shaving are substantially parallel to each other, and the longitudinal direction of the chip and the one-pass shaving The cracks can be suppressed by making them substantially parallel.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
[0016]
FIG. 1 shows an optical semiconductor IC chip, in which a photodiode (or a phototransistor) and a circuit for calculating this output are incorporated. Alternatively, a drive circuit for driving as a predetermined circuit including the optical semiconductor device is incorporated.
[0017]
This semiconductor chip is realized by, for example, a BIP-IC. This consists of a P-type semiconductor substrate and at least one N-type epitaxial layer (or N-type or P-type) stacked on this substrate. In particular, the N type epitaxial layer includes a plurality of island regions surrounded by P + type isolation regions reaching the semiconductor substrate. Each island region includes a photodiode, a transistor, a diode, a capacitor, a diffused resistor, and the like. Is built.
[0018]
The N-type island region where the photodiode is formed and the P-type semiconductor substrate constitute a PN-type photodiode, which is reverse-biased at a predetermined voltage, and when irradiated with light, a photocurrent is generated according to the amount of light. It is flowing. Reference numeral 11 denotes a region where the photodiode is formed.
[0019]
On the other hand, the IC region 12 indicated by a dotted line is formed with a photodiode operation or drive circuit, and is mainly composed of NPN, PNP type transistors, diodes, resistors (diffusion resistors and poly-Si resistors), capacitors, and the like.
[0020]
In FIG. 1, the area excluding the light receiving unit 11 is composed of blocks A to K indicated by dotted lines, and a function of filtering light of a specific frequency is built in. In particular, although the detection circuit is employed, the resistors 20 of the zapping circuit that realizes the improvement of the accuracy of the detection circuit are concentrated in the block J. Here, only the resistor 20 is schematically shown. The present invention resides in this resistor 20.
As described with reference to FIG. 8, the filler 16 is mixed in the resin sealing body 14 of the conventional semiconductor device in order to relieve stress and prevent cracks in the resin and the chip. However, when packaging is performed with the resin mixed with the filler 16, the filler causes light scattering. Therefore, it is preferable that the optical IC contains as little filler as possible or removes all of it.
[0021]
However, it was found that if the mixing rate of the filler is reduced or eliminated at all, the stress generated from the sealing resin 14 increases, and the value of the resistor 20 formed in the IC region 12 in FIG. .
[0022]
Therefore, as shown in FIG. 1, the direction of the resistor 20 is inclined by 45 degrees with respect to the sides 30 and 31 of the chip. It has been found that this arrangement can suppress the fluctuation of the resistance value even if the mixing ratio of the filler in the sealing resin is reduced (or made zero).
[0023]
9 and 10 show the results of this experiment. Resistors ad shown in FIG. 9 indicate the direction of the resistor. The upper side 30 and the lower side 31 of the chip are formed in parallel with the orientation flat [011] axis in the (100) plane wafer.
[0024]
Resistors a and b: Conventional resistors arranged in parallel to the sides 30 and 31 of the IC chip 10. The pattern size is 400 μm long and 10 μm wide. The former is arranged in parallel to the [011] axis of the orientation flat, and the latter is arranged at a right angle.
[0025]
Resistors c and d: Resistors of the present invention that intersect at 45 degrees with respect to the side of the chip (side parallel to the orientation flat [011] axis). The pattern size is 200 μm long and 10 μm wide.
[0026]
Further, FIG. 9 shows only the relationship between the resistor and the chip side. Actually, a large number are formed as shown in the IC region of FIG. In FIG. 1, an N-type epitaxial layer is formed on a P-type substrate, and a P + type isolation region that reaches the P-type substrate from this epitaxial layer is formed. A plurality of oblique diffusion resistors indicated by c and d in FIG. 9 are formed in the N type island region surrounded by the isolation region.
[0027]
The experimental results are shown in FIG. Resistors a to d are resistors shown in FIG. (1) shown in the resistance position column is arranged at the center of the chip, and (2) is arranged at the periphery of the chip. Moreover, the numerical value shown on the right side of the column of samples 1-18 shows a change rate,
The change rate (%) is obtained by dividing (resistance value after assembly−resistance value in the wafer state) by the resistance value in the wafer state and multiplying by 100.
[0028]
In the experiment, the resistance value was measured in the wafer state in which the above-mentioned diffusion resistance was made, and then scribed, and both ends of each resistance were bonded to Au and 30 μmφ wires, and then connected to the lead terminal, and then sealed with resin And then measured.
[0029]
X is an average obtained by adding a plus or minus value as it is and dividing by the number of samples. σ is a standard deviation.
As can be seen from the figure, the resistors c and d arranged at an angle of 45 degrees are smaller by one to two digits. Further, in a and b, the rate of change was smaller in the peripheral portion of the chip than in the central portion of the chip.
[0030]
Returning to FIG. 1, when only the resistor 20 is disposed obliquely in the IC region 12, the other elements are in the same direction as the upper side or the left and right sides of the chip, so that a dead space is generated only in the resistor portion. . Therefore, when the mixing ratio of the filler of the sealing resin is reduced or eliminated as an optical semiconductor device, an IC chip that requires accuracy is an IC in which resistors are arranged obliquely and the shrinkage of the chip is more important than accuracy. The change rate of the chip can be suppressed by disposing a resistor around the chip.
[0031]
Also, as described above, the orientation flat employed when manufacturing the optical semiconductor device is the [011] axis in the (100) wafer, and FIG. 11 in which the resistors are arranged obliquely with respect to this axis is appropriate. It was found that the arrangement of FIG.
[0032]
If the latter positional relationship of FIG. 12 is employed, semiconductor elements such as transistors and resistors can be arranged in a direction parallel to or perpendicular to the side of the chip, so that chip mounting efficiency is good. However, when this is adopted, there is a problem that chip chipping occurs after molding.
There were two causes. When the wafer surface is (100) and the orientation flat is the [011] axis, the cleavage direction is parallel to or perpendicular to the [011] axis. Accordingly, as shown in (1) in FIG. 12, when the scribe line 50 obliquely intersects the [011] axis direction, chipping occurs at the corners of the chip.
[0033]
{Circle around (2)} When the scratch generated in the back grind crosses the [011] axis obliquely, the strength is lost.
The results are shown in FIGS.
[0034]
As shown in FIG. 11, a (100) plane wafer whose orientation flat axis is the [011] axis is adopted, and a chip obtained by dicing the orientation flat horizontally and at a right angle is Jst. As shown in FIG. A wafer having an orientation flat that obliquely intersects with the 11 orientation flat axes was adopted, and a chip obtained by dicing the orientation flat horizontally and at a right angle was shown as 45 °. Then, as shown in FIG. 3, a fulcrum was provided, and a load (0 to 4.5 Kgf) was applied from above as indicated by an arrow to measure the strength.
[0035]
The chip 32 has a size of 6 × 6 mm and 4 × 4 mm, and the interval between the fulcrums 33 and 34 is 3 mm. The load application speed is 10 mm / min. It is.
FIG. 2 shows a strength test by half-cutting by dicing and breaking through the half-cut groove to form a chip.
[0036]
As is apparent from the figure, Jst was found to be stronger than 45 °. This is because, when breaking, a force is applied along the cleavage direction shown in FIG. 11, whereas at 45 °, the direction of the force applied to the breaking is oblique with respect to the cleavage direction, and fine cracks are generated. It is assumed that the chip enters the chip and the chip is broken by the stress after sealing.
[0037]
FIG. 4 also includes the backgrinding method. One is a one-pass method and the other is an in-feed method.
[0038]
5 and 6, the former one-pass method is such that the turntable 40 rotates at a speed of R1, the scriber 41 rotates at R2, and the wafer 42 rotates completely on the turntable 40. It is something that does not. When back grinding is performed by this method, as shown in FIG. 5 and the wafer 42a, the streaks (grooves generated in the back grinding) substantially coincide with the orientation flat direction.
[0039]
In the latter in-field method, the turntable 40 rotates at a speed of R1, the scriber 41 rotates at R2, and the wafer 42 also rotates on the turntable 40 at R3. When backgrinding is performed by this method, as shown in FIG. 5 and the wafer 42b, the streaks are formed in a radial and spiral shape, and the portion that coincides with the direction of the orientation flat is only one region.
[0040]
The experimental results are shown in FIG. In other words, it was found that Jst was stronger as in FIG. 2, and that the one-pass method (groove 42a in FIG. 5) was stronger. In other words, the grooves generated by the in-field method remaining on the back surface of the chip often coincide with the cleavage direction, and it is considered that chipping occurs due to the shrinkage distortion of the resin.
[0041]
In summary, when an epoxy resin, for example, is used as a sealing material for an optical IC and the filler is reduced or eliminated completely to prevent light scattering, the stress at the time of resin shrinkage increases. This generates resistance fluctuations and chip chipping. Therefore, the resistors are arranged obliquely as shown in FIG. 11, and the back grind is a one-pass method so that the groove is substantially parallel to the [011] direction, and the [011] axis and the longitudinal direction of the chip are set as much as possible. It is important to match.
[0042]
On the other hand, in FIGS. 7 and 8, the lens 21 is arranged right above the chip, but this is only an example, and the shape and position of the lens are arbitrary. The present invention can be applied to all cases where a resin transparent to light is employed.
[0043]
Subsequently, a mounting form will be described. As the mounting means, a printed board, a flexible board, a ceramic board, a metal board, and the like are conceivable, and a copper pattern, for example, is formed thereon. Then, another semiconductor device is mounted in this pattern for the present optical semiconductor device and a circuit configuration including the same. That is, the filler mixing rate of the present optical semiconductor device is smaller than the filler mixing rate of other semiconductor devices.
[0044]
【The invention's effect】
According to the present invention, the resistors constituting the driving circuit are arranged in a direction intersecting at 45 degrees with respect to the side of the chip, so that the resistance of the resistor generated even if the mixing ratio of the feeler is reduced or zero. The resistance value change rate can be suppressed. In addition, shrinkage distortion occurs by reducing the filler mixing rate, but chipping can be prevented by using the back grind as a one-pass system.
[0045]
Accordingly, attenuation or diffuse reflection of incident or emitted light can be suppressed, the light transmittance can be improved, the light emitted from the optical semiconductor device can be further distant, and the intensity of the incident light can be increased. Furthermore, in the optical IC, a circuit for detecting only a specific frequency is provided, and a zapping circuit is employed to further improve the detection accuracy. Therefore, an oblique resistor which is the point of the present invention is disposed here. It is possible to improve the accuracy of light detection (filtering). In addition, the yield can be improved by the one-pass method.
[Brief description of the drawings]
FIG. 1 is a plan view of an optical semiconductor device according to an embodiment of the present invention.
FIG. 2 is a diagram showing experimental results of chip strength.
FIG. 3 is a diagram for explaining a chip strength test method;
FIG. 4 is a diagram showing experimental results of chip strength.
FIG. 5 is a diagram for explaining scratches that occur in back grinding.
FIG. 6 is a diagram illustrating a back grinding method.
FIG. 7 illustrates an optical semiconductor device.
FIG. 8 illustrates an optical semiconductor device.
FIG. 9 is a diagram illustrating an experimental method for examining a change rate of a resistor.
10 is a diagram for explaining an experimental result according to FIG. 9; FIG.
FIG. 11 is a diagram illustrating a positional relationship between an orientation flat and a resistor.
FIG. 12 is a diagram illustrating a positional relationship between an orientation flat and a resistor.

Claims (2)

At least one N-type epitaxial layer provided on the P-type semiconductor substrate, a P-type isolation region formed to reach the semiconductor substrate from the epitaxial layer, and a plurality of regions surrounded by the isolation regions A photodiode, a transistor, a diode, a capacitor, and a diffused resistor are formed in the N-type island region and the island region. The first region where the photodiode is formed is used as a light receiving region, and the second region is used as the light receiving region. provided as a drive circuit of the light receiving region, a rectangular semiconductor chip made of four sides, the semiconductor chip sealed, not contaminated fillers that cause scattering of light, transparent resin to the light Having a sealing body,
In the method of manufacturing an optical semiconductor device in which the light enters the resin sealing body from the outside and enters the light receiving region, and is processed by the drive circuit.
The drive circuit includes a detection circuit, and a resistor of a zapping circuit for improving the accuracy of the detection circuit is concentrated on the block, and the resistor requiring the accuracy is connected to the side of the chip. Te is disposed in a direction intersecting at 45 degrees, if it is desired shrink than the accuracy, the resistor, the periphery of the semiconductor chip located inside the said four side edges outside from the center of the rectangular semiconductor chip The semiconductor chip is provided in the same direction as the four sides, the back surface of the semiconductor chip is back-ground by a one-pass method, and the groove on the back surface of the semiconductor chip formed by the back-grind is formed with the side edge of the semiconductor chip. An optical semiconductor device manufacturing method characterized by being substantially parallel to a parallel direction.   2. An optical semiconductor device according to claim 1, wherein in the (100) plane wafer, the orientation flat is arranged in the [011] axis direction, and the resistors are arranged in a direction intersecting at 45 degrees with respect to the axis. Method.

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