JP4334175B2 - Non-volatile storage medium - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile storage medium, and more particularly to a nonvolatile storage medium in which a main memory array and an additional memory array are directly connected.
[0002]
[Prior art]
A recent nonvolatile storage medium includes a so-called additional memory array in addition to a conventional main memory array. The additional memory array is completely similar in structure to the main memory array, and is an alternative to storage elements that are found to be ineffective in the main memory array. Therefore, such a non-volatile storage medium can tolerate a relatively large manufacturing defect when manufacturing the storage element of the main memory array, so that the yield of the entire non-volatile storage medium can be increased.
[0003]
FIG. 1 is a block diagram showing the structure of a conventional nonvolatile storage medium 10. The nonvolatile storage medium 10 is manufactured on a base (not shown) of a semiconductor chip. The nonvolatile storage medium 10 includes a peripheral circuit area 20 and a memory array area 50, and the memory array area 50 includes a main memory array 60 and an additional memory array 80. The peripheral circuit area 20 includes an address buffer 22, an addressable memory unit 24 that stores address data of storage elements that are not valid in the main memory array 60, a main memory array ground line decoder 26, and a main memory array 60. A plurality of ground lines GL electrically connected to the main memory bit line decoder 27, the additional memory array ground line decoder 28, and a plurality of ground lines RGL electrically connected to the additional memory array 80. And an additional memory array bit line decoder 29.
[0004]
Each bit line BL, RBL is electrically connected to the pass transistor, and the main memory array bit line decoder 27 is electrically connected to the gate electrode of the pass transistor, and the additional memory array bit line. The decoder 29 is also electrically connected to the gate electrode of the pass transistor to electrically connect the respective bit lines BL and RBL to the data line.
[0005]
  FIG. 2A illustrates the structure of the memory array region 50 of the conventional nonvolatile storage medium 10, and FIG. 2B illustrates the circuit of the memory array region 50 of the conventional nonvolatile storage medium 10. The nonvolatile storage medium 10 is provided on the base part 42 of the semiconductor chip 40.The memory array 50 includes a main memory array 60 and an additional memory array 80, and is provided between the main memory array 60 and the additional memory array 80 to isolate the main memory array 60 and the additional memory array 80. A field oxide layer 70 ofIt includes two dummy memories provided on both sides of the field oxide layer 70 for isolating the main memory array 60 and the additional memory array 80 so as not to affect the main oxide array 60 in the manufacturing process of the field oxide layer 70.
[0006]
The main memory array 60 has M bit lines BL₁~ BL_MAnd M + 1 ground lines GL₁~ GL_{M + 1}And a plurality of memory cells. Each memory cell includes a source 54 and a drain 56, is formed in the base 42 of the semiconductor chip 40, and a gate electrode 58 is formed on the base 42. Each ground line GL is electrically connected to the sources 54 of a predetermined number of memory cells in the main memory array 60, and each bit line BL is connected to the drains of a predetermined number of memory cells in the main memory array 60. 56. Of the M + 1 ground wires, GL₂~ GL_MIs used to operate both adjacent memory cells, and the ground line GL₂~ GL_MIs shared with both adjacent memory cells. Also, ground line GL₁And GL_{M + 1}Can only operate on one adjacent memory cell. Also, BL₁~ BL_MIs used to operate the adjacent memory cells. That is, bit line BL₁~ BL_{M + 1}Is shared with both adjacent memory cells.
[0007]
The additional memory array 80 includes N bit lines RBL.₁~ RBL_NN + 1 ground lines RGL₁~ RG_{LN + 1}And a plurality of memory cells. Each memory cell includes a source 54 and a drain 56 and is formed in the base 42 of the semiconductor chip 40, and a gate electrode 58 is provided on the base 42. Each ground line RGL is electrically connected to a source 54 of a predetermined number of memory cells in the additional memory array 80, and each bit line RBL is connected to a drain of a predetermined number of memory cells in the additional memory array 80. 56 is electrically connected. Of the N + 1 ground wires, RGL₂~ RGL_NIs used to operate the adjacent memory cells. That is, the ground line RGL₂~ GL_NIs shared with both adjacent memory cells. Also, ground line RGL₁And RGL_{N +1}Can only operate on one adjacent memory cell. RBL₁~ RBL_NIs used to operate the adjacent memory cells. That is, the bit line RBL₁~ RBL_MIs shared with both adjacent memory cells.
[0008]
  As shown in FIG. 2B, when an operation is performed on the memory cell M2 in the non-volatile storage medium 10, addresses are first arranged on the ground line GL2, the bit line BL1, and the word line WL1, and the memory cell Source54And the drain56And the gate electrode58Can be controlled separately to advance the operation of the memory cell M2. The address buffer 22 sends address signals to the addressable memory unit 24, the main memory array ground line decoder 26, the main memory bit line decoder 27, the additional memory array ground line decoder 28, and the additional memory array bit line decoder 29. In contrast, an address signal is output. The main memory array ground line decoder 26 decodes based on the address signal and performs address arrangement on the ground line GL2. The main memory array bit line decoder 27 decodes based on the address signal, activates (turns on) each pass gate, and performs address arrangement on the address bit line BL1. The address arrangement method of the word line WL1 is performed in a similar manner based on the same principle.
[0009]
If the address signal transmitted is coincident with the address stored in the addressable memory unit 24, the addressable memory unit 24 generates a sign signal to generate an additional memory array ground line decoder 28 and an additional memory array bit line decoder 29. Turn on. The additional memory array ground line decoder 28 performs decoding based on the address signal output from the address buffer 22 and performs address arrangement of the additional ground line. The additional memory cell bit line decoder 29 outputs the address signal output from the address buffer 22. And turn on the pass gates to place addresses in the additional bits.
[0010]
In the memory array area of the conventional nonvolatile storage medium 10, a field oxide layer is mainly provided between the main memory array 60 and the additional memory array 80, and two dummy memories are provided on both sides of the field oxide layer. By providing, the main memory array 60 and the additional memory array 80 are separated. However, providing the field oxide layer and the dummy memory 72 that cannot store data increases the layout area of the memory array area 50. Therefore, when designing to reduce the size in the manufacture of semiconductors, it is important to reduce the area occupied by the field oxide layer and the dummy memory 72 to increase the use efficiency of the layout area of the memory array region. It becomes a difficult task.
[0011]
[Problems to be solved by the invention]
An object of the present invention is to provide a non-volatile storage medium capable of improving the use efficiency of the layout area of the memory array region and effectively reducing the size of the semiconductor.
[0012]
[Means for Solving the Problems]
Therefore, the present inventor has conducted intensive research in view of the drawbacks found in the prior art, and paid attention to the structure of the non-volatile storage medium having a virtual ground array structure in which the main memory array and the additional memory array are merged. Based on the above, the present invention has been developed.
[0013]
That is, the present invention removes the field oxide layer for separating the main memory array from the additional memory array and the dummy memory, connects the main memory array directly to the additional memory array, and adopts a virtual ground array structure. did. The main memory array region and the additional memory array region each include a plurality of memory cells, a plurality of bit lines, and a plurality of ground lines, and each of the memory cells is within the base of the semiconductor chip. The common source and the common drain formed in each of the bit lines are electrically connected to the drains of a predetermined number of memory cells provided in the main memory array or the additional memory array. Each ground line is configured to be electrically connected to a source of a predetermined number of memory cells provided in the main memory array or the additional memory array.
[0014]
  According to the inventionThe nonvolatile storage medium is a nonvolatile storage medium provided on the base of the semiconductor chip, and includes a main memory array, an additional memory array directly connected to the main memory array, and a shared source. The main memory array includes at least one memory cell including a source and a drain provided in a base of the semiconductor chip, at least one bit line electrically connected to the drain of the memory cell, And at least one ground line electrically connected to the source of the memory cell. The additional memory array includes an additional memory cell including an additional source and an additional drain provided in the base of the semiconductor chip, and at least one additional bit line electrically connected to the additional drain of the additional memory cell. And at least one additional ground line electrically connected to an additional source of the additional memory cell,The shared source is a main source and an additional source at a position where the main memory array and the additional memory array are in contact with each other..
[0015]
  AboveThe nonvolatile storage medium further includes a peripheral circuit area, and the peripheral circuit area includes a main memory ground line decoder electrically connected to the ground line of the main memory array, and an additional ground line electrically connected to the additional memory array. And an additional memory ground line decoder connected to each other, and at least two signal transmission lines, and both ends of the signal transmission line are electrically connected to the main memory ground line decoder and the additional memory ground line decoder, respectively. To do.
[0016]
  AboveWhen the shared source is electrically connected to the shared ground line, and the main memory ground line decoder performs address arrangement on the shared ground line, the main memory ground line decoder is connected to the additional memory ground line decoder via the signal transmission line. A signal is transmitted to determine the voltage of the shared ground line, and an electrical connection between the shared ground line and the additional memory ground line decoder forms an open circuit, the additional memory ground line decoder The additional memory ground line decoder transmits a signal to the main memory ground line decoder via another signal transmission line to determine the voltage of the shared ground line, and An electrical connection between the shared ground line and the main memory ground line decoder is configured to form an open circuit state.
[0017]
  AboveThe main memory ground line decoder includes a sub-decoder electrically connected to the common ground line, and the sub-decoder includes a three-input NAND gate that receives an address signal, an inverter, and a three-mode inverter. The input terminal of the inverter is electrically connected to the output terminal of the three-input NAND gate, and the control terminal of the three-mode inverter is connected to the common ground line in the additional ground line decoder. -Electrically connected to the output terminal of the 4-input NAND gate of the decoder. In the additional memory ground line decoder, the sub-decoder electrically connected to the common ground line includes a 4-input NAND gate that receives an address signal and a sign signal, an inverter, and a three-mode inverter. The input terminal of the inverter is electrically connected to the output terminal of the 4-input NAND gate, and the control terminal of the three-mode inverter is electrically connected to the common ground line in the main memory ground line decoder. It is electrically connected to the output terminal of the 3-input NAND gate of the decoder.
[0018]
  AboveWhen a shared source is electrically connected to the shared ground line, and the main memory ground line decoder performs address allocation on the shared ground line, the main memory ground line decoder sends a signal to the additional memory via a signal transmission line. Any sub-decoder that transmits to the ground line decoder and is electrically connected to the common ground line is selected and outputs an equivalent voltage. When the additional memory ground line decoder performs address arrangement on the shared ground line, the additional memory ground line decoder transmits a signal to the main memory ground line decoder via the signal transmission line to electrically connect the shared ground line. Any sub-decoder connected to is selected and outputs an equivalent voltage.
[0019]
  AboveThe main memory ground line decoder includes a sub-decoder electrically connected to the common ground line, and the sub-decoder includes a 3-input NAND gate that receives an address signal, a 2-input NAND gate, and an inverter. One input terminal of the two-input NAND gate is electrically connected to the output terminal of the three-input NAND gate, and the other input terminal of the two-input NAND gate is connected to the common ground line in the additional ground line decoder. Electrically connected to the output terminal of the NAND gate of the sub decoder to be electrically connected. In the additional memory ground line decoder, the sub-decoder electrically connected to the common ground line includes a 4-input NAND gate that receives an address signal and a sign signal, a 2-input NAND gate, and an inverter. One input terminal of the two-input NAND gate is electrically connected to the output terminal of the four-input NAND gate, and the other input terminal of the two-input NAND gate is the common ground line in the main memory ground line decoder. Is electrically connected to the output terminal of the 3-input NAND gate of the sub-decoder.
[0020]
  AboveThe nonvolatile storage medium is a nonvolatile storage medium having a virtual ground line array structure.
[0021]
  According to the inventionThe nonvolatile storage medium is a nonvolatile storage medium provided at the base of the semiconductor chip, and includes a main memory array, an additional memory array directly connected to the main memory array, and a shared drain. The main memory array includes at least one memory cell including a source and a drain provided in a base of the semiconductor chip, at least one bit line electrically connected to the drain of the memory cell, At least one ground line electrically connected to a source of the memory cell, and the additional memory array includes an additional memory cell including an additional source and an additional drain provided in a base of the semiconductor chip; At least one additional bit line electrically connected to the additional drain of the additional memory cell, and at least one additional ground line electrically connected to the additional source of the additional memory cell.The shared drain is a main drain and an additional drain at a position where the main memory array and the additional memory array are in contact with each other..
[0022]
  AboveThe non-volatile storage medium further includes a peripheral circuit area, and the peripheral circuit area includes a main memory bit line decoder electrically connected to the bit lines of the main memory array and an additional bit line of the additional memory array. And an additional memory bit line decoder connected to each other, and at least two signal transmission lines, and both ends of the signal transmission line are electrically connected to the main memory bit line decoder and the additional memory bit line decoder, respectively. To do.
[0023]
  AboveWhen the shared drain is electrically connected to the shared bit line and the main memory bit line decoder performs address arrangement on the shared bit line, the main memory bit line decoder is connected to the additional memory bit line decoder via the signal transmission line. A signal is transmitted to the shared bit line to determine a voltage of the shared bit line and an electrical connection between the shared bit line and the additional memory bit line decoder forms an open circuit state. When the decoder performs address arrangement on the shared bit line, the additional memory bit line decoder transmits a signal to the main memory bit line decoder through another signal transmission line to determine the voltage of the shared bit line; And between the shared bit line and the main memory bit line decoder. Connection is configured to form a circuit open condition.
[0024]
  AboveThe main memory bit line decoder includes a sub-decoder electrically connected to the shared bit line, the sub-decoder including a three-input NAND gate that receives an address signal, an inverter, and a three-mode inverter. The input terminal of the inverter is electrically connected to the output terminal of the three-input NAND gate, and the control terminal of the three-mode inverter is electrically connected to the shared bit line in the additional bit line decoder. Electrically connected to the output terminal of the 4-input NAND gate of the decoder. In the additional memory bit line decoder, the sub-decoder electrically connected to the shared bit line includes a 4-input NAND gate that receives an address signal and a sign signal, an inverter, and a 3-mode inverter. The input terminal of the inverter is electrically connected to the output terminal of the 4-input NAND gate, and the input terminal of the 3-mode inverter is electrically connected to the shared bit line in the main memory bit line decoder. Electrically connected to the output terminal of the 3-input NAND gate of the decoder.
[0025]
  AboveWhen the shared drain is electrically connected to the shared bit line and the main memory bit line decoder performs address arrangement on the shared bit line, the main memory bit line decoder transmits a signal to the additional memory via a signal transmission line. Any sub-decoder that is transmitted to the bit line decoder and electrically connected to the shared bit line is selected and outputs an equivalent voltage. When the additional memory bit line decoder performs address arrangement on the shared bit line, the additional memory bit line decoder transmits a signal to the main memory bit line decoder via the signal transmission line to electrically connect the shared bit line to the shared bit line. Any sub-decoder connected to is selected and outputs an equivalent voltage.
[0026]
  AboveThe main memory bit line decoder includes a sub-decoder electrically connected to the shared bit line. The sub-decoder includes a 3-input NAND gate that receives an address signal, a 2-input NAND gate, and an inverter. One input terminal of the two-input NAND gate is electrically connected to an output terminal of the three-input NAND gate, and the other input terminal of the two-input NAND gate is connected to the shared bit line in the additional bit line decoder. Is electrically connected to the output terminal of the 4-input NAND gate of the sub-decoder. In the additional memory bit line decoder, the sub-decoder electrically connected to the shared bit line includes a 4-input NAND gate that receives an address signal and a sign signal, a 2-input NAND gate, and an inverter. One input terminal of the two-input NAND gate is electrically connected to an output terminal of the four-input NAND gate, and the other input terminal of the two-input NAND gate is connected to the shared bit line in the main memory bit line decoder. Is electrically connected to the output terminal of the 3-input NAND gate of the sub-decoder.
[0027]
  AboveThe non-volatile storage medium is a non-volatile storage medium having a virtual ground array structure.
[0028]
  According to the inventionThe non-volatile storage medium is a non-volatile storage medium provided at the base of the semiconductor chip, and includes a main memory array, an additional memory array, and a shared doping region, and the main memory array includes at least one or more main memory arrays. It has a memory cell. The additional memory array is directly connected to the main memory array and has at least one memory cell. The shared doping region is provided at a position where the main memory array and the additional memory array are in contact with each other, and is electrically connected to the adjacent memory cell and the additional memory cell at both side edges.
[0029]
  AboveA memory cell and an additional memory cell each include a source and a drain provided in the base of the semiconductor chip, and the doping region is adjacent to the main memory array at a position where the additional memory array contacts And a shared source of additional memory cells.
[0030]
  AboveA memory cell and an additional memory cell each include a source and a drain provided in the base of the semiconductor chip, and the doping region is adjacent to the main memory array at a position where the additional memory array contacts And the common drain of the additional memory cell.
[0031]
  According to the inventionA method for controlling a non-volatile storage medium is a method for controlling a non-volatile storage medium having a virtual ground array structure, the non-volatile storage medium comprising a main memory array, an additional memory array directly connected to the main memory array, and a peripheral And a shared doping region provided at a position where the main memory array and the additional memory array are in contact with each other. The main memory array includes at least one or more memory cells and a drain of the memory cell. And a ground line electrically connected to the source of the memory cell. The additional memory array includes at least one additional memory cell, an additional bit line electrically connected to a drain of the additional memory cell, and an additional ground line electrically connected to a source of the additional memory cell. A main memory ground line decoder electrically connected to the ground line of the main memory array; and an additional memory ground line decoder electrically connected to the additional ground line of the additional memory array. And at least first and second signal transmission lines, and both ends of each signal transmission line are connected to the main memory ground line decoder and the additional memory ground line decoder, respectively. A method for controlling a nonvolatile storage medium having such a configuration includes the following steps, and performing address arrangement on a shared ground line electrically connected to the shared doping region using the main memory ground line decoder: The main memory ground line decoder transmits a signal to the additional memory ground line decoder via a first signal transmission line to determine a voltage of the common ground line; and the shared ground line and additional memory ground line decoder When the additional memory bit line decoder is used to place an address on the common ground line, the additional memory ground line decoder connects the second signal transmission line to the second signal transmission line. A signal through the main memory ground line decoder to determine the voltage of the shared ground line, and a circuit for electrical connection between the shared ground line and the main memory ground line decoder Form an open state.
[0032]
  According to the present inventionThe non-volatile storage medium control method is a non-volatile storage medium control method having a virtual ground array structure, and the non-volatile storage medium includes a main memory array and an additional memory array directly connected to the main memory array. A peripheral circuit region, and a shared doping region provided at a position where the main memory array and the additional memory array are in contact with each other. The main memory array includes at least one memory cell and a drain of the memory cell. A bit line electrically connected to the memory cell, and a ground line electrically connected to the source of the memory cell. The additional memory array includes at least one additional memory cell and a drain of the additional memory cell. And an additional bit line electrically connected to the source, and an additional ground line electrically connected to the source of the additional memory cell. It made. The peripheral circuit area includes a main memory ground line decoder electrically connected to the ground line of the main memory array, an additional memory ground line decoder electrically connected to the additional ground line of the additional memory array, and At least first and second signal transmission lines are provided, and both ends of each signal transmission line are connected to the main memory ground line decoder and the additional memory ground line decoder, respectively. A method for controlling a non-volatile storage medium having such a configuration includes the following steps, and performing address arrangement on a shared ground line electrically connected to the shared doping region using the main memory ground line decoder: The main memory ground line decoder transmits a signal to the additional memory ground line decoder via the first signal transmission line, and the shared ground line and each of the sub-decoders are selected, and the equivalent voltage is set. When the additional memory ground line decoder uses the additional memory ground line decoder to assign an address to the shared ground line, the additional memory ground line decoder sends a signal to the main memory ground line decoder via the second signal transmission line. So that both the common ground line and each sub-decoder are selected and output an equivalent voltage.
[0033]
  According to the inventionThe non-volatile storage medium control method is a non-volatile storage medium control method having a virtual ground array structure, and the non-volatile storage medium includes a main memory array, an additional memory array directly connected to the main memory array, and A peripheral doping region, and a common doping region provided at a position where the main memory array and the additional memory array are in contact with each other. The main memory array includes at least one memory cell and a drain of the memory cell. A bit line that is electrically connected; and a ground line that is electrically connected to a source of the memory cell. The additional memory array includes at least one additional memory cell and a drain of the additional memory cell. And an additional bit line electrically connected to the source, and an additional ground line electrically connected to the source of the additional memory cell. It made. The peripheral circuit area includes a main memory bit line decoder electrically connected to the bit lines of the main memory array, an additional memory bit line decoder electrically connected to the additional bit lines of the additional memory array, and At least first and second signal transmission lines are provided, and both ends of each signal transmission line are connected to the main memory bit line decoder and the additional memory bit line decoder, respectively. A method for controlling a non-volatile storage medium having such a configuration includes the following steps, in which address arrangement is performed on a shared bit line electrically connected to the shared doping region using the main memory bit line decoder: The main memory bit line decoder transmits a signal to the additional memory bit line decoder via a first signal transmission line to determine a voltage of the shared bit line; and the shared bit line and the additional memory bit When an open circuit state is formed in the electrical connection with the line decoder, and the address arrangement is performed on the shared bit line using the additional memory bit line decoder, the additional memory bit line decoder transmits the second signal. A signal is transmitted over the line to the memory bit line decoder to determine the voltage of the shared bit line, and the common A bit line, to form a circuit open to the electrical connection between the main memory bit line decoder.
[0034]
  According to the inventionThe non-volatile storage medium control method is a non-volatile storage medium control method having a virtual ground array structure, and the non-volatile storage medium includes a main memory array, an additional memory array directly connected to the main memory array, and A peripheral doping region, and a common doping region provided at a position where the main memory array and the additional memory array are in contact with each other. The main memory array includes at least one memory cell and a drain of the memory cell. A bit line that is electrically connected; and a ground line that is electrically connected to a source of the memory cell. The additional memory array includes at least one additional memory cell and a drain of the additional memory cell. And an additional bit line electrically connected to the source, and an additional ground line electrically connected to the source of the additional memory cell. It made. The peripheral circuit area includes a main memory bit line decoder electrically connected to the bit lines of the main memory array, an additional memory bit line decoder electrically connected to the additional bit lines of the additional memory array, and At least first and second signal transmission lines are provided, and both ends of each signal transmission line are connected to the main memory bit line decoder and the additional memory bit line decoder. A method for controlling a non-volatile storage medium having such a configuration includes the following steps, in which address arrangement is performed on a shared bit line electrically connected to the shared doping region using the main memory bit line decoder: The main memory bit line decoder transmits a signal to the additional memory bit line decoder via the first signal transmission line, and both the shared bit line and each sub-decoder are selected, and an equivalent voltage is applied. When the additional memory bit line decoder uses the additional memory bit line decoder to place an address on the shared bit line, the additional memory bit line decoder sends a signal to the main memory bit line decoder via the second signal transmission line. Both the shared bit line and the respective sub-decoder are selected, and So as to output a voltage equal.
[0035]
  According to the inventionThe non-volatile storage medium is a non-volatile storage medium provided at the base of the semiconductor chip, and is connected to the main memory array including at least one or more memory cells and directly connected to the main memory array, and at least one or more An additional memory array including additional memory cells, a memory cell adjacent to both side edges provided at a position where the main memory array and the additional memory array are in contact with each other, and a shared doping area shared by the additional memory cells And a peripheral circuit region including at least one decoder.
[0036]
  AboveThe decoder includes a main memory decoder, an additional memory decoder, and a shared decoder.
[0037]
  AboveThe shared decoder is a shared ground line decoder.
[0038]
  AboveThe shared decoder is a shared bit line decoder.
[0039]
  According to the inventionThe non-volatile storage medium is a non-volatile storage medium provided at the base of the semiconductor chip, and includes a main memory array, an additional memory array directly connected to the main memory array, and a peripheral circuit area. The array includes at least one or more memory cells having a source and a drain provided in a base of the semiconductor chip, a bit line electrically connected to the drain of the memory cell, and an electrical connection to the source of the memory cell The additional memory array includes at least one additional memory cell having an additional source and an additional drain provided in the base of the semiconductor chip, and an additional drain electrically connected to the additional drain of the additional memory cell. And an additional bit line connected to the additional memory cell and an additional ground line electrically connected to the additional source of the additional memory cell. It becomes in and the additional memory array share a common doped region with the main memory array, in the peripheral circuit region includes at least one or more decoders.
[0040]
  AboveA main memory ground line decoder electrically connected to the ground line of the main memory array; an additional memory ground line decoder electrically connected to the additional ground line of the additional memory array; and at least two signals A transmission line is provided, and both ends of each signal transmission line are electrically connected to the main memory ground line decoder and the additional memory ground line decoder.
[0041]
  AboveThe decoder further includes a shared ground line decoder.
[0042]
  AboveThe shared doping region is a source at a position where the main memory array and the additional memory array are in contact with each other, and is also an additional source.
[0043]
  AboveA main memory bit line decoder electrically connected to the bit lines of the main memory array; an additional memory bit line decoder electrically connected to the additional bit lines of the additional memory array; and at least two signals A transmission line is provided, and both ends of each signal transmission line are electrically connected to the main memory bit line decoder and the additional memory bit line decoder.
[0044]
  AboveThe decoder further includes a shared bit line decoder.
[0045]
  AboveThe shared doping region is a drain at a position where the main memory array and the additional memory array are in contact with each other, and is also an additional drain.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
The present invention is a non-volatile storage medium capable of increasing the use efficiency of the layout area of the memory array region and effectively reducing the size of the semiconductor, and is directly connected to the main memory array and the additional memory array to provide a virtual ground Configure the array structure. That is, the present invention removes the field oxide layer for separating the main memory array from the additional memory array and the dummy memory, and directly connects the main memory array to the additional memory array.
[0047]
In order to explain the structure and characteristics of such a non-volatile storage medium, specific examples will be given and will be described in detail below with reference to the drawings.
[0048]
【Example】
FIG. 3 is a block diagram showing a partial structure of the nonvolatile storage medium 110 according to the present invention. The nonvolatile storage medium 110 includes a peripheral circuit area 120 and a memory array area 150. Memory array area 150 includes main memory array 160 and additional memory array 170, and peripheral circuit area 120 includes address buffer 122, addressable memory unit 124, ground line decoder 130, and additional ground line decoder 140. It becomes. Addressable memory unit 124 is provided for storing address data of stale memory units in main memory array 160. The ground line decoder 130 is electrically connected to the main memory array 160 via the ground line GL, and the additional ground line decoder 140 is electrically connected to the additional memory array via the ground line RGL.
[0049]
4 is a circuit diagram of the memory array area 150 of the nonvolatile storage medium 110 according to the present invention. FIG. 5 shows the structure of the memory array area 150 of the nonvolatile storage medium 110 according to the present invention. As illustrated, the nonvolatile storage medium 110 is formed on the base 182 of the semiconductor chip 180. The memory array area 150 includes a main memory array 160 and an additional memory array 170. The main memory array 160 is directly connected to the additional memory array 170. Ground line GL at a position corresponding to the edge of main memory array 160_{M + 1}Is a ground line RGL at a position corresponding to the edge of the additional memory array 170₁Connected to the common ground line GL_CIt becomes. That is, the main source and the additional source at a position where the main memory array 160 and the additional memory array 170 are in contact with each other serve as a common doping region.
[0050]
  The main memory array 160 includes M bit lines BL1 to BLM, M + 1 ground lines GL1 to GLM + 1, and a plurality of memory cells. Each memory cell includes a source 184 and a drain 186, formed in the base 182 of the semiconductor chip 180, and a gate electrode 188 formed on the base 182. The gate electrode 188 may be a control gate or a flow gate. Each ground line GL is electrically connected to a source 184 of a predetermined number of memory cells in the main memory array 160 and each bit line BL is connected to a predetermined number in the main memory array 160.ofElectrically connected to the drain 186 of the memory cell. Of the M + 1 ground lines, GL2 to GLM + 1 are used to operate the adjacent memory cells. That is, the ground lines GL2 to GLM + 1 are shared with the adjacent memory cells. Since the ground line GL1 is located at the edge of the main memory array 160, only the cells on one side can be operated.
[0051]
The additional memory array 170 includes N bit lines RBL.₁~ RBL_NN + 1 ground lines RGL₁~ RGL_{N + 1}And a plurality of memory cells. Each memory cell includes a source 184 and a drain 186 and is formed in the base 182 of the semiconductor chip 180, and a gate electrode 188 is provided on the base 182. Each ground line RGL is electrically connected to a source 184 of a predetermined number of memory cells in the additional memory array 170, and each bit line RBL is connected to a drain of a predetermined number of memory cells in the additional memory array 170. Electrically connected to 186. Of the N + 1 ground wires, RGL₁~ RGL_NIs used to operate the adjacent memory cells. That is, the ground line RGL₁~ GL_NIs shared with both adjacent memory cells. Also, ground line RGL_{N + 1}Is located at the edge of the additional memory array 170 and can only operate on one side cell.
[0052]
FIG. 6A is a logic circuit diagram of the ground line decoder 130 'and the additional ground line decoder 140' in the embodiment. As shown, the ground line decoder 130 'includes M + 1 sub-decoders 131'._-1′ To 131_{-M + 1}'And each sub-decoder 131' is provided corresponding to each ground line GL 'of the main memory array 160. Also, the sub decoder 131_-1′ And 131_{-M + 1}Each sub-decoder 131 except '_{− 2}′ To 131_-M'Includes two three-input NAND gates each receiving an address signal and one two-input NAND gate. The input terminals of the 2-input NAND gate are electrically connected to the two output terminals of the 3-input NAND gate and the inverter, respectively, and the input terminal of the inverter is electrically connected to the output terminal of the NAND gate.
[0053]
Ground wire GL_{M + 1}Sub-decoder 131 corresponding to '_{-M + 1}'Includes one 3-input NAND gate 132 that receives an address signal, one 2-input NAND gate 133, and one inverter 134. One input terminal of the NAND gate 133 is electrically connected to the output terminal of the NAND gate 132, and the other input terminal is electrically connected to the signal transmission line 136 '.
[0054]
The additional ground line decoder 140 ′ includes N + 1 sub-decoders 141._-1'To 141_{-N + 1}'And each sub-decoder 141' is provided corresponding to the ground line RGL 'of the additional memory array 170. Sub decoder 141_-1'And 141_{-N + 1}Each decoder 141 except '_-2'To 141_-N'Includes two four-input NAND gates each receiving an address signal and a sign signal, and one two-input NAND gate, and the input terminals of the two-input NAND gates are respectively two two-input NAND gates. The output terminal is electrically connected to the inverter, and the input terminal of the inverter is electrically connected to the output terminal of the NAND gate.
[0055]
Ground wire RGL₁Sub-decoder 141 corresponding to '_-1'Includes a 4-input NAND gate 142 for receiving an address signal and a sign signal, a 2-input NAND gate 143, and an inverter 144. The NAND gate 143 has one input terminal electrically connected to the output terminal of the NAND gate 142 and the other input terminal electrically connected to the signal transmission line 138 ′.
[0056]
Both ends of the signal transmission line 136 'are respectively connected to the sub-decoder 131._{-M + 1}'Is electrically connected to one input terminal of the two-input NAND gate 133 and the output terminal of the four-input NAND gate 142 of the sub decoder 141-1'. Further, both ends of the signal transmission line 138 ′ are respectively connected to one input terminal of the 2-input NAND gate 143 of the sub decoder 141-1 ′ and the sub decoder 131._{-M + 1}It is electrically connected to the output terminal of the three-input NAND gate 132.
[0057]
  When the nonvolatile storage medium 110 is operated, the address buffer 122 outputs an address signal to the ground line decoder 130 ′ and the addressable memory unit 124, respectively.lineThe decoder 130 ′ decodes a signal transmitted from the signal transmission line 136 ′ based on the address signal, and selects an appropriate ground line GL of the main memory array 160. If the transmitted address signal matches the address stored in the addressable memory unit 124, the addressable memory unit 124 generates a sign signal, and drives the additional ground line decoder 140 ′ by the sign signal. Based on the address signal, a signal transmitted from the signal transmission line 138 ′ is decoded, and an appropriate ground line RGL of the additional memory array 170 is selected.
[0058]
For example, the ground line decoder 130 'may be connected to the common ground line GL._CSub decoder 131_{-M + 1}Output ground line GL_{M + 1}'Is selected and the sub-decoder 131 of the ground line decoder 130' is selected._{-M + 1}The sub-decoder 141 of the additional ground decoder 140 'receives the operation corresponding signal through the signal transmission line 138'._-1To the sub-decoder 141._-1RGL output by '₁'Is also selected. Therefore, the sub decoder 131_{-M + 1}', 141_-1'Is selected (ie, outputs a voltage). On the other hand, the additional ground line decoder 140 'shares a common ground line GL._CSub-decoder 141 when trying to drive '_-1'Output Grounding Line RGL'₁Is selected and the sub-decoder 141 of the ground line decoder 140 'is selected._-1The sub-decoder 131 of the additional ground decoder 130 'receives the operation corresponding signal through the signal transmission line 136'._{-M + 1}′ And the sub decoder 131_{-M + 1}GL output by ’_{M + 1}'Is also selected. Therefore, the sub decoder 131_{-M + 1}', 141_-1'Is selected (ie, outputs a voltage).
[0059]
  FIG. 6B is a logic circuit diagram of a ground line decoder 130 ″ and an additional ground line decoder 140 ″ according to another embodiment. The illustrated embodiment includes a three-input NAND gate 132 in which the sub-decoder 131-M + 1 ″ of the ground line GLM + 1 ″ receives an address signal;Inverter 134,In this respect, comprising a three-mode output inverter 1356A.And different. One input terminal of the inverter 134 is electrically connected to the output terminal of the NAND gate 132, one input terminal of the three-mode output inverter 135 is electrically connected to the output terminal of the inverter 134, and the control of the three-mode output inverter 135 is performed. The end is electrically connected to the signal transmission line 136 ''.
[0060]
The sub-decoder 141-1 ″ includes a 4-mode input NAND gate 142 that receives an address signal and a sign signal, an inverter 144, and a 3-mode output inverter 145. One input terminal of the inverter 144 is electrically connected to the output terminal of the NAND gate 142, and the input terminal of the three-mode output inverter 145 is electrically connected to the output terminal of the inverter 144. The control end of the three-mode output inverter 145 is electrically connected to the signal transmission line 138 ''.
[0061]
Both ends of the signal transmission line 136 ″ are respectively connected to the sub decoder 131._{-M + 1}The control terminal of the three-mode inverter 135 of ″ and the sub decoder 141_-1It is electrically connected to the output terminal of the four-input NAND gate 142. In addition, both ends of the signal transmission line 138 ″ are connected to the sub-decoder 141, respectively._-1The control terminal of the inverter 145 of ″ and the sub decoder 131_{-M + 1}The three-mode input NAND gate 132 of ″ is electrically connected to the output terminal.
[0062]
Similar to the above-described operation procedure according to FIG. 6A, when performing an operation on the nonvolatile storage medium 110, the address buffer 122 transmits an address signal to the ground line decoder 130 ″ and the addressable memory unit 124, respectively. . The ground line decoder 130 ″ decodes a signal transmitted from the signal transmission line 136 ″ based on the address signal, and selects an appropriate ground line GL ″ of the main memory array 160. If the transmitted address signal matches the address stored in the addressable memory unit 124, the addressable memory unit 124 generates a code signal and drives the additional ground line decoder 140 '' by the code signal. Based on the address signal, the signal transmitted from the signal transmission line 138 ″ is decoded, and an appropriate ground line RGL ″ of the additional memory array 170 is selected.
[0063]
For example, a ground line GL shared by the ground line decoder 130 ″ is used._CWhen trying to drive "", the sub-decoder 131_{-M + 1}"" Output ground line GL_{M + 1}″ Is selected and the sub-decoder 131 of the ground line decoder 130 ″ is selected._{-M + 1}The operation corresponding signal is transmitted to the sub-decoder 141 of the additional ground decoder 140 ″ via the ″ signal transmission line 138 ″._-1”And output to the sub-decoder 141._-1RGL 'output by ""₁ The output circuit open state is formed at ″. For this reason, the common ground line GLc ″ cannot be operated. That is, the voltage of the common ground line GLc ″ is equal to the sub decoder 131._{-M + 1}Determined by the output of ″. Conversely, the additional ground line decoder 140 ″ is connected to the common ground line GL._CWhen it is intended to drive "", the sub-decoder 141 is used._-1"" Output ground line RGL₁″ Is selected and the sub-decoder 141 of the ground line decoder 140 ″ is selected._-1The operation corresponding signal is transmitted to the sub-decoder 131 of the additional ground decoder 130 ″ via the ″ signal transmission line 136 ′._{-M + 1}”And output to the sub decoder 131._{-M + 1}"" Output ground line GL_{M + 1}″ Forms an output circuit open state and the common ground line GL_C‘” Cannot be operated. That is, the voltage of the common ground line GLc ″ is equal to the sub decoder 141._-1Determined by the output of ″.
[0064]
Therefore, in the present invention, the main memory array 160 and the additional memory array 170 can be directly connected by controlling the ground line decoders 130 ′ / 130 ″ and the additional ground line decoders 140 ′ / 140 ″. In the above embodiment, the main memory array 160 shares the source with the additional memory array 170 to form a common ground line, and transmits from the signal transmission line 138 ′ / 138 ″ of the ground line decoder 130 ′ / 130 ″. The additional ground line decoder 140 ′ / 140 ″ is controlled by using the operation corresponding signal, and the operation corresponding to the operation transmitted from the signal transmission line 136 ′ / 136 ″ of the additional ground line decoder 140 ′ / 140 ″. The signals are used to control the ground line decoders 130 ′ / 130 ″ so that each voltage is accurately applied to the shared ground line.
[0065]
  In addition to sharing one ground line, the main memory array 160 and the additional memory array 170 may be connected using one bit line. FIG. 7 is a partial block diagram of the nonvolatile storage medium 210 according to the present invention. The nonvolatile storage medium 210 includes a peripheral circuit area 220 and a memory array area 250. However, the portion related to the ground line is not shown in FIG. The memory array area 250 includes a main memory array 260 and an additional memory array 270, and the peripheral circuit area 220 includesAddress buffer222, an addressable memory unit 224 for storing address data of an expired memory unit in the main memory array 260, a bit line decoder 230 electrically connected to the bit line BL of the main memory array 260, and an additional memory And an additional bit line decoder 240 electrically connected to the bit line RBL of the array 270.
[0066]
  FIG. 8 is a circuit diagram of the memory array area 250 of the nonvolatile storage medium 210 according to the present invention. FIG. 9 shows the structure of the memory array area 250 of the nonvolatile storage medium 210 according to the present invention. The nonvolatile storage medium 210 is formed on the base 282 of the semiconductor chip 280. Memory array area 250 includes a main memory array 260 and an additional memory array 270. Main memory array 260 is directly connected to additional memory array 270. The bit line BLM + 1 at the position corresponding to the end edge of the main memory array 260 is connected to the bit line RBL1 at the position corresponding to the end edge of the additional memory array 270 to form a shared bit line BLC. That is, the position where the main memory array 260 and the additional memory array 270 are in contact with each other.Main drainWhenAdditional drainBecomes a shared doping region.
[0067]
The main memory array 260 has M + 1 bit lines BL₁~ BL_{M + 1}And M ground wires GL₁~ GL_MAnd a plurality of memory cells. Each memory cell includes a source 286 and a drain 284, is formed in the base 282 of the semiconductor chip 280, and a gate electrode 288 is formed on the base 282. Each ground line GL is electrically connected to the source 286 of a predetermined number of memory cells in the main memory array 260, and each bit line BL is connected to the drain of a predetermined number of memory cells in the main memory array 60. Electrically connected to 284. BL out of M + 1 bit lines₂~ BL_{M + 1}Is used to operate the adjacent memory cells. That is, bit line BL₂~ BL_{M + 1}Is shared with both adjacent memory cells. Bit line BL₁Is located at the edge of the main memory array 260 and can only operate on one side cell.
[0068]
  The additional memory array 270 includes N + 1 bit lines RBL.₁~ RBL_{N + 1}And N ground lines RGL₁~RGL _N And a plurality of memory cells. Each memory cell includes a source 286 and a drain 284 and is formed in the base 282 of the semiconductor chip 280, and a gate electrode 288 is provided on the base 282. Each ground line RGL is electrically connected to a source 286 of a predetermined number of memory cells in the additional memory array 270, and each bit line RBL is connected to a drain of a predetermined number of memory cells in the additional memory array 270. Electrically connected to 284. Of N + 1 bit lines, RBL₁~ RBL_NIs used to operate the adjacent memory cells. That is, the bit line RBL₁~ GBL_NIs shared with both adjacent memory cells. The bit line line RBL_{N + 1}Can only operate cells on one side.
[0069]
  FIG. 10A shows a bit line decoder 230 'in the embodiment,Additional bit line decoderIt is a logic circuit diagram of 240 '. The bit line decoder 230 ′ has M + 1 sub-decoders 231._-1'To 231_{-M + 1}'And each sub-decoder 231' is provided corresponding to each bit line BL 'of the main memory array 260. Also, the sub decoder 231_-1'And 231_{-M + 1}Each sub-decoder 231 except '_{− 2}'To 231_-M'Includes two three-input NAND gates each receiving an address signal and one two-input NAND gate.Bit line BL _{M + 1} Bit line sub-decoder 231 corresponding to ' _{-M + 1} 'Includes a 3-input NADN gate 232, a 2-input NAND gate 233 and an inverter 234 for receiving an address signal. One input end of the 2-input NAND gate 233 is electrically connected to the output end of the 3-input NAND gate 232, and the other input end of the 2-input NAND gate 233 is electrically connected to the signal transmission line 236 ′. . The input terminal of the inverter 234 is electrically connected to the output terminal of the two-input NAND gate 233..
[0070]
  The additional bit decoder 240 ′ includes N + 1 sub-decoders 241._-1′ To 241_{-N + 1}'And each sub-decoder 241' is provided corresponding to the bit line RBL 'of the additional memory array 270. Sub decoder241 _-1 'as well as241 _{-N + 1} Each decoder 241 except '_-2′ To 241_-N'Includes two four-input NAND gates each receiving an address signal and a sign signal, and one two-input NAND gate, and the input terminals of the two-input NAND gates are respectively two two-input NAND gates. Electrically connected to the output end and to the inverter. Also, the sub decoder 241 corresponding to the bit line RBL1 '._-1'Includes a four-input NAND gate 242 that receives an address signal and a sign signal, and a two-input NAND gate 243. The NAND gate 243 has an input terminal 1 electrically connected to an output terminal of the NAND gate 242; The other input terminal is electrically connected to the signal transmission line 238 ′.
[0071]
Both ends of the signal transmission line 236 'are respectively connected to the sub decoder 231._{-M + 1}'Is electrically connected to one input terminal of the 2-input NAND gate 233 and the output terminal of the 4-input NAND gate 242 of the sub decoder 241-1'. Further, both ends of the signal transmission line 238 ′ are respectively connected to one input terminal of the 2-input NAND gate 243 of the sub-decoder 241-1 ′ and the sub-decoder 231._{-M + 1}'Is electrically connected to the output terminal of the 3-input NAND gate 232.
[0072]
  When the nonvolatile storage medium 210 is operated, the address buffer 222 outputs an address signal to the bit line decoder 230 ′ and the addressable memory unit 224, respectively, and the bit line decoder 230 ′ decodes the address signal, An appropriate bit line BL of the main memory array 260 is selected. If the transmitted address signal matches the address stored in the addressable memory unit 224, the addressable memory unit 224 generates a code signal,Additional bit line decoder240 'is driven, the signal transmitted from the signal transmission line 236' is decoded based on the address signal, and an appropriate bit line line RBL 'of the additional memory array 270 is selected.
[0073]
The bit line decoder 230 '_CWhen the sub decoder 231 is to be driven,_{-M + 1}'Output bit line BL_{M + 1}'Is selected and the sub-decoder 231 of the bit line decoder 230' is selected._{-M + 1}The signal corresponding to the operation is transmitted via the signal transmission line 238 'and the sub decoder 241 of the additional bit line decoder 240'._-1′ And the sub decoder 241_-1Bit line RBL output by '₁'Is also selected. Therefore, the sub decoder 231_{-M + 1}', 241_-1'Is selected (ie, outputs a voltage). Conversely, the additional bit line decoder 240 'is shared by the ground line GL._CWhen trying to drive ', the sub-decoder 241_-1'Output bit line RBL'₁Is selected and the sub-decoder 241 of the bit line decoder 240 '_-1The operation corresponding signal is transmitted to the sub-decoder 231 of the bit line decoder 230 'through the signal transmission line 236'._{-M + 1}′ And the sub decoder 231_{-M + 1}Bit line BL output by '_{M + 1}'Is also selected. Therefore, the sub decoder 231_{-M + 1}', 241_-1'Is selected (ie, outputs a voltage).
[0074]
FIG. 10B is a logic circuit diagram of a ground line decoder 230 ″ and an additional ground line decoder 240 ″ according to another embodiment. Bit line BL_{M + 1}Sub-decoder 131 corresponding to ""_{-M + 1}″ Includes a three-input NAND gate 232, an inverter 234, and a three-mode output inverter 235, and the control terminal of the three-mode output inverter 235 is electrically connected to the signal transmission line 236 ″. In addition, bit line RBL₁The sub-decoder 241-1 ″ corresponding to ″ includes a 4-input mode NAND gate 242 that receives an address signal and a sign signal, an inverter 244, and a 3-mode output inverter 245. The control end of the inverter 245 is electrically connected to the signal transmission line 238 ″.
[0075]
10A and 10B, the main memory array 260 and the additional memory array 270 are controlled by controlling the bit line decoder 230 ′ / 230 ″ and the additional bit line decoder 240 ′ / 240 ″. Are directly linked. That is, the main memory array 260 and the additional memory array 270 share a drain to form a common bit line, and the bit line decoder 230 ′ / 230 ″ transmits the signal via the signal transmission line 238 ′ / 238 ″. The additional bit line decoder 240 ′ / 240 ″ is controlled by the operation corresponding signal, and the bit line is determined by the operation corresponding signal transmitted by the additional bit line decoder 240 ′ / 240 ″ through the signal transmission line 236 ′ / 236 ″. By controlling the decoders 230 ′ / 230 ″, each voltage is applied correctly to the shared bit line.
[0076]
Since the conventional nonvolatile storage medium is provided with the field oxide layer and the dummy memory between the main memory array and the additional memory array, the layout area is used more than necessary. The present invention directly connects the main memory array and the additional memory array by controlling the main memory array decoder and the additional memory decoder. Therefore, it is not necessary to provide a field oxide layer and a dummy memory to separate the main memory array and the additional memory array, and the layout area of the memory array can be reduced. That is, the nonvolatile storage medium according to the present invention is a nonvolatile storage medium having a kind of virtual ground array structure.
[0077]
The above are preferred embodiments of the present invention, and do not limit the scope of the present invention. Therefore, any modifications and changes that can be made by those skilled in the art and that have an equivalent effect on the present invention shall fall within the scope of the claims of the present invention.
[0078]
【The invention's effect】
The nonvolatile storage medium according to the present invention can increase the use efficiency of the layout area of the memory array region and effectively reduce the size of the semiconductor.
[Brief description of the drawings]
FIG. 1 is a block diagram of a conventional nonvolatile storage medium.
FIG. 2A is an explanatory diagram showing a structure of a memory array of a conventional nonvolatile storage medium.
FIG. 2B is a circuit diagram of a memory array of a conventional nonvolatile storage medium.
FIG. 3 is a partial block diagram of a nonvolatile storage medium according to the present invention.
FIG. 4 is a circuit diagram of a memory array of a nonvolatile storage medium according to the present invention.
FIG. 5 is a circuit diagram of a memory array of a nonvolatile storage medium according to the present invention.
FIG. 6A is a logic circuit diagram of one embodiment of a ground line decoder and an additional ground line decoder in the present invention.
FIG. 6B is a logic circuit diagram according to another embodiment of the ground line decoder and the additional ground line decoder in the present invention.
FIG. 7 is a partial block diagram of a nonvolatile storage medium according to the present invention.
FIG. 8 is a circuit diagram of a memory array of a nonvolatile storage medium according to the present invention.
FIG. 9 is an explanatory diagram showing a structure of a memory array of a nonvolatile storage medium according to the present invention.
FIG. 10A is a logic circuit diagram of one embodiment of a bit line decoder and an additional bit line decoder in the present invention.
FIG. 10B is a logic circuit diagram according to another embodiment of the bit line decoder and additional bit line decoder of the present invention.
[Explanation of symbols]
110, 210 Nonvolatile storage medium
120, 220 Peripheral circuit area
124, 224 Addressable memory unit
122, 222 Address buffer
130, 130 ', 130 "ground line decoder
131 ', 131 ", 141', 141", 231, 231 ', 231 ", 241, 241', 241" sub-decoder
132, 133, 142, 143 NAND gate
134, 144, 234, 244 Inverter
135, 145, 235, 245 3-mode output inverter
140, 140 ', 140 "additional ground line decoder
136, 136 ', 136 ", 138, 138', 138", 236, 236 ', 236 ", 238, 238', 238" signal transmission line
150, 250 Memory array area
160, 260 Main memory array
170, 270 Additional memory array
180, 280 semiconductor chip
182 and 282 base
184, 286 source
186, 284 drain
188 Gate electrode
230, 230 ', 230 "bit line decoder
232, 233, 242, 243 NAND gate pole
240, 240 ', 240 "additional bit line decoder
288 Gate electrode
GL, RGL Ground wire
BL, RBL bit line

Claims (16)

A non-volatile storage medium provided at the base of a semiconductor chip,
A main memory array, an additional memory array directly connected to the main memory array, a shared source, and a peripheral circuit area;
The main memory array includes at least one memory cell including a source and a drain provided in a base of the semiconductor chip, at least one bit line electrically connected to the drain of the memory cell, And at least one ground line electrically connected to a source of the memory cell,
The additional memory array includes an additional memory cell including an additional source and an additional drain provided in the base of the semiconductor chip, and at least one additional bit line electrically connected to the additional drain of the additional memory cell. And at least one additional ground line electrically connected to an additional source of the additional memory cell,
The peripheral circuit area includes at least two main memory ground line decoders electrically connected to the ground lines of the main memory array, additional memory ground line decoders electrically connected to the additional ground lines of the additional memory array, and More than one signal transmission line, and both ends of the signal transmission line are electrically connected to the main memory ground line decoder and the additional memory ground line decoder, respectively.
The shared source is a main source and an additional source at a position where the main memory array and the additional memory array are in contact with each other.
A non-volatile storage medium characterized by the above. When the common source is electrically connected to the common ground line and the main memory ground line decoder performs address arrangement on the common ground line, the main memory ground line decoder is connected to the additional memory ground line decoder via a signal transmission line. A signal is transmitted to the common ground line to determine a voltage of the common ground line, and an electrical connection between the common ground line and the additional memory ground line decoder forms an open circuit state. When the decoder performs address arrangement on the shared ground line, the additional memory ground line decoder transmits a signal to the main memory ground line decoder through another signal transmission line to determine the voltage of the shared ground line; 2. The non-volatile storage medium according to claim 1, wherein an electrical connection between the shared ground line and the main memory ground line decoder forms an open circuit state. . The main memory ground line decoder includes a sub-decoder electrically connected to the common ground line. The sub-decoder includes a three-input NAND gate that receives an address signal, an inverter, and a three-mode inverter. The input terminal of the inverter is electrically connected to the output terminal of the three-input NAND gate, and the control terminal of the three-mode inverter is electrically connected to the common ground line in the additional ground line decoder. The sub-decoder electrically connected to the output terminal of the 4-input NAND gate of the sub-decoder and electrically connected to the shared ground line in the additional memory ground line decoder receives the address signal and the sign signal. A four-input NAND gate, an inverter, and a three-mode inverter, the input terminal of the inverter being electrically connected to the output terminal of the four-input NAND gate, 3. The control terminal of the inverter is electrically connected to an output terminal of a 3-input NAND gate of a sub-decoder electrically connected to the common ground line in the main memory ground line decoder. Non-volatile storage medium. The shared source is electrically connected to the shared ground line, and when the main memory ground line decoder performs address allocation on the shared ground line, the main memory ground line decoder adds the signal via a signal transmission line. Any sub-decoder that is transmitted to the memory ground line decoder and electrically connected to the shared ground line is selected and outputs an equivalent voltage, and the additional memory ground line decoder assigns an address to the shared ground line. When performing, the sub-decoder for transmitting the signal to the main memory ground line decoder through the signal transmission line to the main memory ground line decoder and electrically connecting to the common ground line is selected, and equivalent The nonvolatile storage medium according to claim 1, wherein a voltage is output. The main memory ground line decoder includes a sub-decoder electrically connected to the common ground line, the sub-decoder receiving an address signal, a 3-input NAND gate, a 2-input NAND gate, an inverter, One input terminal of the two-input NAND gate is electrically connected to an output terminal of the three-input NAND gate, and the other input terminal of the two-input NAND gate is connected to the common ground in the additional ground line decoder. In the additional memory ground line decoder, the sub decoder electrically connected to the shared ground line is electrically connected to the output terminal of the NAND gate of the sub decoder electrically connected to the line. A four-input NAND gate that receives a sign signal, a two-input NAND gate, and an inverter, wherein one input terminal of the two-input NAND gate is electrically connected to the output terminal of the four-input NAND gate; Besides the 2-input NAND gate 5. The nonvolatile memory according to claim 4, wherein an input terminal is electrically connected to an output terminal of a 3-input NAND gate of a sub-decoder that is electrically connected to the common ground line in the main memory ground line decoder. Sex storage medium. The nonvolatile storage medium according to claim 1, wherein the nonvolatile storage medium is a nonvolatile storage medium having a virtual ground line array structure. A non-volatile storage medium provided at the base of a semiconductor chip,
A main memory array, an additional memory array directly connected to the main memory array, a shared drain, and a peripheral circuit region;
The main memory array includes at least one memory cell including a source and a drain provided in a base of the semiconductor chip, at least one bit line electrically connected to the drain of the memory cell, And at least one ground line electrically connected to a source of the memory cell,
The additional memory array includes an additional memory cell including an additional source and an additional drain provided in the base of the semiconductor chip, and at least one additional bit line electrically connected to the additional drain of the additional memory cell. And at least one additional ground line electrically connected to an additional source of the additional memory cell,
The peripheral circuit area includes at least two main memory bit line decoders electrically connected to the bit lines of the main memory array, additional memory bit line decoders electrically connected to the additional bit lines of the additional memory array, and More than one signal transmission line, and both ends of the signal transmission line are electrically connected to the main memory bit line decoder and the additional memory bit line decoder, respectively.
The shared drain is a main drain and an additional drain at a position where the main memory array and the additional memory array are in contact with each other.
A non-volatile storage medium characterized by the above. When the shared drain is electrically connected to a shared bit line and the main memory bit line decoder performs address arrangement on the shared bit line, the main memory bit line decoder transmits the additional memory bit line via a signal transmission line. A signal is transmitted to the decoder to determine the voltage of the shared bit line and an electrical connection between the shared bit line and the additional memory bit line decoder forms an open circuit state; When the line decoder performs address arrangement on the shared bit line, the additional memory bit line decoder transmits a signal to the main memory bit line decoder through another signal transmission line to determine the voltage of the shared bit line. And between the shared bit line and the main memory bit line decoder Non-volatile storage medium of claim 7, the gas connection is characterized by configured to form a circuit open condition. The main memory bit line decoder includes a sub decoder electrically connected to the shared bit line. The sub decoder includes a three-input NAND gate that receives an address signal, an inverter, and a three-mode inverter. The input terminal of the inverter is electrically connected to the output terminal of the three-input NAND gate, and the control terminal of the three-mode inverter is electrically connected to the shared bit line in the additional bit line decoder. The sub-decoder electrically connected to the output terminal of the 4-input NAND gate of the sub-decoder and electrically connected to the shared bit line in the additional memory bit line decoder receives the address signal and the sign signal. A four-input NAND gate, an inverter, and a three-mode inverter, the input terminal of the inverter being the four-input NAND gate The input terminal of the three-mode inverter is electrically connected to the output terminal of the 3-input NAND gate of the sub-decoder that is electrically connected to the shared bit line in the main memory bit line decoder. The nonvolatile storage medium according to claim 8, wherein the nonvolatile storage medium is connected to the storage medium. The shared drain is electrically connected to the shared bit line, and when the main memory bit line decoder assigns an address to the shared bit line, the main memory bit line decoder adds the signal via a signal transmission line. Any sub-decoder that is transmitted to the memory bit line decoder and electrically connected to the shared bit line is selected and outputs an equivalent voltage, and the additional memory bit line decoder assigns an address arrangement to the shared bit line. When the sub-decoder is selected, the sub-decoder that transmits the signal to the main memory bit line decoder through the signal transmission line and electrically connects to the shared bit line is selected. The nonvolatile storage medium according to claim 7, wherein a voltage is output. The main memory bit line decoder includes a sub-decoder electrically connected to the shared bit line. The sub-decoder receives an address signal, a 3-input NAND gate, a 2-input NAND gate, an inverter, One input terminal of the two-input NAND gate is electrically connected to an output terminal of the three-input NAND gate, and the other input terminal of the two-input NAND gate is connected to the shared bit in the additional bit line decoder. In the additional memory bit line decoder, the sub decoder electrically connected to the shared bit line is electrically connected to the output terminal of the 4-input NAND gate of the sub decoder electrically connected to the line. A 4-input NAND gate for receiving a signal and a sign signal, a 2-input NAND gate, and an inverter, wherein one input terminal of the 2-input NAND gate is an output of the 4-input NAND gate The other input terminal of the 2-input NAND gate is electrically connected to the output terminal of the 3-input NAND gate of the sub-decoder that is electrically connected to the shared bit line in the main memory bit line decoder. The non-volatile storage medium according to claim 10, wherein the non-volatile storage medium is connected. The nonvolatile storage medium according to claim 7, wherein the nonvolatile storage medium is a nonvolatile storage medium having a virtual ground array structure. In a control method of a nonvolatile storage medium having a virtual ground array structure, the nonvolatile storage medium includes a main memory array, an additional memory array directly connected to the main memory array, a peripheral circuit area, and the main memory array. The main memory array comprising at least one or more memory cells, a bit line electrically connected to a drain of the memory cells, and A ground line electrically connected to a source of the memory cell, the additional memory array comprising at least one additional memory cell; an additional bit line electrically connected to a drain of the additional memory cell; and And an additional ground line electrically connected to the source of the additional memory cell, and the peripheral circuit region includes the memory. A main memory ground line decoder electrically connected to the ground line of the memory array, an additional memory ground line decoder electrically connected to the additional ground line of the additional memory array, and at least first and second signals A method for controlling a non-volatile storage medium comprising a transmission line and having both ends of each signal transmission line connected to the main memory ground line decoder and the additional memory ground line decoder, respectively, includes the following steps: The main memory ground line decoder is connected via the first signal transmission line when the address arrangement is performed on the common ground line electrically connected to the common doping region using the main memory ground line decoder. A signal is transmitted to the additional memory ground line decoder to determine the voltage of the shared ground line and an electrical connection between the shared ground line and the additional memory ground line decoder. In the case where a circuit open state is subsequently formed and the additional memory bit line decoder is used to place an address on the shared ground line, the additional memory ground line decoder sends a signal to the main signal via a second signal transmission line. A nonvolatile circuit characterized in that a voltage of the common ground line is determined by transmission to a memory ground line decoder, and a circuit open state is formed in an electrical connection between the common ground line and the main memory ground line decoder. Control method for a portable storage medium. In a control method of a nonvolatile storage medium having a virtual ground array structure, the nonvolatile storage medium includes a main memory array, an additional memory array directly connected to the main memory array, a peripheral circuit area, and the main memory array. The main memory array comprising at least one or more memory cells, a bit line electrically connected to a drain of the memory cells, and A ground line electrically connected to a source of the memory cell, and the additional memory array includes at least one additional memory cell and an additional bit line electrically connected to a drain of the additional memory cell; And an additional ground line electrically connected to the source of the additional memory cell, and the peripheral circuit region includes the A main memory ground line decoder electrically connected to the ground line of the in-memory array; an additional memory ground line decoder electrically connected to the additional ground line of the additional memory array; and at least first and second signals A method for controlling a non-volatile storage medium comprising a transmission line and having both ends of each signal transmission line connected to the main memory ground line decoder and the additional memory ground line decoder, respectively, includes the following steps: The main memory ground line decoder is connected via the first signal transmission line when the address arrangement is performed on the common ground line electrically connected to the common doping region using the main memory ground line decoder. The signal is transmitted to the additional memory ground line decoder so that both the common ground line and each sub-decoder are selected and the equivalent voltage is output. In addition, when the additional memory ground line decoder is used to place an address on the shared ground line, the additional memory ground line decoder transmits a signal to the main memory ground line decoder via the second signal transmission line. A control method for a non-volatile storage medium, wherein both the common ground line and the respective sub-decoders are selected and output an equivalent voltage. In a control method of a nonvolatile storage medium having a virtual ground array structure, the nonvolatile storage medium includes a main memory array, an additional memory array directly connected to the main memory array, a peripheral circuit area, and the main memory array. The main memory array comprising at least one or more memory cells, a bit line electrically connected to a drain of the memory cells, and A ground line electrically connected to a source of the memory cell, and the additional memory array includes at least one additional memory cell and an additional bit line electrically connected to a drain of the additional memory cell; And an additional ground line electrically connected to the source of the additional memory cell, and the peripheral circuit region includes the A main memory bit line decoder electrically connected to the bit lines of the in-memory array, an additional memory bit line decoder electrically connected to the additional bit lines of the additional memory array, and at least first and second signals A method for controlling a nonvolatile storage medium comprising a transmission line and having both ends of each signal transmission line connected to the main memory bit line decoder and the additional memory bit line decoder, respectively, includes the following steps: The main memory bit line decoder is connected via the first signal transmission line when the address arrangement is performed on the shared bit line electrically connected to the shared doping region using the main memory bit line decoder. To transmit the signal to the additional memory bit line decoder to And an open circuit is formed in the electrical connection between the shared bit line and the additional memory bit line decoder, and the address arrangement is arranged on the shared bit line using the additional memory bit line decoder. If so, the additional memory bit line decoder transmits a signal to the memory bit line decoder via a second signal transmission line to determine the voltage of the shared bit line, and the shared bit line and the main memory A method for controlling a nonvolatile storage medium, wherein a circuit open state is formed in an electrical connection with a bit line decoder. In a control method of a nonvolatile storage medium having a virtual ground array structure, the nonvolatile storage medium includes a main memory array, an additional memory array directly connected to the main memory array, a peripheral circuit area, and the main memory array. The main memory array comprising at least one or more memory cells, a bit line electrically connected to a drain of the memory cells, and A ground line electrically connected to a source of the memory cell, and the additional memory array includes at least one additional memory cell and an additional bit line electrically connected to a drain of the additional memory cell; And an additional ground line electrically connected to the source of the additional memory cell, and the peripheral circuit region includes the A main memory bit line decoder electrically connected to the bit lines of the in-memory array, an additional memory bit line decoder electrically connected to the additional bit lines of the additional memory array, and at least first and second signals A method for controlling a nonvolatile storage medium comprising a transmission line and having both ends of each signal transmission line connected to the main memory bit line decoder and the additional memory bit line decoder includes the following steps: When the main memory bit line decoder uses the main memory bit line decoder to perform address arrangement on the shared bit line electrically connected to the shared doping region, the main memory bit line decoder is connected via the first signal transmission line. A signal is transmitted to the additional memory bit line decoder so that the shared bit line and each support bit are transmitted. When both of the decoders are selected and output an equivalent voltage, and the additional memory bit line decoder uses the additional memory bit line decoder to perform address allocation on the shared bit line, the additional memory bit line decoder A signal is transmitted to the main memory bit line decoder through a signal transmission line so that both the shared bit line and each sub-decoder are selected and output an equivalent voltage. A method for controlling a nonvolatile storage medium.

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