JP4335263B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP4335263B2 JP4335263B2 JP2007028494A JP2007028494A JP4335263B2 JP 4335263 B2 JP4335263 B2 JP 4335263B2 JP 2007028494 A JP2007028494 A JP 2007028494A JP 2007028494 A JP2007028494 A JP 2007028494A JP 4335263 B2 JP4335263 B2 JP 4335263B2
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- resin layer
- molded resin
- semiconductor chip
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/124—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed the encapsulations having cavities other than that occupied by chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/016—Manufacture or treatment using moulds
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/877—Bump connectors and die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/10—Containers or parts thereof
- H10W76/12—Containers or parts thereof characterised by their shape
- H10W76/15—Containers comprising an insulating or insulated base
- H10W76/153—Containers comprising an insulating or insulated base having interconnections in passages through the insulating or insulated base
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
図1(A)は、実施形態1に係る半導体装置10の概略構成を示す斜視図である。図1(B)は、図1(A)のA−A’線上の断面構造を示す断面図である。半導体装置10は、基板20と、表面をフェイスダウンした状態で基板20にフリップチップ実装された半導体チップ30と、半導体チップ30が実装された基板20の同一面上に、半導体チップ30と離間し、半導体チップ30の周囲に設けられた成型樹脂層40と、半導体チップ30の裏面とTIM層80を介し、成型樹脂層40の上面と接着層82を介して接合されたリッド90とを備える。
図3は、実施形態1の半導体装置の製造方法の概略を示すフロー図である。まず、多層配線構造を有する基板を形成し(S10)、この基板の上に半導体チップを実装する(S20)。続いて、半導体チップと離間した周囲に成型樹脂層を形成する(S30)。次に半導体チップ裏面とTIM層を介し、成型樹脂層の上面と接着層を介してリッドを接着する(S40)。最後にハンダボール、キャパシタなどを基板の裏面に実装する(S50)。
図4は、実施形態1の半導体装置10の半導体チップ30の実装方法を示す工程断面図である。
図5および図6は、実施形態1の半導体装置10の成型樹脂層の形成方法を示す工程図である。
図7は、実施形態1の半導体装置10のリッド接着方法を示す工程図である。
図8(A)は、実施形態2に係る半導体装置11の断面構造を示している。また、実施形態2に係る半導体装置11の説明において、実施形態1に係る半導体装置10と同様な構成については適宜省略し、実施形態1に係る半導体装置10と異なる構成について説明する。
図8(B)は、実施形態3に係る半導体装置12の断面構造を示している。また、実施形態3に係る半導体装置12の説明において、実施形態2に係る半導体装置11と同様な構成については適宜省略し、実施形態2に係る半導体装置11と異なる構成について説明する。
Claims (6)
- 基板と、
表面をフェイスダウンした状態で前記基板に実装された半導体チップと、
前記半導体チップが実装された前記基板の同一面上に、前記半導体チップと離間し、前記半導体チップの周囲に設けられた成型樹脂層と、
前記半導体チップの熱を放熱するための冷却部材と、
前記冷却部材と前記成型樹脂層の上面を接着する接着層と、
前記半導体チップの裏面と前記冷却部材を熱的に接続する熱インターフェース材料層と、
を備え、
前記成型樹脂層の上面に凹部が設けられていることを特徴とする半導体装置。 - 前記成型樹脂層の上面は、前記半導体チップの裏面よりも上方に位置することを特徴とする請求項1に記載の半導体装置。
- 前記成型樹脂層の上面と同一平面における前記凹部の開口部の面積は、前記成型樹脂層の上面の面積よりも大きいことを特徴とする請求項1または2に記載の半導体装置。
- 前記接着層が、前記凹部内に設けられていることを特徴とする請求項1から3のいずれか1項に記載の半導体装置。
- 前記成型樹脂層の上面に前記凹部と前記成型樹脂層の側面を連通する流出路が設けられており、
前記流出路の底部が、前記凹部の底部よりも上方に位置することを特徴とする請求項1から4のいずれか1項に記載の半導体装置。 - 配線パターンが設けられた基板に表面をフェイスダウンした半導体チップをフリップチップ実装する工程と、
前記半導体チップが実装された前記基板の同一面上に、前記半導体チップと離間し、前記半導体チップの周囲に位置する成型樹脂層を成型するための工程と、
前記成型樹脂層の上面に接着層を形成する工程と、
前記半導体チップの裏面に熱インターフェース材料層を形成する工程と、
前記半導体チップの熱を放熱するための冷却部材を、前記成型樹脂層に対して前記接着層を介して接着するとともに前記熱インターフェース材料層と熱的に接続する工程と、
を備え、
前記成型樹脂層を成型するための工程において、前記成型樹脂層の上面に凹部を設けることを特徴とする半導体装置の製造方法。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007028494A JP4335263B2 (ja) | 2007-02-07 | 2007-02-07 | 半導体装置および半導体装置の製造方法 |
| US11/968,840 US20080185712A1 (en) | 2007-02-07 | 2008-01-03 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007028494A JP4335263B2 (ja) | 2007-02-07 | 2007-02-07 | 半導体装置および半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008192996A JP2008192996A (ja) | 2008-08-21 |
| JP4335263B2 true JP4335263B2 (ja) | 2009-09-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007028494A Expired - Fee Related JP4335263B2 (ja) | 2007-02-07 | 2007-02-07 | 半導体装置および半導体装置の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20080185712A1 (ja) |
| JP (1) | JP4335263B2 (ja) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8384223B2 (en) * | 2008-06-30 | 2013-02-26 | Intel Corporation | Backside mold process for ultra thin substrate and package on package assembly |
| US9275949B2 (en) | 2011-06-01 | 2016-03-01 | Canon Kabushiki Kaisha | Semiconductor device |
| US10020236B2 (en) * | 2014-03-14 | 2018-07-10 | Taiwan Semiconductar Manufacturing Campany | Dam for three-dimensional integrated circuit |
| CN109716745B (zh) * | 2016-08-01 | 2020-12-18 | 宁波舜宇光电信息有限公司 | 摄像模组及其模塑电路板组件和模塑感光组件和制造方法 |
| WO2019066989A1 (en) * | 2017-09-30 | 2019-04-04 | Intel Corporation | INTEGRATED SUBSTRATE AMOUNTS AND HEAT DIFFUSER CUSTOMIZATION FOR ENHANCED PACKAGING THERMOMECHANICS |
| WO2021106114A1 (ja) * | 2019-11-27 | 2021-06-03 | 三菱電機株式会社 | 半導体モジュール |
| DE102020131849B4 (de) | 2020-12-01 | 2025-06-12 | Infineon Technologies Ag | Chip-Package, Halbleiteranordnung, Verfahren zum Bilden eines Chip-Packages, und Verfahren zum Bilden einer Halbleiteranordnung |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4929965A (en) * | 1987-09-02 | 1990-05-29 | Alps Electric Co. | Optical writing head |
| JPH0671061B2 (ja) * | 1989-05-22 | 1994-09-07 | 株式会社東芝 | 樹脂封止型半導体装置 |
| DE19638667C2 (de) * | 1996-09-20 | 2001-05-17 | Osram Opto Semiconductors Gmbh | Mischfarbiges Licht abstrahlendes Halbleiterbauelement mit Lumineszenzkonversionselement |
| JP2002270638A (ja) * | 2001-03-06 | 2002-09-20 | Nec Corp | 半導体装置および樹脂封止方法および樹脂封止装置 |
| US6509696B2 (en) * | 2001-03-22 | 2003-01-21 | Koninklijke Philips Electronics N.V. | Method and system for driving a capacitively coupled fluorescent lamp |
| TW521410B (en) * | 2001-11-15 | 2003-02-21 | Siliconware Precision Industries Co Ltd | Semiconductor package article |
| US8174114B2 (en) * | 2005-12-15 | 2012-05-08 | Taiwan Semiconductor Manufacturing Go. Ltd. | Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiency |
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2007
- 2007-02-07 JP JP2007028494A patent/JP4335263B2/ja not_active Expired - Fee Related
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2008
- 2008-01-03 US US11/968,840 patent/US20080185712A1/en not_active Abandoned
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| Publication number | Publication date |
|---|---|
| US20080185712A1 (en) | 2008-08-07 |
| JP2008192996A (ja) | 2008-08-21 |
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